Analog Devices EE260v01 Application Notes

Engineer-to-Engineer Note EE-260

a

Technical notes on using Analog Devices DSPs, processors and development tools

Contact our technical support at [e-mail] and at [e-mail]
Or vi sit our o n-li ne r esou rces htt p:/ /www.analog.com/ee-notes and http://www.analog.com/processors

Interfacing AD7865 Parallel ADCs to ADSP-2136x SHARC® Processors

Contributed by Aseem Vasudev Prabhugaonkar and Jagadeesh Rayala Rev 1 – December 17, 2004

Introduction

This application note explains how to interface
parallel ADCs to ADSP-21365 SHARC®
processors. The parallel ADC considered in this
application note is the AD7865. The two
schemes described in this application note to
interface an AD7865 with an ADSP-21365 are
the parallel port interface and the parallel data
acquisition port (PDAP) interface. This
application note also provides example code to
demonstrate how the SHARC processor’s
parallel port and PDAP can be programmed to
receive data from an AD7865 in DMA mode.

About AD7865 ADCs

The AD7865 is a fast, low-power, four-channel
simultaneous sampling 14-bit A/D converter that
operates from a single 5 V supply. The device
contains a 2.4 µs successive approximation
ADC, four track/hold amplifiers, 2.5 V reference,
on-chip clock oscillator, signal conditioning
circuitry, and a high-speed parallel interface. The
input signals on four channels are sampled
simultaneously. This preserves the relative phase
information of the signals on the four analog
inputs.

The device allows any subset of the four
channels to be converted, maximizing the
throughput rate on the selected sequence. The
channels to be converted can be selected via
hardware (channel select input pins) or via
software (programming the channel select
register).

Copyright 2004, Analog Devices, Inc. All rights reserved. Analog Devices assumes no responsibility for customer product design or the use or application of
customers’ products or for any infringements of patents or rights of others which may result from Analog Devices assistance. All trademarks and logos are property
of their respective holders. Information furnished by Analog Devices applications and development tools engineers is believed to be accurate and reliable, however
no responsibility is assumed by Analog Devices regarding technical accuracy and topicality of the content provided in Analog Devices’ Engineer-to-Engineer Notes.

The high-speed parallel interface also allows
interfacing to 3 V processors.

AD7865 Product Highlights

 The AD7865 features four track/hold

amplifiers and a fast (2.4 µs) ADC, allowing
simultaneous sampling and conversion of any
subset of the four channels.

 The AD7865 operates from a single 5 V

supply and consumes only 115 mW (typical),
making it ideal for low-power and portable
applications.

 The AD7865 offers a high-speed parallel

interface for easy connection to
microprocessors, microcontrollers, and
digital signal processors.

 The AD7865 is offered in three versions,

each with different analog input ranges. The
AD7865-1 offers the standard industrial
ranges of ±10 V and ±5 V; the AD7865-2
offers a unipolar range of 0 V to 2.5 V (or
0 V to 5 V); and the AD7865-3 offers the
common signal processing input range of
±2.5 V.

 The device features very tight aperture delay

matching between the four input sample and
hold amplifiers.

AD7865 ADC Applications

AD7865 applications include:

 AC motor control

a

 Uninterruptible power supplies
 Industrial power meters/monitors
 Data acquisition systems
 Communications

About ADSP-21365 Processors

The third generation of SHARC processors,
which includes the ADSP-21262, ADSP-21266,
ADSP-21267, ADSP-21364, and ADSP-21365
derivatives, offers increased performance, audio
and application-focused peripherals, and new
memory configurations capable of supporting the
latest surround-sound decoder algorithms. All
devices are pin compatible and are completely
code compatible with all prior SHARC
processors. The newest members of the SHARC
family are based on a single-instruction,
multiple-data (SIMD) core, which supports both
32-bit fixed-point and 32-/40-bit floating-point
arithmetic formats, making them particularly
suitable for high-performance audio applications.

The ADSP-21365 derivative offers the highest
performance – 300 MHz / 1800 MFLOPs. This
level of performance makes the ADSP-21365
particularly well suited to address the increasing
requirements of the professional and automotive
audio market segments. In addition to its high­performance core, the ADSP-21365 includes
additional value-added peripherals such as an
S/PDIF transmitter/ receiver, 8-channel
asynchronous sample rate converter, and
hardware digital transmission content protection
(DTCP) encryption/ decryption block.

Third-generation SHARC processors also
integrate application-specific peripherals that
simplify hardware design, minimize design risks,
and ultimately reduce time to market. Grouped
together and broadly named the digital audio
interface (DAI), these functional blocks may be
connected to each other or to external pins via
the software programmable signal routing unit
(SRU). The SRU is an innovative architectural
feature that enables complete and flexible routing

among DAI blocks. Peripherals connected
through the SRU include (but are not limited to)
SPORTs, SPI ports, S/PDIF Tx/Rx, DTCP
accelerator, and an 8-channel asynchronous
sample rate converter block.

Interfacing AD7865 via Parallel Port

This application note employs a high-speed
parallel 14-bit ADC for the interface. A single
conversion start signal (
places all the track/holds into hold mode and
initiates the conversion sequence for the selected
channels. The /EOC signal indicates the end of
each individual conversion in the selected
conversion sequence. The BUSY signal indicates
the end of the conversion sequence. Data is read
from the AD7865 via a 14-bit parallel data bus
using its /CS and /RD signals. All four ADC
channels are selected in hardware. When the

H#/S SEL pin is a logic 0, the AD7865

conversion sequence selection is controlled via
the SL1–SL4 input pins and uses an internal
clock.

For the sake of simplicity in this application
note, the flag pin (FLG0) has been used to select
the /CS of the AD7865 instead of the entire
Address latch and decode logic (refer to the blue
ellipse in Figure 1). The address latch and
address decode logic is required in any practical
system where multiple devices like memory, I/O
devices, and so on share the processor’s parallel
port.

Refer to the functional block diagram in Figure 1
for interfacing details.

/CONVST) simultaneously

Interfacing AD7865 Parallel ADCs to ADSP-2136x SHARC® Processors (EE-260) Page 2 of 7

a

ADSP-21365

AD0-AD15

FSx

ALE

/IRQx

Figure 1. Functional Block Diagram – ADSP-21365
and AD7865 Interface via Parallel Port

/CONVST

Addr
Latch
and
decoder
logic

/CS

Data

/RD /RD

AD7865-3

DB0­DB13

BUSY

A low-to-high transition on the /CONVST input
places all of the track/holds into hold mode and
starts conversion on the selected channels. Frame
sync of SPORT0 is used to generate a

/CONVST

signal for the ADC. The serial port is configured
to transmit with frame sync as data independent
frame sync. The SPORT frame sync frequency is
determined by the value loaded in the DIV0
register. An initial dummy write to the SPORT

TXSP0A register is required to start continuous

frame sync on the FS0 signal. The BUSY signal
from AD7865 indicates the end of conversion on

all the selected ADC channels. The falling edge
of BUSY triggers an interrupt. The interrupt is
configured to be edge sensitive. Parallel port
DMA is configured in the interrupt service
routine and the DMA is initiated.

The ADSP-21365 parallel port must be
configured for a 16-bit mode. Two received 16­bit words are packed and transferred to the
internal memory as a single 32-bit word;
therefore, the DMA completion status is checked
to verify the completion of DMA and data re­arrangement is carried out before exiting the
external interrupt (IRQ1) service routine. The
external address modifier (EMPP) value used in
the example code is “1”; however, an external
address modifier of “0” can be used as a special
case for reading FIFOs, offering higher
throughput.

Refer to the timing diagram in Figure 2 for
reading after the conversion sequences. Figure 3
shows a screen capture of various signals.

Figure 2. Timing Diagram, Reading After the Conversion Sequences

Interfacing AD7865 Parallel ADCs to ADSP-2136x SHARC® Processors (EE-260) Page 3 of 7