Analog Devices EE254v01 Application Notes

Engineer-to-Engineer Note EE-254

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Interfacing ADSP-21365 SHARC® PDAP to ADSP-BF533 Blackfin®
EBIU

Contributed by Srinivas K. and Kunal Singh Rev 1 – November 12, 2004

Introduction

ADSP-21365 devices belong to the third
generation of SHARC® processors. ADSP­21365 processors offer a very high bandwidth
(up to 1 Gbps) input data port for data
acquisition, called Parallel Data Acquisition Port
(PDAP).

The PDAP supports the acquisition of data from
an external device with different word lengths.
The received data is packed automatically into
32-bit words. The various word lengths formats
supported by PDAP include, 2x16-bit (mode 01),
4x8-bit (mode 00), 10-11-11-bit (mode 10), and
20-bit (mode 11). In 20-bit mode, the received
data bits are mapped to the highest 20 bits of the
32-bit word. The lowest 12 bits of the 32-bit
word are assumed to be zero.

The ADSP-BF533 Blackfin® family of
processors (including the ADSP-BF531 and
ADSP-BF532 derivatives) features an External
Bus Interface Unit (EBIU) which provides
interface to the external memory devices. The
EBIU supports interface for the synchronous and
asynchronous memory banks. The data bus on
the ADSP-BF533 EBIU is 16 bits wide.

This EE-Note discusses a hardware interface
scheme between the ADSP-21365 PDAP port
and the EBIU interface on an ADSP-BF532
processor. Since the EBIU is 16 bits wide, the
interface uses the PDAP in 2x16-bit format.
However, the 4x8-bit and 10-11-11-bit formats

can also be implemented with minor
modifications to the software.

To implement a handshake protocol, the
proposed interface uses programmable flags and
interrupts available on the two devices.

Since the PDAP is a unidirectional input-only
port, the data can be transferred only from the
ADSP-BF532 processor to the ADSP-21365
PDAP (that is, not from the PDAP to the
Blackfin processor).

PDAP

The PDAP interface on ADSP-21365 SHARC
processors consists of 20 PDAP data pins, a
clock signal (PDAP_CLK), and a data valid signal
(PDAP_HOLD). A rising or falling edge of the
clock can latch the data (on the data pins) into
the PDAP receive buffers (a 6-deep FIFO). The
active edge of the clock is defined by the status
of the IDP_PDAP_CLKEDGE bit in the PDAP
control register.

PDAP_HOLD signal is used to qualify a valid

The
clock signal. The clock is considered to be valid
if PDAP_HOLD is low in that particular clock
cycle. Data on the PDAP port is acquired during
every valid clock cycle.

Figure 1 depicts the data transfer protocol on

PDAP port, when the port has been configured
for the activity on the falling edge of the

PDAP_CLK.

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The data from the PDAP receive FIFO can be
transferred to the internal memory of the
processor using core-based transfers or DMA­based transfers. DMA transfers are completely
transparent to the core.

The maximu m CLK rate for the PDAP is 50 MHz.
Hence, the maximum data bandwidth (1 Gbps) is
achieved when the PDAP is configured for 20-bit
transfers. However, since the EBIU on Blackfin
processors is only 16 bits wide, the 20-bit mode
cannot be used for the given interface.

PDAP_CLK

PDAP_HOLD

PDAP_DATA

Data will not be clocked on this clock cycle since the PDAP_HOLD
signal is de-asserted

Figure 1. PDAP Port Data Transfer Protocol

As discussed before, the PDAP can be interfaced
with the EBIU in mode 00, mode 01, or mode 10.
The example software provided with this EE­Note covers the interface in mode 01 only.

Introduction to the Blackfin EBIU

Introduction to Interrupt and Flags Signals

The given interface uses THE Interrupt signals
and the GPIO flags available on the two devices
as the handshake control signals.

The ADSP-21365 processor has three external
asynchronous interrupts (IRQ0-2). The IRQx
interrupts can be configured to be level-sensitive
or edge-sensitive. The given interface uses the

IRQ0 signal as an edge-sensitive interrupt.

ADSP-21365 SHARC processors feature 16
GPIO flags, which are available through the DAI
pins. The flags can be configured as inputs to the
processor or as outputs from the processor. The
given interface uses the FLAG0 signal in output
mode.

ADSP-BF532 processors feature 16
programmable flags (PF0-PF15.). Each PFx
signal can be configured individually as an input
or an output. When the PFx signal is configured
as an input, it can be programmed to function as
an asynchronous interrupt signal to the
processor. The interrupt can be level-sensitive or
edge-sensitive.

The given interface uses the processor's PF4 and

PF6 signals. The given example also uses the PF5

signal as a user request to initiate a data transfer
request. The functionality of PF5 has been added
only for the purpose of testing. In the actual
interface, only

PF4 and PF6 are utilized.

The External Bus Interface Unit (EBIU) on
Blackfin processors provides interface to
external memory devices. The EBIU services
requests for external memory in core mode or in
DMA mode. Based on the address of the
requested accesses, the accesses are controlled
by the SDRAM controller or by the
Asynchronous Memory Controller. The EBIU is
clocked by the system clock (

SCLK).

The PF4 signal on the ADSP-BF532 processor is
defined as an output

IRQ0 of the ADSP-21365 processor. PF4 is used

FLAG. PF4 is connected to

by the ADSP-BF532 processor to request the
ADSP-21365 processor for the initiation of a
data transfer.

PF6 is configured as an edge-sensitive interrupt

and is used as an acknowledge signal from the
ADSP-21365 processor in response to a data
transfer request.

In the given example code, the PF5 signal is
used as an edge-sensitive interrupt to initiate a

Interfacing ADSP-21365 SHARC® PDAP to ADSP-BF533 Blackfin® EBIU (EE-254) Page 2 of 16

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data transfer sequence on the ADSP-BF532
processor. In a real system, the data initiation
request may come from a device in the system or
from the ADSP-BF532 processor itself.

PDAP to EBIU Interface

Figure 2 depicts the hardware interface scheme

between the SHARC PDAP and the Blackfin
EBIU.

The PDAP signals (data, clock, and hold) on
ADSP-21365 processors are available through
the SRU. In mode 00, Data[15..0] are mapped
to DAI_PIN20..5. The clock and hold signals
can be mapped to any of DAI pins 1..4. The
given example uses DAI_PIN 01 and 03,
respectively, for the clock and hold signals.

ADSP-21365 ADSP-BF532

Figure 2. Hardware Interface for PDAP and Blackfin

The ADSP-BF532 processor offers different
memory banks (with individual memory select
signals
devices to be mapped to ADSP-BF532
processors. The PDAP can be mapped to the
ADSP-BF532 processor as one asynchronous
memory device. The given example maps the
PDAP port to the external asynchronous memory
bank-0 of ADSP-BF532 processor. Therefore,

/AMS0 is connected to PDAP_HOLD. Thus, /AMS0

is used to validate the
the

SCLK of the ADSP-BF532.

While implementing the above interface, ensure
that the
of one

SCLK cycle only for a single data transfer.

PDAP_CLK
PDAP_DATA
PDAP_HOLD

IRQ0

FLAG0

/AMSx), allowing multiple memory

PDAP_CLK, which in turn is

/AMSx signal is asserted for the duration

SCLK
DATA15..0
AMS0

PF4
PF6
PF5

This requirement arises from the fact that, if the

/AMSx

signal (mapped to PDAP_HOLD) is asserted
for more than one clock cycle, the same data
would be clocked into the PDAP FIFO, more than
once.

Data Transfer Protocol for the Interface

In the above interface all data transfers are
controlled by software running on the ADSP­21365 and ADSP-BF532 processors.

A data transfer operation from the Blackfin
processor to the SHARC processor consists of
two phases, which are completely implemented
in software:

 Command_Phase: The ADSP-BF532

processor passes the various control
parameters (e.g., number of data words,
internal memory address for the ADSP­21365 processor where the data has to be
stored, and so on). In the given example
code, the ADSP-21365 processor uses the
above control words as DMA parameters for
the PDAP DMA. The example software can
be modified to include additional control
variable (e.g., PDAP mode, DMA modifier,
and so on).

 Data_Phase: After receiving the control

parameters from the ADSP-BF532 processor,
the ADSP-21365 processor configures its
PDAP port for the data transfers.

Synchronization Between the
ADSP-21365 Processors and the
ADSP-BF532 Processors

ADSP-BF532 Blackfin processor can initiate
data transfers by requesting a transfer from the
ADSP-21365 processor. The ADSP-BF532
processor software achieves this by generating an
interrupt signal (
processor through its PF4 pin.

IRQ0) for the ADSP-21365

Interfacing ADSP-21365 SHARC® PDAP to ADSP-BF533 Blackfin® EBIU (EE-254) Page 3 of 16

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The ADSP-21365 processor will jump to the

IRQ0 interrupt service routine. Inside the ISR, if

a earlier data transfer operation (requested by the
ADSP-BF532 processor) is not pending, the
ADSP-21365 processor will configure the
PDAP port to receive control words from the
ADSP-BF532 processor. After configuring the
PDAP port, the ADSP-21365 processor would
pass an acknowledgement to the ADSP-BF532
processor by asserting FLAG0.

A rising edge on FLAG0 causes the ADSP-BF532
processor to interrupt its program execution and
respond to the interrupt request on PF6 (which
has been mapped to

IVG12, the ADSP-BF532 processor will transfer

the control words to the ADSP-21365 processor
through its EBIU.

Upon receiving the control words, the ADSP­21365 processor processes the PDAP DMA
"over" interrupt. Inside the interrupt service
routine, the ADSP-21365 processor re­configures the PDAP for data transfers. The
DMA parameters are configured, based on the
control words received. After the PDAP is
configured the ADSP-21365 processor passes an
acknowledgement to the ADSP-BF532 processor
again (through FLAG0), instructing the ADSP­BF532 processor to perform the data transfer
operations.

It is interesting to note that the same pins (
and PF6) are used as the acknowledgement signal
to start the
The ADSP-BF532 processor identifies the
operation to be performed (whether to transfer
data or control words), based on flag variables
maintained by the software running on the
ADSP-BF532 processor.

command_phase and data_phase.

IVG12). Inside the ISR for

FLAG0

Driver Software for ADSP-21365 SHARC Processors

The ADSP-21365 processor would receive a new
data transfer request from the ADSP-BF532
processor through the IRQ0 signal. If a new
request is received while an old request is

pending, the ASDP-21365 processor considers
the new request to be invalid and does not
respond to the new request. In a real-time
system, a corrective action must be taken when
an invalid request is identified.

When a valid data request from an ADSP-BF532
processor is encountered, the ADSP-21365
processor initiates the command_phase. The

command_phase involves passing control

parameters (memory index and DMA count for
the data transfers) from the ADSP-BF532
processor to ADSP-21365 processor. The ADSP­21365 processor would configure the PDAP
DMAs to receive the control words from the
ADSP-BF532 processor. In the given code
example, only memory index and DMA count
values are passed as control parameters.
However, the given example can be extended to
pass more parameters, such as DMA modifier,
PDAP mode, and so on.

After configuring the PDAP in DMA mode to
receive control words, the ADSP-21365
processor passes an acknowledgement to the
ADSP-BF532 processor.

The PDAP DMA "over" interrupt is generated
upon completion of the command_phase. The
ADSP-21365 processor reads these control
parameters and re-configures the PDAP for the

data_phase. Again, an acknowledgement is

passed to the ADSP-BF532 processor to initiate
the data_phase. The ADSP-BF532 processor
responds to the acknowledgement by sending the
actual data.

Driver Software for ADSP-BF532 Blackfin Processors

As discussed, ADSP-BF532 processors can
initiate a data transfer sequence by generating

IRQ0 for ADSP-21365 processors. In the given

example, you can initiate data transfers by
interrupting the ADSP-BF532 processor through

PF5, which has been configured as an edge-

triggered interrupt. In the given example code,

Interfacing ADSP-21365 SHARC® PDAP to ADSP-BF533 Blackfin® EBIU (EE-254) Page 4 of 16

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you are asked to pass the control parameters
(DMA parameters) through VisualDSP++ I/O
(Output window's Console page). However, in a
real-time system, the control parameters arise
from the ADSP-BF532 processor. After
receiving the control words from the console, the
ADSP-BF532 processor requests the ADSP­21365 processor to initiate a data transfer
sequence by interrupting the ADSP-21365
processor by PF4. The ADSP-BF532 processor
sets the request_flag and command_flag
before asserting PF0. If all of the previous data
transfers have been completed, the ADSP-21365
processor responds to the request with an
acknowledge signal.

When an acknowledgement is received, the
ADSP-BF532 processor checks for the

command_flag and request_flag.

 If both these variables are set, a command

phase is initiated which involves writing the
control parameters through the EBIU. The

command_flag is cleared after completing the

command phase.

 If request_flag is set and the

command_flag is cleared, the ADSP-BF532

processor initiates the data transfer phase
which involves writing the actual data block
to the PDAP through EBIU.

 If request_flag is cleared, no action is

taken.

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