Analog Devices DA7870AJN Datasheet

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a

AD7870A

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1997

LC2MOS

Complete, 12-Bit, 100 kHz , Sampling ADC

FUNCTIONAL BLOCK DIAGRAM

FEATURES
Complete Monolithic 12-Bit ADC with:

2 ms Track/Hold Amplifier
8 ms A/D Converter
On-Chip Reference
Laser-Trimmed Clock

Parallel, Byte and Serial Digital Interface
70 dB SNR at 10 kHz Input Frequency
57 ns Data Access Time
Low Power—60 mW typ

APPLICATIONS
Digital Signal Processing
Speech Recognition and Synthesis
Spectrum Analysis
High Speed Modems
DSP Servo Control

GENERAL DESCRIPTION

The AD7870A is a fast, complete, 12-bit A/D converter. It con­sists of a track/hold amplifier, 8 µs successive approximation
ADC, 3 V buried Zener reference and versatile interface logic.
The ADC features a self-contained internal clock that is laser
trimmed to guarantee accurate control of conversion time. No
external clock timing components are required; the on-chip
clock may be overridden by an external clock if required.

AD7870A offers a choice of three data output formats: a single,
parallel, 12-bit word, two 8-bit bytes or serial data. Fast bus
access times and standard control inputs ensure easy interfacing
to modern microprocessors and digital signal processors.

The AD7870A operates from ± 5 V power supplies, accepts
bipolar input signals of ± 3 V and can convert full power signals
up to 50 kHz.

In addition to the traditional dc accuracy specifications such as
linearity, full-scale and offset errors, the AD7870A is also fully
specified for dynamic performance parameters including har­monic distortion and signal-to-noise ratio.

The AD7870A is fabricated in Analog Devices’ linear compati­ble CMOS (LC

2

MOS) process, a mixed technology process that
combines precision bipolar circuits with low power CMOS logic.
The part is available in a 24-pin, 0.3-inch wide, plastic dual in­line package (DIP).

PRODUCT HIGHLIGHTS

1. Complete 12-bit ADC on a chip.
The AD7870A is the most complete monolithic ADC avail­able and combines a 12-bit ADC with internal clock, track/
hold amplifier and reference on a single chip.

2. Dynamic specifications for DSP users.
The AD7870A is fully specified and tested for ac parameters,
including signal-to-noise ratio, harmonic distortion and inter­modulation distortion. Key digital timing parameters are also
tested and guaranteed over the full operating temperature
range.

3. Fast microprocessor interface.
Data access times of 57 ns make the AD7870A compatible
with modern 8- and 16-bit microprocessors and digital signal
processors.

AD7870A–SPECIFICATIONS

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(VDD = +5 V 6 5%, VSS = –5 V 6 5%, AGND = DGND = 0 V, f

CLK

is internal, unless

otherwise noted. All specifications T

MIN

to T

MAX

unless otherwise noted.)

Parameter J

1

Units Test Conditions/Comments

DYNAMIC PERFORMANCE

2

Signal-to-Noise Ratio3 (SNR)

@ +25°C 70 dB min V

IN

= 10 kHz Sine Wave, f

SAMPLE

= 100 kHz

T

MIN

to T

MAX

70 dB min Typically 71.5 dB for 0 < VIN ≤ 50 kHz

Total Harmonic Distortion (THD) –80 dB max V

IN

= 10 kHz Sine Wave, f

SAMPLE

= 100 kHz

Typically –86 dB for 0 < V

IN

< 50 kHz

Peak Harmonic or Spurious Noise –80 dB max V

IN

= 10 kHz, f

SAMPLE

= 100 kHz

Typically –86 dB for 0 < V

IN

< 50 kHz

Intermodulation Distortion (IMD)

Second Order Terms –80 dB max fa = 9 kHz, fb = 9.5 kHz, f

SAMPLE

= 50 kHz

Third Order Terms –80 dB max fa = 9 kHz, fb = 9.5 kHz, f

SAMPLE

= 50 kHz

Track/Hold Acquisition Time 2 µs max

DC ACCURACY

Resolution 12 Bits
Minimum Resolution for Which

No Missing Codes Are Guaranteed 12 Bits

Integral Nonlinearity ±1/2 LSB typ
Bipolar Zero Error ±5 LSB max
Positive Full-Scale Error

4

±5 LSB max

Negative Full-Scale Error

4

±5 LSB max

ANALOG INPUT

Input Voltage Range ±3 Volts
Input Current ±500 µA max

REFERENCE OUTPUT

REF OUT @ +25°C 2.99 V min

3.01 V max

REF OUT Tempco ±60 ppm/°C max

Reference Load Sensitivity (∆REF OUT/∆I) ±1 mV max Reference Load Current Change (0 µA–500 µA)

Reference Load Should Not Be Change During Conversion

LOGIC INPUTS

Input High Voltage, V

INH

2.4 V min VDD = 5 V ± 5%

Input Low Voltage, V

INL

0.8 V max VDD = 5 V ± 5%

Input Current, I

IN

±10 µA max VIN = 0 V to V

DD

Input Current (12/8 CLK Input Only) ±10 µA max VIN = VSS to V

DD

Input Capacitance, C

IN

5

10 pF max

LOGIC OUTPUTS

Output High Voltage, V

OH

4.0 V min I

SOURCE

= 40 µA

Output Low Voltage, V

OL

0.4 V max I

SINK

= 1.6 mA

DB11–DB0

Floating State Leakage Current ±10 µA max
Floating-State Output Capacitance

5

15 pF max

CONVERSION TIME

External Clock (f

CLK

= 2.5 MHz) 7.6/8 µs min/µs max

Internal Clock 8/10 µs min/µs max

POWER REQUIREMENTS

V

DD

+5 V V nom ±5% for Specified Performance

V

SS

–5 V non ±5% for Specified Performance

I

DD

13 mA max Typically 8 mA

I

SS

6 mA max Typically 4 mA

Power Dissipation 95 mW max Typically 60 mW

NOTES

1

Temperature range is as follow: J Version: 0°C to +70°C.

2

V

IN

(pk-pk) = ±3 V.

3

SNR calculation includes distortion and noise components.

4

Measured with respect to internal reference and includes bipolar offset error.

5

Sample tested @ +25°C to ensure compliance.

Specifications subject to change without notice.

AD7870A

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TIMING CHARACTERISTICS

1, 2

(VDD = +5 V 6 5%, VSS = –5 V 6 5%, AGND = DGND = 0 V. See Figures 9 and 10.)

Limit at T

MIN

, T

MAX

Parameter (J Version) Units Conditions/Comments

t

1

50 ns min CONVST Pulse Width

t

2

0 ns min CS to RD Setup Time (Mode 1)

t

3

60 ns min RD Pulse Width

t

4

0 ns min CS to RD Hold Time (Mode 1)

t

5

70 ns max RD to INT Delay

t

6

3

57 ns max Data Access Time after RD

t

7

4

5 ns min Bus Relinquish Time after RD
50 ns max

t

8

0 ns min HBEN to RD Setup Time

t

9

0 ns min HBEN to RD Hold Time

t

10

100 ns min SSTRB to SCLK Falling Edge Setup Time

t

11

5

370 ns min SCLK Cycle Time

t

12

6

135 ns max SCLK to Valid Data Delay. CL = 35 pF

t

13

100 ns min SCLK Rising Edge to SSTRB

t

14

10 ns min Bus Relinquish Time after SCLK
100 ns max

NOTES

1

Timing specifications in bold print are 100% production tested. All other times are sample tested at +25 °C to ensure compliance. All input signals are specified with
tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

2

Serial timing is measured with a 4.7 kΩ pull-up resistor on SDATA and SSTRB and a 2 kΩ pull-up on SCLK. The capacitance on all three outputs is 35 pF.

3

t6 is measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.

4

t7 is defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.

5

SCLK mark/space ratio (measured from a voltage level of 1.6 V) is 40/60 to 60/40.

6

t6 SDATA will drive higher capacitive loads but this will add to t12 since it increases the external RC time constant (4.7 kΩiCL) and hence the time to reach 2.4 V.

Specifications subject to change without notice.

a. High-Z to V

OH

b. High-Z to V

OL

Figure 1. Load Circuits for Access Time

a. VOH to High-Z b. VOL to High-Z

Figure 2. Load Circuits for Output Float Delay

AD7870A

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WARNING!

ESD SENSITIVE DEVICE

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7870A features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

ABSOLUTE MAXIMUM RATINGS*

VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

V

SS

to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V

AGND to DGND . . . . . . . . . . . . . . . . . –0.3 V to V

DD

+0.3 V

V

IN

to AGND . . . . . . . . . . . . . . . . . . . . . . . . .–15 V to +15 V

REF OUT to AGND . . . . . . . . . . . . . . . . . . . . . . . 0 V to V

DD

Digital Inputs to DGND . . . . . . . . . . . . –0.3 V to VDD +0.3 V

Digital Outputs to DGND . . . . . . . . . . . –0.3 V to V

DD

+0.3 V

Operating Temperature Range

Commercial (J Version) . . . . . . . . . . . . . . . . . . . 0°C to +70°C

ORDERING GUIDE

Relative

Temperature SNR Accuracy Package

Model Range (dBs) (LSB) Option*

AD7870AJN 0°C to +70°C 70 min ± 1/2 typ N-24

*N = Plastic DIP.

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . .+300°C

Power Dissipation (Any Package) to +75°C . . . . . . . 450 mW

Derates above +75°C by . . . . . . . . . . . . . . . . . . . . 10 mW/°C

*Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

PIN CONFIGURATION

DIP