ANALOG DEVICES AD9042 Service Manual

12-Bit, 41 MSPS

A

FEATURES

41 MSPS minimum sample rate
80 dB spurious-free dynamic range
595 mW power dissipation
Single 5 V supply
On-chip track-and-hold (T/H) and reference
Twos complement output format
CMOS-compatible output levels

APPLICATIONS

Cellular/PCS base stations
GPS anti jamming receivers
Communications receivers
Spectrum analyzers
Electro-optics
Medical imaging
AT E

GENERAL DESCRIPTION

The AD9042 is a high speed, high performance, low power,
monolithic 12-bit analog-to-digital converter (ADC). All
necessary functions, including track-and-hold (T/H) and
reference, are included on chip to provide a complete conversion
solution. The AD9042 operates from a single 5 V supply and
provides CMOS-compatible digital outputs at 41 MSPS.

Designed specifically to address the needs of wideband, multi­channel receivers, the AD9042 maintains 80 dB spurious-free
dynamic range (SFDR) over a bandwidth of 20 MHz. Noise
performance is also exceptional; typical signal-to-noise ratio
(SNR) is 68 dB.

The AD9042 is built on a high speed complementary bipolar
process (XFCB) used by Analog Devices, Inc., and uses an
innovative multipass architecture. Units are packaged in a
44-lead LQFP low profile quad flat package. The AD9042

Monolithic ADC

AD9042

FUNCTIONAL BLOCK DIAGRAM

V

CC

AIN

V

OFFSET

V

REF

ENCODE
ENCODE

2.4V

REFERENCE

INTERNAL

TIMING

GND

ADC

MSB LSB

industrial grade is specified from −40°C to +85°C. However,
the AD9042 was designed to perform over the full military
temperature range (−55°C to +125°C); consult the factory for
military grade product options.

PRODUCT HIGHLIGHTS

1. Guaranteed sample rate is 41 MSPS.

2. Dynamic performance specified over entire Nyquist band;

spurious signals 80 dBc typical for −1 dBFS input signals.

3. Low power dissipation: 595 mW off a single 5 V supply.

4. Reference and track-and-hold included on chip.

5. Packaged in 44-lead LQFP.

DV

CC

TH2A1 TH1 TH3 A2

ADC

DAC

6

DIGITAL ERROR CORRECTION LOGIC

D10D9D8D7D6D5D4D3D2D1D0D11

Figure 1.

AD9042

7

00554-001

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©1995–2009 Analog Devices, Inc. All rights reserved.

AD9042

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

DC Specifications ......................................................................... 3

Switching Specifications .............................................................. 4

AC Specifications .......................................................................... 4

Absolute Maximum Ratings ............................................................ 6

Thermal Resistance ...................................................................... 6

Explanation of Test Levels ........................................................... 6

ESD Caution .................................................................................. 6

Pin Configuration and Function Descriptions ............................. 7

Typical Performance Characteristics ............................................. 8

Terminolog y .................................................................................... 11

Equivalent Circuits ......................................................................... 12

Theory of Operation ...................................................................... 13

Encoding the AD9042 ............................................................... 13

Driving the Analog Input .......................................................... 14

Power Supplies ............................................................................ 15

Output Loading .......................................................................... 15

Layout Information .................................................................... 15

Digital Wideband Receivers .......................................................... 16

Introduction ................................................................................ 16

Noise Floor and SNR ................................................................. 18

Processing Gain .......................................................................... 18

Overcoming Static Nonlinearities with Dither ...................... 18

Receiver Example ....................................................................... 19

IF Sampling, Using the AD9042 as a Mix-Down Stage ........ 20

Receive Chain for Digital and Analog Beam Forming Medical

Ultrasound Using the AD9042 ........................................................ 21

Outline Dimensions ....................................................................... 22

Ordering Guide .......................................................................... 22

REVISION HISTORY

9/09—Rev. A to Rev. B

Updated Format .................................................................. Universal

Reorganized Layout ............................................................ Universal

Deleted DH-28 Package ................................................ Throughout

Changes to General Description Section and Product

Highlights Section ............................................................................ 1

Deleted Wafer Test Limits Section ................................................. 4

Deleted Die Layout and Mechanical Information Table and Die

Layout with Pad Labels Figure ........................................................ 6

Changes to Figure 4 .......................................................................... 7

Deleted Figure 7; Renumbered Sequentially ................................. 7

Deleted Figure 15 and Figure 16 ..................................................... 9

Deleted Evaluation Boards Section .............................................. 13

Changes to Layout Information Section ...................................... 16

Removed Evaluation Boards Section ........................................... 18

Changes to Figure 49 and Figure 50 ............................................. 19

Changes to Figure 52 ...................................................................... 20

Changes to Figure 54 ...................................................................... 22

Updated Outline Dimension ......................................................... 24

Changes to Ordering Guide .......................................................... 24

5/96—Rev. 0 to Rev. A

Changes to Specifications Section ................................................... 2

Changes to Switching Specifications Section................................. 2

Changes to AC Specifications Section ............................................ 3

Changes to Ordering Guide ............................................................. 4

Changes to Pin Descriptions Section .............................................. 5

Added Die Layout and Mechanical Information Section ............ 6

Changes to Figure 2, Figure 3, Figure 5, and Figure 6 .................. 7

Changes to Figure 37 ...................................................................... 14

Added Figure 38 ............................................................................. 15

Added Table 2 ................................................................................. 15

Added Figure 43, Figure 44, Figure 45, and Figure 46 .............. 17

Added Figure 47 and Figure 48 .................................................... 18

Changes to Figure 53 ...................................................................... 21

Changes to Figure 54 ...................................................................... 22

Added Receiver Example Section ................................................. 22

Added Multitone Performance Section ....................................... 22

Added Receive Chain for Digital Beam-Forming Medical

Ultrasound Using the AD9042 Section ....................................... 23

Added Figure 58 ............................................................................. 23

10/95—Rev. 0: Initial Version

Rev. B | Page 2 of 24

AD9042

SPECIFICATIONS

DC SPECIFICATIONS

AVCC = DVCC = 5 V; V

tied to V

REF

through 50 Ω; T

OFFSET

= −40°C, T

MIN

= +85°C.

MAX

Table 1.

Parameter

1

Temperature Test Level Min Typ Max Un i t

RESOLUTION 12 Bits
DC ACCURACY

No Missing Codes Full VI Guaranteed
Offset Error Full VI −10 ±3 +10 mV
Offset Tempco Full V 25 ppm/°C
Gain Error Full VI −6.5 0 +6.5 % FS
Gain Tempco Full V −50 ppm/°C

REFERENCE OUT (V

REF

2

)

25°C V 2.4 V

ANALOG INPUT (AIN)

Input Voltage Range V

± 0.500 V

REF

Input Resistance Full IV 200 250 300 Ω
Input Capacitance 25°C V 5.5 pF

ENCODE INPUT

Logic Compatibility

3

4

TTL/CMOS
Logic 1 Voltage Full VI 2.0 5.0 V
Logic 0 Voltage Full VI 0 0.8 V
Logic 1 Current (V
Logic 0 Current (V

= 5 V) Full VI 450 625 800 μA

INH

= 0 V) Full VI −400 −300 −200 μA

INL

Input Capacitance 25°C V 2 pF

DIGITAL OUTPUTS

Logic Compatibility CMOS
Logic 1 Voltage (IOH = 10 μA) 25°C I 3.5 4.2 V
Full IV 3.5 V
Logic 0 Voltage (IOL = 10 μA) 25°C I 0.75 0.80 V
Full IV 0.85 V
Output Coding Twos complement

POWER SUPPLY

AVCC Supply Voltage Full VI 5.0 V
AVCC Current (I) Full V 109 mA
DVCC Supply Voltage Full VI 5.0 V
DVCC Current (I) Full V 10 mA
ICC (Total) Supply Current Full VI 119 147 mA
Power Dissipation Full VI 595 735 mW
Power Supply Rejection Ratio (PSRR) 25°C I −20 ±1 +20 mV/V

Full V ±5 mV/V

1

C1 (Pin 10) tied to GND through a 0.01 μF capacitor.

2

V

is normally tied to V

REF

3

ENCODE driven by single-ended source;

4

ENCODE may also be driven differentially in conjunction with

through 50 Ω. If V

OFFSET

is used to provide dc offset to other circuits, it should first be buffered.

REF

ENCODE

bypassed to ground through a 0.01 μF capacitor.

ENCODE

; see the Encoding the AD9042 section for details.

Rev. B | Page 3 of 24

AD9042

SWITCHING SPECIFICATIONS

AVCC = DVCC = 5 V; ENCODE and

ENCODE

= 41 MSPS; V

tied to V

REF

through 50 Ω; T

OFFSET

= −40°C, T

MIN

= +85°C.

MAX

Table 2.

Parameter

1

Temperature Test Level M i n Typ Max Unit

Maximum Conversion Rate Full VI 41 MSPS
Minimum Conversion Rate Full IV 5 MSPS
Aperture Delay (tA) 25°C V −250 ps
Aperture Uncertainty (Jitter) 25°C V 0.7 ps rms
ENCODE Pulse Width High 25°C IV 10 ns
ENCODE Pulse Width Low 25°C IV 10 ns
Output Delay (tOD) Full IV 5 9 14 ns

1

C1 (Pin 10) tied to GND through a 0.01 μF capacitor.

AC SPECIFICATIONS

AVCC = DVCC = 5 V; ENCODE and

Table 3.

Parameter

SNR

1, 2

3

Temp Test Level Min Typ Max Units

Analog Input at −1 dBFS

1.2 MHz 25°C V 68 dB
Full V 67.5 dB

9.6 MHz 25°C V 67.5 dB
Full V 67 dB

19.5 MHz 25°C I 64 67 dB
Full V 66.5 dB

4

SINAD

Analog Input at −1 dBFS

1.2 MHz 25°C V 67.5 dB
Full V 67 dB

9.6 MHz 25°C V 67.5 dB
Full V 67 dB

19.5 MHz 25°C I 64 67 dB
Full V 66.5 dB

WORST SPUR

5

Analog Input at −1 dBFS

1.2 MHz 25°C V 80 dBc
Full V 78 dBc

9.6 MHz 25°C V 80 dBc
Full V 78 dBc

19.5 MHz 25°C I 73 80 dBc
Full V 78 dBc

SMALL SIGNAL SFDR (WITH DITHER)

Analog Input

1.2 MHz Full V 90 dBFS

9.6 MHz Full V 90 dBFS

19.5 MHz Full V 90 dBFS

TWO-TONE IMD REJECTION

7

F1, F2 @ –7 dBFS Full V 80 dBc
TWO-TONE SFDR (WITH DITHER)
THERMAL NOISE 25°C V 0.33 LSB rms

ENCODE

6

8

= 41 MSPS; V

Full V 90 dBFS

tied to V

REF

through 50 Ω; T

OFFSET

= −40°C, T

MIN

= +85°C.

MAX

Rev. B | Page 4 of 24

AD9042

Parameter

1, 2

Temp Test Level Min Typ Max Units

DIFFERENTIAL NONLINEARITY 25°C I −1.0 ±0.3 +1.0 LSB

(ENCODE = 20 MSPS) Full V ±0.4 LSB

INTEGRAL NONLINEARITY

(ENCODE = 20 MSPS) Full V ±0.75 LSB
ANALOG INPUT BANDWIDTH 25°C V 100 MHz
TRANSIENT RESPONSE 25°C V 10 ns
OVERVOLTAGE RECOVERY TIME 25°C V 25 ns

1

All ac specifications tested by driving ENCODE and

2

C1 (Pin 10 on AD9042ASTZ only) tied to GND through a 0.01 μF capacitor.

3

Analog input signal power at −1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first five harmonics removed).

4

Analog input signal power at −1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics.

5

Analog input signal power at −1 dBFS; worst spur is the ratio of the signal level to worst spur, usually limited by harmonics.

6

Analog input signal power swept from −20 dBFS to –95 dBFS; dither power = −32.5 dBm; dither circuit used on input signal (see the Overcoming Static Nonlinearities

with Dither section); SFDR is the ratio of converter full scale to worst spur.

7

Tones at −7 dBFS (f1 = 15.3 MHz, f2 = 19.5 MHz); two-tone intermodulation distortion (IMD) rejection is ratio of either tone to worst-third order intermodulation

product.

8

Both input tones swept from −20 dBFS to −95 dBFS; dither power = −32.5 dBm; dither circuit used on input signal (see the Overcoming Static Nonlinearities with

ENCODE

differentially; see the Encoding the AD9042 section for details.

Dither section); two-tone spurious-free dynamic range (SFDR) is the ratio of converter full scale to worst spur.

Rev. B | Page 5 of 24

AD9042

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter1 Rating

AVCC Voltage 0 V to 7 V
DVCC Voltage 0 V to 7 V
Analog Input Voltage 0.5 V to 4.5 V
Analog Input Current 20 mA
Digital Input Voltage (ENCODE) 0 V to AVCC
ENCODE, ENCODE Differential Voltage
Digital Output Current −40 to +40 mA
Operating Temperature Range (Ambient) −40 °C to +85°C
Maximum Junction Temperature +150°C
Lead Temperature (Soldering, 10 sec) +300°C
Storage Temperature Range (Ambient) −65°C to +150°C

1

Absolute maximum ratings are limiting values to be applied individually, and

beyond which the serviceability of the circuit may be impaired.

4 V

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 5. Thermal Resistance

Package Type θJA Unit

44-Lead LQFP 55 °C/W

EXPLANATION OF TEST LEVELS

I. 100% production tested.

II. 100% production tested at +25°C, and sample tested at

specified temperatures. AC testing done on sample basis.

III. Sample tested only.
IV. Parameter is guaranteed by design and characterization

testing.

V. Parameter is a typical value only.

VI. 100% production tested at +25°C; sample tested at

temperature extremes.

ESD CAUTION

Rev. B | Page 6 of 24

AD9042

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

DV

CC

2

DV

CC

V

OFFSET

GND
GND

V

AV

AIN

REF

3
4
5
6
7
8
9

10

C1

11

CC

ENCODE
ENCODE

NC = NO CONNECT

(Not to Scale)

14

15 16 17 18

VCCV

GND

CC

GND

AD9042

TOP VIEW

CC

GND

D11 (MSB)

D10D9DVCCDV

44 43 42 41 40 393837 36 35 34

PIN 1

12

13

CC

V

GND

GND

GND

DVCCDV

19

V

CC

GND

GND

33
32
31
30
29
28
27
26
25
24
23

21 22

20

CC

CC

V

GND

GND

Figure 2. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description

1, 2 DVCC 5 V Power Supply (Digital). Powers output stage only.
3 ENCODE Encode Input. Data conversion initiated on rising edge.
4

ENCODE

Complement of ENCODE. Drive differentially with ENCODE or bypass to ground for single-ended clock mode.
5, 6 GND Ground.
7 AIN Analog Input.
8 V

9 V

Voltage Offset Input. Sets mid point of analog input range. Normally tied to V

OFFSET

REF

Internal Voltage Reference. Nominally 2.4 V; normally tied to V

and with 0.1 μF + 0.01 μF microwave chip capacitor.
10 C1 Internal Bias Point. Bypass to ground with a 0.01 μF capacitor.
11, 12 AV

5 V Power Supply (Analog).

CC

13, 14 GND Ground.
15, 16 AV

5 V Power Supply (Analog).

CC

17, 18 GND Ground.
19, 20 AV

5 V Power Supply (Analog).

CC

21, 22 GND Ground.
23 NC No Connect
24 GND Ground.
25 D0 (LSB) Digital Output Bit (Least Significant Bit).
26 to 33 D1 to D8 Digital Output Bits.
34, 35 GND Ground.
36, 37 DVCC 5 V Power Supply (Digital). Powers output stage only.
38, 39 GND Ground.
40, 41 DV

5 V Power Supply (Digital). Powers output stage only.

CC

42, 43 D9 to D10 Digital Output Bits.
44

D11

(MSB)

Digital Output Bit (Most Significant Bit). Output coded as twos complement.

D8
D7
D6
D5
D4
D3
D2
D1
D0 (LSB)
GND
NC

00554-003

through a 50 Ω resistor.

REF

through a 50 Ω resistor. Bypass to ground

OFFSET

Rev. B | Page 7 of 24

AD9042

TYPICAL PERFORMANCE CHARACTERISTICS

0

–20

–40

–60

2 3 4 5 6 7 8 9

–80

–100

POWER RELATIVE TO ADC F ULL SCALE (dB)

–120

dc 4.1 8.2 12.3 16.4 20.5

FREQUENCY (MHz)

Figure 3. Single Tone at 1.2 MHz

0

–20

–40

–60

4 8 8 5 3 7 6 2

–80

ENCODE = 41MSPS
AIN = 1.2MHz

ENCODE = 41MSPS
AIN = 9.6MHz

81

80

79

78

WORST- CASE HARMO NI C (d Bc)

77

0 2 4 6 8 10 12 14 16 18 20

00554-013

T = +25°C

T = –40°C

T = +85°C

ANALOG INPUT FREQUENCY ( M Hz )

ENCODE = 41MSPS
TEMP = –40°C, +25°C, AND +85°C

00554-016

Figure 6. Worst-Case Harmonics vs. AIN

70

69

T = –40°C

68

SNR (dB)

67

T = +85°C

ENCODE = 41MSPS
TEMP = –40°C, +25°C, AND + 85°C

T = +25°C

–100

POWER REL ATIVE TO ADC FULL SCALE ( dB)

–120

dc 4.1 8.2 12.3 16.4 20.5

FREQUENCY (MHz)

Figure 4. Single Tone at 9.6 MHz

0

ENCODE = 41MSPS

–20

AIN = 19.5MHz

–40

–60

2 4 6 8 9 7 5 3

–80

–100

POWER REL ATIVE TO ADC FULL SCALE ( dB)

–120

dc 4.1 8.2 12.3 16.4 20.5

FREQUENCY (MHz )

Figure 5. Single Tone at 19.5 MHz

66

0 2 4 6 8 101214161820

00554-014

ANALOG INPUT FREQUENCY ( MHz )

0554-017

Figure 7. SNR vs. AIN

90

80

70

60

50

WORST-CAS E HARMO NI C ( d Bc)

40

30

1 2 4 102040 100

00554-015

ANALOG INPUT FREQUENCY (M Hz )

ENCODE = 41MSP S

00554-018

Figure 8. Worst-Case Harmonics vs. AIN

Rev. B | Page 8 of 24