Analog Devices AD8802, AD8804 Datasheet
FUNCTIONAL BLOCK DIAGRAM
CS
CLK
SDI
SHDN
AD8802/AD8804
D7
D0
ADDR
DEC
EN
D11
D10
D9
D8
D7
SER
REG
DD0
DAC
REG
#1
R
V
DD
D7
D0
DAC
12
DAC
REG
#12
R
DAC
1
8
O1
O2
O4
O5
O6
O7
O8
O9
O10
O11
O12
V
REFH
GND
RS
(AD8802 ONLY)
V
REFL
(AD8804 ONLY)
O3
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
12 Channel, 8-Bit TrimDACs
with Power Shutdown
AD8802/AD8804
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703
GENERAL DESCRIPTION
The 12-channel AD8802/AD8804 provides independent digitallycontrollable voltage outputs in a compact 20-lead package. This
potentiometer divider TrimDAC® allows replacement of the
mechanical trimmer function in new designs. The AD8802/
AD8804 is ideal for dc voltage adjustment applications.
Easily programmed by serial interfaced microcontroller ports,
the AD8802 with its midscale preset is ideal for potentiometer
replacement where adjustments start at a nominal value. Applications such as gain control of video amplifiers, voltage controlled frequencies and bandwidths in video equipment,
geometric correction and automatic adjustment in CRT computer graphic displays are a few of the many applications ideally
suited for these parts. The AD8804 provides independent control of both the top and bottom end of the potentiometer divider
allowing a separate zero-scale voltage setting determined by the
V
REFL
pin. This is helpful for maximizing the resolution of
devices with a limited allowable voltage control range.
Internally the AD8802/AD8804 contains 12 voltage-output
digital-to-analog converters, sharing a common referencevoltage input.
TrimDAC is a registered trademark of Analog Devices, Inc.
FEATURES
Low Cost
Replaces 12 Potentiometers
Individually Programmable Outputs
3-Wire SPI Compatible Serial Input
Power Shutdown <55 mWatts Including I
DD
& I
REF
Midscale Preset, AD8802
Separate V
REFL
Range Setting, AD8804
+3 V to +5 V Single Supply Operation
APPLICATIONS
Automatic Adjustment
Trimmer Replacement
Video and Audio Equipment Gain and Offset Adjustment
Portable and Battery Operated Equipment
Each DAC has its own DAC latch that holds its output state.
These DAC latches are updated from an internal serial-toparallel shift register that is loaded from a standard 3-wire
serial input digital interface. The serial-data-input word is
decoded where the first 4 bits determine the address of the DAC
latches to be loaded with the last 8 bits of data. The AD8802/
AD8804 consumes only 10 µA from 5 V power supplies. In ad-
dition, in shutdown mode reference input current consumption
is also reduced to 10 µA while saving the DAC latch settings for
use after return to normal operation.
The AD8802/AD8804 is available in the 20-pin plastic DIP, the
SOIC-20 surface mount package, and the 1 mm thin TSSOP-20
package.
Parameter Symbol Conditions Min Typ1Max Units
STATIC ACCURACY
Specifications apply to all DACs
Resolution N 8 Bits
Differential Nonlinearity Error DNL Guaranteed Monotonic –1 ±1/4 +1 LSB
Integral Nonlinearity Error INL –1.5 ±1/2 +1.5 LSB
Full-Scale Error G
FSE
–1 1/2 +1 LSB
Zero Code Error V
ZSE
–1 1/4 +1 LSB
DAC Output Resistance R
OUT
35 8 kΩ
Output Resistance Match ∆R/R
O
1.5 %
REFERENCE INPUT
Voltage Range
2
V
REFH
0V
DD
V
V
REFL
Pin Available on AD8804 Only 0 V
DD
V
REFH Input Resistance R
REFH
Digital Inputs = 55H, V
REFH
= V
DD
1.2 kΩ
REFL Input Resistance
3
R
REFL
Digital Inputs = 55H, V
REFL
= V
DD
1.2 kΩ
Reference Input Capacitance
3
C
REF0
Digital Inputs all Zeros 32 pF
C
REF1
Digital Inputs all Ones 32 pF
DIGITAL INPUTS
Logic High V
IH
VDD = +5 V 2.4 V
Logic Low V
IL
VDD = +5 V 0.8 V
Logic High V
IH
VDD = +3 V 2.1 V
Logic Low V
IL
VDD = +3 V 0.6 V
Input Current I
IL
VIN = 0 V or + 5 V ±1 µA
Input Capacitance
3
C
IL
5pF
POWER SUPPLIES
4
Power Supply Range V
DD
Range 2.7 5.5 V
Supply Current (CMOS) I
DD
VIH = VDD or VIL = 0 V 0.01 10 µA
Supply Current (TTL) I
DD
VIH = 2.4 V or VIL = 0.8 V, V
DD
= +5.5 V 1 4 mA
Shutdown Current I
REFH
SHDN = 0 0.2 10 µA
Power Dissipation P
DISS
VIH = VDD or VIL = 0 V, VDD = +5.5 V 55 µW
Power Supply Sensitivity PSRR VDD = +5 V ± 10% 0.001 0.002 %/%
DYNAMIC PERFORMANCE
3
V
OUT
Settling Time t
S
±1/2 LSB Error Band 0.6 µs
Crosstalk CT Between Adjacent Outputs
5
50 dB
SWITCHING CHARACTERISTICS
3, 6
Input Clock Pulse Width tCH, t
CL
Clock Level High or Low 15 ns
Data Setup Time t
DS
5ns
Data Hold Time t
DH
5ns
CS Setup Time t
CSS
10 ns
CS High Pulse Width t
CSW
10 ns
Reset Pulse Width t
RS
90 ns
CLK Rise to
CS Rise Hold Time t
CSH
20 ns
CS Rise to Clock Rise Setup t
CS1
10 ns
NOTES
1
Typicals represent average readings at +25°C.
2
V
REFH
can be any value between GND and VDD, for the AD8804 V
REFL
can be any value between GND and VDD.
3
Guaranteed by design and not subject to production test.
4
Digital Input voltages VIN = 0 V or VDD for CMOS condition. DAC outputs unloaded. P
DISS
is calculated from (IDD × VDD).
5
Measured at a V
OUT
pin where an adjacent V
OUT
pin is making a full-scale voltage change (f = 100 kHz).
6
See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of VDD) and timed from a voltage level of
1.6 V.
Specifications subject to change without notice.
AD8802/AD8804–SPECIFICATIONS
REV. 0
–2–
(VDD = +3 V 6 10% or +5 V 6 10%, V
REFH
= +VDD, V
REFL
= 0 V, –408C
≤T
A
≤ +858C unless otherwise noted)
AD8802/AD8804
REV. 0
–3–
ABSOLUTE MAXIMUM RATINGS
(TA = +25°C, unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3, + 8 V
V
REFX
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, V
DD
Outputs (Ox) to GND . . . . . . . . . . . . . . . . . . . . . . . . 0 V, V
DD
Digital Input Voltage to GND . . . . . . . . . . . . . . . . . 0 V, +8 V
Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C
Maximum Junction Temperature (T
J
MAX) . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C
Package Power Dissipation . . . . . . . . . . . . (T
J
MAX – TA)/θ
JA
Thermal Resistance θ
JA,
SOIC (SOL-20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
P-DIP (N-20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W
TSSOP-20 (RU-20) . . . . . . . . . . . . . . . . . . . . . . . . 155°C/W
AD8802 PIN DESCRIPTIONS
Pin Name Description
1V
REF
Common DAC Reference Input
2 O1 DAC Output #1, addr = 0000
2
3 O2 DAC Output #2, addr = 0001
2
4 O3 DAC Output #3, addr = 0010
2
5 O4 DAC Output #4, addr = 0011
2
6 O5 DAC Output #5, addr = 0100
2
7 O6 DAC Output #6, addr = 0101
2
8 SHDN Reference input current goes to zero. DAC
latch settings maintained
9
CS Chip Select Input, Active Low. When CS
returns high, data in the serial input register is
decoded based on the address bits and loaded
into the target DAC register
10 GND Ground
11 CLK Serial Clock Input, Positive Edge Triggered
12 SDI Serial Data Input
13 O7 DAC Output #7, addr = 0110
2
14 O8 DAC Output #8, addr = 0111
2
15 O9 DAC Output #9, addr = 1000
2
16 O10 DAC Output #10, addr = 1001
2
17 O11 DAC Output #11, addr = 1010
2
18 O12 DAC Output #12, addr = 1011
2
19 RS Asynchronous Preset to Midscale Output
Setting. Loads all DAC Registers with 80
H
20 V
DD
Positive Power Supply, Specified for Operation
at Both +3 V and +5 V
PIN CONFIGURATIONS
14
13
12
11
17
16
15
20
19
18
9
8
1
2
3
4
7
6
5
10
O10
O11
O12
V
DD
O7
O8
O9
V
REFL
CLK
SDI
V
REFH
O1
O2
O3
O4
O5
O6
SHDN
CS
GND
TOP VIEW
(Not to Scale)
AD8804
14
13
12
11
17
16
15
20
19
18
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
V
REFH
O11
O12
RS
V
DD
O1
O2
O3
AD8802
O8
O9
O10
O4
O5
O6
SHDN
CS
GND CLK
SDI
O7
AD8804 PIN DESCRIPTIONS
Pin Name Description
1V
REFH
Common High-Side DAC Reference Input
2 O1 DAC Output #1, addr = 0000
2
3 O2 DAC Output #2, addr = 0001
2
4 O3 DAC Output #3, addr = 0010
2
5 O4 DAC Output #4, addr = 0011
2
6 O5 DAC Output #5, addr = 0100
2
7 O6 DAC Output #6, addr = 0101
2
8 SHDN Reference input current goes to zero DAC latch
settings maintained
9
CS Chip Select Input, Active Low. When CS returns
high, data in the serial input register is decoded
based on the address bits and loaded input the
target DAC register
10 GND Ground
11 V
REFL
Common Low-Side DAC Reference Input
12 CLK Serial Clock Input, Positive Edge Triggered
13 SDI Serial Data Input
14 O7 DAC Output #7, addr = 0110
2
15 O8 DAC Output #8, addr = 0111
2
16 O9 DAC Output #9, addr = 1000
2
17 O10 DAC Output #10, addr = 1001
2
18 O11 DAC Output #11, addr = 1010
2
19 O12 DAC Output #12, addr = 1011
2
20 V
DD
Positive power supply, specified for operation at
both +3 V and +5 V
ORDERING GUIDE
Temperature Package Package
Model FTN Range Description Option
AD8802AN
RS –40°C/+85°C PDIP-20 N-20
AD8802AR RS –40°C/+85°C SOL-20 R-20
AD8802ARU
RS –40°C/+85°C TSSOP-20 RU-20
AD8804AN REFL –40°C/+85°C PDIP-20 N-20
AD8804AR REFL –40°C/+85°C SOL-20 R-20
AD8804ARU REFL –40°C/+85°C TSSOP-20 RU-20
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although these devices feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
AD8802/AD8804–Typical Performance Characteristics
REV. 0
–4–
CODE – Decimal
INL – LSB
1
–1
0.75
0
–0.25
–0.5
–0.75
0.5
0.25
0 25632 64 96 128 160 192 224
VDD = +5V
V
REFH
= +5V
V
REFL
= 0V
TA = +85°C
T
A
= +25°C
T
A
= –40°C
Figure 1. INL vs. Code
CODE – Decimal
INL – LSB
1
–1
0.75
0
–0.25
–0.5
–0.75
0.5
0.25
0 25632 64 96 128 160 192 224
TA = +85°C
T
A
= +25°C
T
A
= –40°C
VDD = +5V
V
REFH
= +5V
V
REFL
= 0V
Figure 2. Differential Nonlinearity Error vs. Code
FREQUENCY
ABSOLUTE VALUE TOTAL UNADJUSTED ERROR – LSB
1600
320
960
640
1280
0
0 0.2 0.4 0.6 0.8 1.0
VDD = +4.5V
V
REF
= +4.5V
V
REFL
= 0V
T
A
= +25°C
SS = 3600 PCS
Figure 3. Total Unadjusted Error Histogram
CODE – Decimal
160
0
80
40
120
140
100
60
20
0 25632 64 96 128 160 192 224
I
REF
CURRENT – µA
V
DD
= +5V
V
REFH
= +2V
V
REFL
= 0V
ONE DAC CHANGING WITH CODE,
OTHER DACs SET TO 00H
T
A
= +25°C
Figure 4. Input Reference Current vs. Code
10k
1k
0
100
10
–35 255–15–55 65 1251058545
TEMPERATURE – °C
SHUTDOWN CURRENT – nA
VDD = +5.5V
V
REF
= +5.5V
VDD = +2.7V
V
REF
= +2.7V
Figure 5. Shutdown Current vs. Temperature
TEMPERATURE – °C
SUPPLY CURRENT – µA
100k
0.001
10k
10
1
0.1
0.01
1k
100
–55 125–35 –15 5 25 45 65 85 105
VDD = +5.5V
V
IN
= +5.5V
VDD = +5.5V
V
IN
= +2.4V
Figure 6. Supply Current vs. Temperature
AD8802/AD8804
REV. 0
–5–
100
0.0001
2.5
0.01
0.001
0.50
0.1
1.0
10
21.51
INPUT VOLTAGE – Volts
53 4.543.5
TA = +25°C
ALL DIGITAL INPUTS
TIED TOGETHER
SUPPLY CURRENT – mA
VDD = +5V
VDD = +3V
Figure 7. Supply Current vs. Logic Input Voltage
80
60
40
20
0
100 100k10k1k10
FREQUENCY – Hz
PSRR – dB
VDD = +5V
ALL OUTPUTS SET
TO MIDSCALE (80H)
Figure 8. Power Supply Rejection vs. Frequency
10
0%
100
90
0%
VDD = +5V
V
REF
= +5V
TIME – 5µs/DIV
4V
0V
5V
0V
OUT
CS
2V
5µs
6V
2V
5V
Figure 9. Large-Signal Settling Time
10
0%
100
90
OUTPUT1: OOH → FF
H
TIME – 0.2µs/DIV
OUTPUT2 – 10mV/DIV
10mV
200ns
V
DD
= +5V
V
REF
= +5V
f = 1MHz
Figure 10. Adjacent Channel Clock Feedthrough
10
0%
100
90
OUTPUT1: 7FH → 80
H
VDD = +5V
V
REF
= +5V
TIME – 1µs/DIV
OUT1
5mV/DIV
CS
5V/DIV
5mV 1µs
5V
Figure 11. Midscale Transition
HOURS OF OPERATION AT 150°C
0.01
–0.01
0
–0.005
0.005
0
600100 300 500
CHANGE IN ZERO-SCALE ERROR – LSB
VDD = +4.5V
V
REF
= +4.5V
SS = 176 PCS
V
REFL
= 0V
200 400
Figure 12. Zero-Scale Error Accelerated by Burn-In
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