Analog Devices AD8801AR, AD8801AN, AD8803AR, AD8803AN Datasheet

Octal 8-Bit TrimDAC

DAC 8

V

OUT

V

REFH

V

REFL

.

.

.

.

.

.

AD8801/AD8803

V

REFL

V

REFH

O1

O8

SHDNRS

CS

CLK

SDI

GND

V

DD

8

8

8

88

8

3

DAC

SELECT

11-BIT
SERIAL
LATCH

D

CK

RS

1

8

ADDRESS

8-BIT

LATCH

CK

RS

8-BIT

LATCH

CK RS

DAC 1

V

OUT

V

REFH

V

REFL

a

FEATURES
Low Cost
Replaces Eight Potentiometers
Eight Individually Programmable Outputs
Three-Wire Serial Input
Power Shutdown ≤ 25 mW Including I
Midscale Preset, AD8801
Separate V

Range Setting, AD8803

REFL

+3 V to +5 V Single Supply Operation
APPLICATIONS

Automatic Adjustment
Trimmer Potentiometer Replacement
Video and Audio Equipment Gain and Offset Adjustment
Portable and Battery Operated Equipment

GENERAL DESCRIPTION

The AD8801/AD8803 provides eight digitally controlled dc
voltage outputs. This potentiometer divider TrimDAC
replacement of the mechanical trimmer function in new designs.
The AD8801/AD8803 is ideal for dc voltage adjustment
applications.

Easily programmed by serial interfaced microcontroller ports,
the AD8801 with its midscale preset is ideal for potentiometer
replacement where adjustments start at a nominal value. Appli­cations such as gain control of video amplifiers, voltage con­trolled frequencies and bandwidths in video equipment,
geometric correction and automatic adjustment in CRT com­puter graphic displays are a few of the many applications ideally
suited for these parts. The AD8803 provides independent con­trol of both the top and bottom end of the potentiometer divider
allowing a separate zero-scale voltage setting determined by the
V

pin. This is helpful for maximizing the resolution of de-

REFL

vices with a limited allowable voltage control range.

See the AD8802/AD8804 for a twelve channel version of this product.

TrimDAC is a registered trademark of Analog Devices, Inc.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

DD

and I

REF

®

allows

with Power Shutdown

AD8801/AD8803

FUNCTIONAL BLOCK DIAGRAM

(DACs 2–7 Omitted for Clarity)

Internally the AD8801/AD8803 contain eight voltage output
digital-to-analog converters, sharing a common reference volt­age input.

Each DAC has its own DAC register that holds its output state.
These DAC registers are updated from an internal serial-to-par­allel shift register that is loaded from a standard three-wire serial
input digital interface. Eleven data bits make up the data word
clocked into the serial input register. This data word is decoded
where the first 3 bits determine the address of the DAC register
to be loaded with the last 8 bits of data. The AD8801/AD8803
consumes only 5 µA from 5 V power supplies. In addition, in
shutdown mode reference input current consumption is also re­duced to 5 µA while saving the DAC latch settings for use after
return to normal operation.

The AD8801/AD8803 is available in 16-pin plastic DIP and the

1.5 mm height SO-16 surface mount packages.

© Analog Devices, Inc., 1995

One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: [phone] Fax: [phone]

AD8801/AD8803–SPECIFICATIONS

(VDD = +3 V 6 10% or +5 V 6 10%, V
≤ TA ≤ +858C unless otherwise noted)

= +VDD, V

REFH

= 0 V, –408C

REFL

Parameter Symbol Conditions Min Typ1Max Units

STATIC ACCURACY
Specifications Apply to All DACs

Resolution N 8 Bits
Integral Nonlinearity Error INL –1.5 ±1/2 +1.5 LSB
Differential Nonlinearity DNL Guaranteed Monotonic –1 ±1/4 +1 LSB
Full-Scale Error G
Zero-Code Error V
DAC Output Resistance R
Output Resistance Match ∆R/R

REFERENCE INPUT

Voltage Range
Input Resistance R

Reference Input Capacitance

2

3

V
V

C
C

FSE
ZSE
OUT

REFH
REFL
REFH
REF0
REF1

O

Pin Available on AD8803 Only 0 V
Digital Inputs = 55H, V

REFH

= V

DD

Digital Inputs All Zeros 25 pF
Digital Inputs All Ones 25 pF

–4 –2.8 +0.5 LSB
–0.5 ±0.1 +0.5 LSB
358 kΩ

1%

0V

DD
DD

V
V

2kΩ

DIGITAL INPUTS

Logic High V
Logic Low V
Logic High V
Logic Low V
Input Current I
Input Capacitance

POWER SUPPLIES

3

4

Power Supply Range V
Supply Current (CMOS) I
Supply Current (TTL) I
Shutdown Current I
Power Dissipation P

IH
IL
IH
IL

IL

C

IL

Range 2.7 5.5 V

DD

DD
DD
REFH

DISS

Power Supply Sensitivity PSRR V
Power Supply Sensitivity PSRR VDD = 3 V ± 10%, V

DYNAMIC PERFORMANCE

V

Settling Time (Positive or Negative) t

OUT

3

S

VDD = +5 V 2.4 V
VDD = +5 V 0.8 V
VDD = +3 V 2.1 V
VDD = +3 V 0.6 V
VIN = 0 V or +5 V ±1 µA

5pF

VIH = VDD or VIL = 0 V 0.01 5 µA
VIH = 2.4 V or VIL = 0.8 V, VDD= +5.5 V 1 4 mA
SHDN = 0 0.01 5 µA
VIH = VDD or VIL = 0 V, VDD = +5.5 V 27.5 µW

= 5 V ± 10%, V

DD

= +4.5 V 0.001 0.002 %/%

REFH

= +2.7 V 0.01 %/%

REFH

±1/2 LSB Error Band 0.6 µs

Crosstalk CT See Note 5, f = 100 kHz 50 dB

SWITCHING CHARACTERISTICS

Input Clock Pulse Width tCH, t
Data Setup Time t
Data Hold Time t

CS Setup Time t
CS High Pulse Width t

Reset Pulse Width t
CLK Rise to

CS Rise Hold Time t

CS Rise to Next Rising Clock t

NOTES

1

Typical values represent average readings measured at +25 °C.

2

V

can be any value between GND and VDD, for the AD8803 V

REFH

3

Guaranteed by design and not subject to production test.

4

Digital Input voltages VIN = 0 V or VDD for CMOS condition. DAC outputs unloaded. P

5

Measured at a V

6

See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of VDD) and timed from a voltage
level of 1.6 V.

Specifications subject to change without notice.

pin where an adjacent V

OUT

3, 6

CL
DS
DH
CSS
CSW
RS
CSH
CS1

pin is making a full-scale voltage change.

OUT

Clock Level High or Low 15 ns

can be any value between GND and VDD.

REFL

is calculated from (IDD × VDD).

DISS

5ns
5ns
10 ns
10 ns
60 ns
15 ns
10

ns

–2–

REV. A

AD8801/AD8803

V

REFH

O1

V

DD

RS

O4

SHDN

CS

O6
O5
SDI

O2
O3

O8
O7

GND CLK

1
2

16
15

5
6
7

12
11
10

3
4

14
13

89

TOP VIEW

(Not to Scale)

AD8801

V

REFH

O1

V

DD

O8

O4

SHDN

CS

O5
SDI
CLK

O2
O3

O7
O6

GND V

REFL

1
2

16
15

5
6
7

12
11
10

3
4

14
13

89

TOP VIEW

(Not to Scale)

AD8803

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

(TA = +25°C, unless otherwise noted)

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3, +8 V

V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, V

REFX

Outputs (Ox) to GND . . . . . . . . . . . . . . . . . . . . . . . . 0 V, V

Digital Input Voltage to GND . . . . . . . . . . . . . . . . . . 0 V, V

DD
DD
DD

Operating Temperature Range . . . . . . . . . . . . .–40°C to +85°C

Maximum Junction Temperature (T

MAX) . . . . . . . . +150°C

J

Storage Temperature . . . . . . . . . . . . . . . . . . .–65°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C

Package Power Dissipation . . . . . . . . . . . . .(T

Thermal Resistance θ

JA,

MAX – TA)/θ

J

JA

SOIC (SO-16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W

P-DIP (N-16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W

AD8801 PIN DESCRIPTIONS

Pin Name Description

1V
2 O1 DAC Output #1, Addr = 000
3 O2 DAC Output #2, Addr = 001
4 O3 DAC Output #3, Addr = 010
5 O4 DAC Output #4, Addr = 011

Common DAC Reference Input

REFH

2
2
2
2

6 SHDN Reference input open circuit, active low, all

DAC outputs open circuit. DAC latch settings
maintained.

7

CS Chip Select Input, active low. When CS returns

high, data in the serial input register is decoded
based on the address bits and loaded into the tar-

get DAC register.
8 GND Ground
9 CLK Serial Clock Input, Positive Edge Triggered
10 SDI Serial Data Input
11 O5 DAC Output #5, Addr = 100
12 O6 DAC Output #6, Addr = 101
13 O7 DAC Output #7, Addr = 110
14 O8 DAC Output #8, Addr = 111

2
2
2
2

15 RS Asynchronous preset to midscale output setting,

16 V

active low. Loads all DAC latches with 80

Positive power supply, specified for operation at

DD

.

H

both +3 V and +5 V.

ORDERING GUIDE

Package Package

Model FTN Temperature Description Option

AD8801AN
AD8801AR

RS –40°C to +85°C PDIP-16 N-16
RS –40°C to +85°C SO-16 R-16A

AD8803AN REFL –40°C to +85°C PDIP-16 N-16
AD8803AR REFL –40°C to +85°C SO-16 R-16A

AD8803 PIN DESCRIPTIONS

Pin Name Description

1V
2 O1 DAC Output #1, Addr = 000
3 O2 DAC Output #2, Addr = 001
4 O3 DAC Output #3, Addr = 010
5 O4 DAC Output #4, Addr = 011

Common High-Side DAC Reference Input

REFH

2
2
2
2

6 SHDN Reference inputs open circuit, active low, all

DAC outputs open circuit. DAC latch settings
maintained.

7

CS Chip Select Input, active low. When CS returns

high, data in the serial input register is decoded
based on the address bits and loaded into the tar-

get DAC register.
8 GND Ground
9V

Common Low-Side DAC Reference Input

REFL

10 CLK Serial Clock Input, Positive Edge Triggered
11 SDI Serial Data Input
12 O5 DAC Output #5, Addr = 100
13 O6 DAC Output #6, Addr = 101
14 O7 DAC Output #7, Addr = 110
15 O8 DAC Output #8, Addr = 111
16 V

Positive power supply, specified for operation at

DD

2
2
2
2

both +3 V and +5 V.

PIN CONFIGURATIONS

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although these devices feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD

REV. A

precautions are recommended to avoid performance degradation or loss of functionality.

–3–

AD8801/AD8803

OCTAL 8-BIT TRIMDAC, WITH SHUTDOWN

1

V

SDI

CLK

CS

OUT

A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

0
1
0

1
0

+5V

0V

DAC REGISTER LOAD

Figure 2a. Timing Diagram

DETAIL SERIAL DATA INPUT TIMING (RS = "1")

SDI

1

(DATA

CLK

CS

V

OUT

AX OR D

0

IN)

1

0

t

CSS

1

0

+5V

0V

AX OR D

X

t

CH

X

t

DS

t

DH

t

t

CSH

CL

±1 LSB ERROR BAND

Figure 2b. Detail Timing Diagram

RESET TIMING

1

RS

0

+5V

V

OUT

2.5V

t

RS

t

S

±1 LSB ERROR BAND

following address assignments for the ADDR decode which de­termines the location of DAC register receiving the serial regis­ter data in bits B7 through B0:

DAC # = A2 × 4 + A1 × 2 + A0 + 1

DAC outputs can be changed one at a time in random se­quence. The fast serial-data loading of 33 MHz makes it possible
to load all eight DACs in as little time as 3 µs (12 × 8 × 30 ns).
The exact timing requirements are shown in Figure 2.

The AD8801 offers a midscale preset activated by the

RS pin
simplifying initial setting conditions at first power up. The
AD8803 has both a V

REFH

and a V

pin to establish indepen-

REFL

dent positive full-scale and zero-scale settings to optimize reso­lution. Both parts offer a power shutdown

SHDN that places
the DAC structure in a zero power consumption state resulting
in only leakage currents being consumed from the power supply,
V

inputs, and all 8 outputs. In shutdown mode the DACx

t

CS1

REF

latch settings are maintained. When returning to operational
mode from power shutdown the DAC outputs return to their
previous voltage settings.

V

REFH

DAC

REGISTER

TO OTHER DACS

P CH
N CH

D7

D6

D0

.

.

.

.

.

.

MSB

O

2R

2R

X

R

R

.

.

.

t

CSW

t

S

±1 LSB

±1 LSB

Figure 2c. Reset Timing Diagram

Table I. Serial-Data Word Format

ADDR DATA
B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB MSB LSB
2102928272625242322212

0

OPERATION

The AD8801/AD8803 provides eight channels of programmable
voltage output adjustment capability. Changing the programmed
output voltage of each TrimDAC is accomplished by clocking in
an 11-bit serial data word into the SDI (Serial Data Input) pin.
The format of this data word is three address bits, MSB first,
followed by eight data bits, MSB first. Table I provides the se­rial register data word format. The AD8801/AD8803 has the

2R

2R

V

GND

REFL

LSB

Figure 3. AD8801/AD8803 Equivalent TrimDAC Circuit

PROGRAMMING THE OUTPUT VOLTAGE

The output voltage range is determined by the external refer­ence connected to V

REFH

and V

pins. See Figure 3 for a

REFL

simplified diagram of the equivalent DAC circuit. In the case of
the AD8801, its V
therefore cannot be offset. V

is internally connected to GND and

REFL

can be tied to VDD and V

REFH

REFL

can be tied to GND establishing a basic rail-to-rail voltage out­put programming range. Other output ranges are established by
the use of different external voltage references. The general
transfer equation that determines the programmed output
voltage is:

V

(Dx) = (Dx)/256 × (V

O

REFH

– V

REFL

) + V

REFL

(1)

where Dx is the data contained in the 8-bit DACx latch.

–4–

REV. A

AD8801/AD8803

LOGIC

100Ω

For example, when V

= +5 V and V

REFH

= 0 V the follow-

REFL

ing output voltages will be generated for the following codes:

DVOXOutput State

(V

= +5 V, V

REFH

REFL

= 0 V)

255 4.98 V Full-Scale
128 2.50 V Half-Scale (Midscale Reset Value)
1 0.02 V 1 LSB
0 0.00 V Zero-Scale

REFERENCE INPUTS (V

REFH

, V

REFL

)

The reference input pins set the output voltage range of all eight
DACs. In the case of the AD8801 only the V

pin is avail-

REFH

able to establish a user designed full-scale output voltage. The
external reference voltage can be any value between 0 and V

DD

but must not exceed the VDD supply voltage. In the case of the
AD8803, which has access to the V

which establishes the

REFL

zero-scale output voltage, any voltage can be applied between
0 V and V
V

REFH

. V

DD

can be smaller or larger in voltage than

REFL

since the DAC design uses fully bidirectional switches as
shown in Figure 3. The input resistance to the DAC has a code
dependent variation that has a nominal worst case measured at
55

, which is approximately 2 kΩ. When V

H

V

, the REFL reference must be able to sink current out of

REFL

is greater than

REFH

the DAC ladder, while the REFH reference is sourcing current
into the DAC ladder. The DAC design minimizes reference
glitch current maintaining minimum interference between DAC
channels during code changes.

DAC OUTPUTS (O1–O8)

The eight DAC outputs present a constant output resistance of
approximately 5 kΩ independent of code setting. The distribu­tion of R

from DAC to DAC typically matches within ±1%.

OUT

However, device to device matching is process lot dependent
having a ±20% variation. The change in R

with temperature

OUT

has a 500 ppm/°C temperature coefficient. During power shut­down all eight outputs are open circuited.

CS

CLK

SDI

D

D10

SER
REG

ADDR
D9
D8
D7

.

.

.

D0

8

EN

DEC

...

...

...

AD8801/AD8803

D7

DAC
REG

#1

D0

D7

DAC
REG

#8

D0

DAC
DAC

R

..

..

..

DAC

R

V

DD

V

REFH

1

8

O1
O2
O3

O4
O5

O6

O7
O8

DIGITAL INTERFACING

The AD8801/AD8803 contains a standard three-wire serial in­put control interface. The three inputs are clock (CLK),

CS and
serial data input (SDI). The positive-edge sensitive CLK input
requires clean transitions to avoid clocking incorrect data into
the serial input register. Standard logic families work well. If
mechanical switches are used for product evaluation, they
should be debounced by a flip-flop or other suitable means. Fig­ure 4 block diagram shows more detail of the internal digital cir­cuitry. When

CS is taken active low, the clock can load data into

the serial register on each positive clock edge, see Table II.

Table II. Input Logic Control Truth Table

CS CLK Register Activity

1 X No effect.
0 P Shifts Serial Register one bit loading the

next bit in from the SDI pin.

P X Data is transferred from the serial register

to the decoded DAC register. See Figure 5.

NOTE: P = positive edge, X = don’t care.

The data setup and data hold times in the specification table
determine the data valid time requirements. The last 11 bits of
the data word entered into the serial register are held when
returns high. At the same time

CS goes high it gates the address

CS

decoder which enables one of the eight positive edge triggered
DAC registers, see Figure 5 detail.

DAC 1

SERIAL

DAC 2

.

.

.

DAC 8

CS

CLK

SDI

ADDR

DECODE

REGISTER

Figure 5. Equivalent Control Logic

The target DAC register is loaded with the last eight bits of the se­rial data word completing one DAC update. Eight separate 11-bit
data words must be clocked in to change all eight output settings.

All digital inputs are protected with a series input resistor and
parallel Zener ESD structure shown in Figure 6. This applies to
digital input pins

CS, SDI, RS, SHDN, CLK.

Figure 6. Equivalent ESD Protection Circuit

Digital inputs can be driven by voltages exceeding the AD8801/
AD8803 V

value. This allows 5 V logic to interface directly to

DD

the part when it is operated at 3 V.

SHDN

REV. A

GND

RS

(AD8801 ONLY) (AD8803 ONLY)

Figure 4. Block Diagram

V

REFL

–5–