Analog Devices AD7859CB, AD7859LAS, AD7859BS, AD7859AP, AD7859AS Datasheet

3 V to 5 V Single Supply, 200 kSPS

a

8-Channel, 12-Bit Sampling ADCs

FEATURES
Specified for V

of 3 V to 5.5 V

DD

AD7859–200 kSPS; AD7859L–100 kSPS
System and Self-Calibration
Low Power

Normal Operation

AD7859: 15 mW (V
AD7859L: 5.5 mW (V

= 3 V)

DD

DD

= 3 V)

Using Automatic Power-Down After Conversion (25 mW)

AD7859: 1.3 mW (VDD = 3 V 10 kSPS)
AD7859L: 650 mW (V

= 3 V 10 kSPS)

DD

Flexible Parallel Interface:

16-Bit Parallel/8-Bit Parallel

44-Pin PQFP and PLCC Packages
APPLICATIONS

Battery-Powered Systems (Personal Digital Assistants,

Medical Instruments, Mobile Communications)
Pen Computers
Instrumentation and Control Systems
High Speed Modems

GENERAL DESCRIPTION

The AD7859/AD7859L are high speed, low power, 8-channel,
12-bit ADCs which operate from a single 3 V or 5 V power
supply, the AD7859 being optimized for speed and the
AD7859L for low power. The ADC contains self-calibration
and system calibration options to ensure accurate operation over
time and temperature and have a number of power-down
options for low power applications.

The AD7859 is capable of 200 kHz throughput rate while the
AD7859L is capable of 100 kHz throughput rate. The input
track-and-hold acquires a signal in 500 ns and features a pseudo­differential sampling scheme. The AD7859 and AD7859L input
voltage range is 0 to V
about V

/2 (bipolar) with both straight binary and 2s comple-

REF

(unipolar) and –V

REF

/2 to +V

REF

REF

/2

ment output coding respectively. Input signal range is to the
supply and the part is capable of converting full-power signals to
100 kHz.

CMOS construction ensures low power dissipation of typically

5.4 mW for normal operation and 3.6 µW in power-down mode.
The part is available in 44-pin, plastic quad flatpack package
(PQFP) and plastic lead chip carrier (PLCC).

AD7859/AD7859L*

FUNCTIONAL BLOCK DIAGRAM

AV

DD

REF

REF

C

C

AIN1

AIN8

OUT

REF1

REF2

CAL

/

IN

I/P

MUX

CALIBRATION MEMORY

T/H

2.5V

REFERENCE

BUF

CHARGE

REDISTRIBUTION

DAC

AND

CONTROLLER

PARALLEL INTERFACE/CONTROL REGISTER

DB15 – DB0

RD

PRODUCT HIGHLIGHTS

1. Operation with either 3 V or 5 V power supplies.

2. Flexible power management options including automatic
power-down after conversion.

3. By using the power management options a superior power
performance at slower throughput rates can be achieved.
AD7859: 1 mW typ @ 10 kSPS
AD7859L: 1 mW typ @ 20 kSPS

4. Operates with reference voltages from 1.2 V to the supply.

5. Analog input ranges from 0 V to V

6. Self and system calibration.

7. Versatile parallel I/O port.

8. Lower power version AD7859L.

AGND

AD7859/AD7859L

COMP

SAR + ADC

CONTROL

WR

CS

DD

W/B

.

DV

DD

DGND

CLKIN

CONVST

BUSY

SLEEP

*Patent pending.
See page 28 for data sheet index.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

© Analog Devices, Inc., 1996

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] Fax: [phone]

1, 2

AD7859/AD7859L–SPECIFICATIONS

External Reference, f
(AD7859L); SLEEP = Logic High; TA = T

Parameter A Version1B Version1Units Test Conditions/Comments

DYNAMIC PERFORMANCE

Signal to Noise + Distortion Ratio370 71 dB min Typically SNR is 72 dB
(SNR) VIN = 10 kHz Sine Wave, f

Total Harmonic Distortion (THD) –78 –78 dB max VIN = 10 kHz Sine Wave, f

Peak Harmonic or Spurious Noise –78 –78 dB max VIN = 10 kHz Sine Wave, f

Intermodulation Distortion (IMD)
Second Order Terms –78 –78 dB typ fa = 9.983 kHz, fb = 10.05 kHz, f

Third Order Terms –78 –78 dB typ fa = 9.983 kHz, fb = 10.05 kHz, f

Channel-to-Channel Isolation –80 –80 dB typ VIN = 25 kHz

DC ACCURACY

Resolution 12 12 Bits
Integral Nonlinearity ±1 ± 0.5 LSB max 5 V Reference VDD = 5 V
Differential Nonlinearity ± 1 ±1 LSB max Guaranteed No Missed Codes to 12 Bits
Unipolar Offset Error ±5 ±5 LSB max

Unipolar Offset Error Match 2(3) 2 LSB max
Positive Full-Scale Error ±5 ±5 LSB max

Negative Full-Scale Error ± 2 ±2 LSB max
Full-Scale Error Match 1 1 LSB max
Bipolar Zero Error ±1 ±1 LSB typ
Bipolar Zero Error Match 2 2 LSB typ

= 4 MHz (for L Version: 1.8 MHz (08C to +708C) and 1 MHz (–408C to +858C)); f

CLKIN

to T

MIN

, unless otherwise noted.) Specifications in () apply to the AD7859L.

MAX

±2 ±2 LSB typ

±2 ±2 LSB typ

(AVDD = DVDD = +3.0 V to +5.5 V, REFIN/REF

= 200 kHz (AD7859) 100 kHz

SAMPLE

= 200 kHz

(for L Version: f

(for L Version: f

(for L Version: f

(for L Version: f

(for L Version: f

SAMPLE

SAMPLE

SAMPLE

SAMPLE

SAMPLE

SAMPLE

= 100 kHz @ f

= 200 kHz

SAMPLE

= 100 kHz @ f

= 200 kHz

SAMPLE

= 100 kHz @ f

= 100 kHz @ f

SAMPLE

= 100 kHz @ f

SAMPLE

= 2 MHz)

CLKIN

= 2 MHz)

CLKIN

= 2 MHz)

CLKIN

= 200 kHz

= 2 MHz)

CLKIN

= 200 kHz

= 2 MHz)

CLKIN

= 2.5 V

OUT

ANALOG INPUT

Input Voltage Ranges 0 to V

REF

0 to V

REF

Volts i.e., AIN(+) – AIN(–) = 0 to V

Biased Up But AIN(+) Cannot Go Below AIN(–)

±V

/2 ±V

REF

/2 Volts i.e., AIN(+) – AIN(–) = –V

REF

Should Be Biased to +V
Below AIN(–) But Cannot Go Below 0 V

Leakage Current ± 1 ± 1 µA max
Input Capacitance 20 20 pF typ

REFERENCE INPUT/OUTPUT

REFIN Input Voltage Range 2.3/V

DD

2.3/V

DD

V min/max Functional from 1.2 V

Input Impedance 150 150 kΩ typ
REF

Output Voltage 2.3/2.7 2.3/2.7 V min/max

OUT

REF

Tempco 20 20 ppm/°C typ

OUT

LOGIC INPUTS

Input High Voltage, V

INH

2.4 2.4 V min AV

2.1 2.1 V min AV

= DVDD = 4.5 V to 5.5 V

DD

= DVDD = 3.0 V to 3.6 V

DD

CAL Pin 3 3 V min AVDD = DVDD = 4.5 V to 5.5 V

2.4 2.4 V min AVDD = DVDD = 3.0 V to 3.6 V

Input Low Voltage, V

Input Current, I

IN

Input Capacitance, C

INL

IN

4

0.8 0.8 V max AV

0.6 0.6 V max AV

= DVDD = 4.5 V to 5.5 V

DD

= DVDD = 3.0 V to 3.6 V

DD

±10 ±10 µA max Typically 10 nA, V
10 10 pF max

IN

LOGIC OUTPUTS

Output High Voltage, V

OH

4 4 V min AVDD = DVDD = 4.5 V to 5.5 V

2.4 2.4 V min AVDD = DVDD = 3.0 V to 3.6 V

Output Low Voltage, V

OL

0.4 0.4 V max I

= 1.6 mA

SINK

Floating State Leakage Current ±10 ±10 µA max
Floating-State Output Capacitance410 10 pF max
Output Coding Straight (Natural) Binary Unipolar Input Range

2s Complement Bipolar Input Range

, AIN(–) Can Be

REF

/2 to +V

REF

/2 and AIN(+) Can Go

REF

= 0 V or V

DD

/2, AIN(–)

REF

–2–

REV. A

Parameter A Version1B Version1Units Test Conditions/Comments

AD7859/AD7859L

CONVERSION RATE t

CLKIN

× 18
Conversion Time 4.5 (10) 4.5 µs max (L Versions Only, 0°C to +70°C, 1.8 MHz CLKIN)
Track/Hold Acquisition Time 0.5 (1) 0.5 µs min (L Versions Only, –40°C to +85°C, 1.8 MHz CLKIN)

POWER REQUIREMENTS

AV

DD, DVDD

I

DD

Normal Mode

Sleep Mode

5

6

+3.0/+5.5 +3.0/+5.5 V min/max

5.5 (1.95) 5.5 mA max AV

5.5 (1.95) 5.5 mA max AV

= DVDD = 4.5 V to 5.5 V. Typically 4.5 mA

DD

= DVDD = 3.0 V to 3.6 V. Typically 4.0 mA

DD

With External Clock On 10 10 µA typ Full Power-Down. Power Management Bits in Control

Register Set as PMGT1 = 1, PMGT0 = 0.

400 400 µA typ Partial Power-Down. Power Management Bits in

Control Register Set as PMGT1 = 1, PMGT0 = 1.

With External Clock Off 5 5 µA max Typically 1 µA. Full Power-Down. Power Management

Bits in Control Register Set as PMGT1 = 1, PMGT0 = 0.

200 200 µA typ Partial Power-Down. Power Management Bits in

Control Register Set as PMGT1 = 1, PMGT0 = 1.

Normal Mode Power Dissipation 30 (10) 30 (10) mW max V

20 (6.5) 20 (6.5) mW max VDD = 3.6 V: Typically 15 mW (5.4); SLEEP = V

= 5.5 V: Typically 25 mW (8); SLEEP = V

DD

DD

DD

Sleep Mode Power Dissipation

With External Clock On 55 55 µW typ V

36 36 µW typ V

With External Clock Off 27.5 27.5 µW max V

= 5.5 V; SLEEP = 0 V

DD

= 3.6 V; SLEEP = 0 V

DD

= 5.5 V: Typically 5.5 µW; SLEEP = 0 V

DD

18 18 µW max VDD = 3.6 V: Typically 3.6 µW; SLEEP = 0 V

SYSTEM CALIBRATION

Offset Calibration Span
Gain Calibration Span

NOTES

1

Temperature range as follows: A, B Versions, –40°C to +85°C.

2

Specifications apply after calibration.

3

SNR calculation includes distortion and noise components.

4

Not production tested, guaranteed by characterization at initial product release.

5

All digital inputs @ DGND except for CONVST, SLEEP, CAL, and SYNC @ DVDD. No load on the digital outputs. Analog inputs @ AGND.

6

CLKIN @ DGND when external clock off. All digital inputs @ DGND except for CONVST, SLEEP, CAL, and SYNC @ DVDD. No load on the digital outputs.
Analog inputs @ AGND.

7

The offset and gain calibration spans are defined as the range of offset and gain errors that the AD7859/AD7859L can calibrate. Note also that these are voltage spans
and are not absolute voltages (i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–) ±0.05 × V
and the allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted out will be V
This is explained in more detail in the calibration section of the data sheet.

7

7

+0.05 × V
+1.025 × V

/–0.05 × V

REF

/–0.975 × V

REF

V max/min Allowable Offset Voltage Span for Calibration

REF

V max/min Allowable Full-Scale Voltage Span for Calibration

REF

± 0.025 × V

REF

REF

REF

,

).

Specifications subject to change without notice.

REV. A

–3–

AD7859/AD7859L

(AV

= DVDD = +3.0 V to +5.5 V; f

DD

1

TIMING SPECIFICATIONS

Limit at T

MIN

, T

TA = T

MAX

MIN

to T

, unless otherwise noted)

MAX

(A, B Versions)

Parameter 5 V 3 V Units Description

2

f

CLKIN

500 500 kHz min Master Clock Frequency
4 4 MHz max

3

t

1

t

2

t

CONVERT

1.8 1.8 MHz max L Version
100 100 ns min CONVST Pulse Width
50 90 ns max CONVST to BUSY ↑ Propagation Delay

4.5 4.5 µs max Conversion Time = 18 t
10 10 µs max L Version 1.8 MHz CLKIN. Conversion Time = 18 t

t

3

t

4

t

5

t

6

t

7

4

t

8

5

t

9

15 15 ns min HBEN to RD Setup Time
5 5 ns min HBEN to RD Hold Time
0 0 ns min CS to RD to Setup Time
0 0 ns min CS to RD Hold Time
55 55 ns min RD Pulse Width
50 50 ns max Data Access Time After RD
5 5 ns min Bus Relinquish Time After RD
40 40 ns max Bus Relinquish Time After

t

10

t

11

t

12

t

13

t

14

t

15

t

16

t

17

4

t

18

t

19

6

t

CAL

6

t

CAL1

6

t

CAL2

NOTES

1

Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.

2

Mark/Space ratio for the master clock input is 40/60 to 60/40.

3

The CONVST pulse width will here only apply for normal operation. When the part is in power-down mode, a different CONVST pulse width will apply (see Power­Down section).

4

Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.

5

t9 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
time of the part and is independent of the bus loading.

6

The typical time specified for the calibration times is for a master clock of 4 MHz. For the L version the calibration times will be longer than those quoted here due to
the 1.8 MHz master clock.

Specifications subject to change without notice.

60 70 ns min Minimum Time Between Reads
0 0 ns min HBEN to WR Setup Time
5 5 ns max HBEN to WR Hold Time
0 0 ns min CS to WR Setup Time
0 0 ns max CS to WR Hold Time
55 70 ns min WR Pulse Width
10 10 ns min Data Setup Time Before WR
5 5 ns min Data Hold Time After WR
1/2 t

2.5 t

CLKIN
CLKIN

1/2 t

2.5 t

CLKIN
CLKIN

ns min New Data Valid Before Falling Edge of BUSY
ns max CS ↑ to BUSY ↑ in Calibration Sequence

31.25 31.25 ms typ Full Self-Calibration Time, Master Clock Dependent (125013

27.78 27.78 ms typ Internal DAC Plus System Full-Scale Cal Time, Master Clock

3.47 3.47 ms typ System Offset Calibration Time, Master Clock Dependent

= 4 MHz for AD7859 and 1.8 MHz for AD7859L;

CLKIN

CLKIN

RD

t

)

CLKIN

Dependent (111124 t

(13889 t

)

CLKIN

, quoted in the timing characteristics is the true bus relinquish

9

CLKIN

)

CLKIN

–4–

REV. A

AD7859/AD7859L

6

7

1

2
3

4

5

8
9

10

11

23

24

25

26

27

28

29

30

31

32

33

22

21

20

19

18

17

16

15

14

13

12

AD7859

TOP VIEW

(Not to Scale)

PIN NO. 1 IDENTIFIER

NC

W/B

REFIN/REF

OUT

AV

DD

C

REF1

AIN0

C

REF2

AGND

AIN1
AIN2
AIN3

DV

DD

DGND

DB5

DB6

DB7

DB8/HBEN

DB9

DB10

DB11

NC

DB4

CONVST

NC

DB14

CLKIN

BUSY

DB12

DB15

DB13

WR

RD

CS

NC

DB1

DB2

DB3

AIN4

AIN5

AIN6

AIN7

CAL

SLEEP

DB0

34

35

36

37

38

39

40

41

42

43

44

TO OUTPUT

PIN

1.6mA I

50pF

200µA I

OL

+2.1V

OH

Figure 1. Load Circuit for Digital Output Timing
Specifications

ORDERING GUIDE

Linearity Power
Error Dissipation Package

Model (LSB)

1

(mW) Option

2

AD7859AP ±1 15 P-44A
AD7859AS ±1 15 S-44
AD7859BS ±1/2 15 S-44
AD7859LAS
EVAL-AD7859CB
EVAL-CONTROL BOARD

NOTES

1

Linearity error refers to the integral linearity error.

2

P = PLCC; S = PQFP.

3

L signifies the low power version.

4

This can be used as a stand-alone evaluation board or in conjunction with the

EVAL-CONTROL BOARD for evaluation/demonstration purposes.

5

This board is a complete unit allowing a PC to control and communicate with
all Analog Devices, Inc. evaluation boards ending in the CB designators.

For more information on Analog Devices products and evaluation boards, visit
our World Wide Web home page at http://www.analog.com.

3

±1 5.5 S-44

4

5

ABSOLUTE MAXIMUM RATINGS

1

(TA = +25°C unless otherwise noted)

AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DV

to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DD

AV

to DVDD . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

DD

Analog Input Voltage to AGND . . . . –0.3 V to AV

Digital Input Voltage to DGND . . . . –0.3 V to DV

Digital Output Voltage to DGND . . . –0.3 V to DV
REF

/REF

IN

Input Current to Any Pin Except Supplies

to AGND . . . . . . . . . –0.3 V to AVDD + 0.3 V

OUT

2

. . . . . . . . ±10 mA

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

DD

Operating Temperature Range

Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

PQFP Package, Power Dissipation . . . . . . . . . . . . . . 450 mW

θ

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 95°C/W

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

PLCC Package, Power Dissipation . . . . . . . . . . . . . . 500 mW

θ

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 55°C/W

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >1500 kV

NOTES

1

Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

2

Transient currents of up to 100 mA will not cause SCR latchup.

PINOUT FOR PLCC

WR

RD

CS

7

NC

8

W/B

REFIN/REF

9

OUT

AV

10

DD

11
12
13
14
15

16
17

18 19 20 21 22 23 24 25 26 27 28

AGND

C

REF1

C

REF2

AIN0
AIN1
AIN2
AIN3

AIN4

AIN5

AIN6

CONVST

BUSY

21443456

AD7859

TOP VIEW

(Not to Scale)

CAL

AIN7

CLKIN

SLEEP

DB15

DB0

DB14

DB1

42 41 4043

DB13

DB2

DB12

NC

NC

DB3

39

NC
DB11

38
37

DB10

36

DB9

35

DB8/HBEN

34

DGND
DV

33
32

DB7

31

DB6

30

DB5

29

DB4

DD

PINOUT FOR PQFP

REV. A

–5–

AD7859/AD7859L

TERMINOLOGY
Integral Nonlinearity

This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The end­points of the transfer function are zero scale, a point 1/2 LSB
below the first code transition, and full scale, a point 1/2 LSB
above the last code transition.

Differential Nonlinearity

This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.

Unipolar Offset Error

This is the deviation of the first code transition (00 . . . 000 to
00 . . . 001) from the ideal AIN(+) voltage (AIN(–) + 1/2 LSB)
when operating in the unipolar mode.

Positive Full-Scale Error

This applies to the unipolar and bipolar modes and is the devia­tion of the last code transition from the ideal AIN(+) voltage
(AIN(–) + Full Scale – 1.5 LSB) after the offset error has been
adjusted out.

Negative Full-Scale Error

This applies to the bipolar mode only and is the deviation of the
first code transition (10 . . . 000 to 10 . . . 001) from the ideal
AIN(+) voltage (AIN(–) – V

/2 + 0.5 LSB).

REF

Bipolar Zero Error

This is the deviation of the midscale transition (all 0s to all 1s)
from the ideal AIN(+) voltage (AIN(–) – 1/2 LSB).

Track/Hold Acquisition Time

The track/hold amplifier returns into track mode and the end of
conversion. Track/Hold acquisition time is the time required for
the output of the track/hold amplifier to reach its final value,
within ±1/2 LSB, after the end of conversion.

Signal to (Noise + Distortion) Ratio

This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the sum of all nonfundamental sig­nals up to half the sampling frequency (f

/2), excluding dc. The

S

ratio is dependent on the number of quantization levels in the
digitization process; the more levels, the smaller the quantiza­tion noise. The theoretical signal to (noise + distortion) ratio for
an ideal N-bit converter with a sine wave input is given by:

Signal to (Noise + Distortion) = (6.02 N +1.76)dB

Thus for a 12-bit converter, this is 74 dB.

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7859/AD7859L, it is
defined as:

2

2

2

2

2

+V

5

)

6

THD (dB) =20 log

(V

+V

+V

2

3

+V

4

V

1

where V1 is the rms amplitude of the fundamental and V2, V3,
V

, V5 and V6 are the rms amplitudes of the second through the

4

sixth harmonics.

Peak Harmonic or Spurious Noise

Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to f

/2 and excluding dc) to the rms value of the

S

fundamental. Normally, the value of this specification is deter­mined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor, it will be a
noise peak.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are
those for which neither m nor n are equal to zero. For example,
the second order terms include (fa + fb) and (fa – fb), while the
third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and
(fa – 2fb).

Testing is performed using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used. In
this case, the second order terms are usually distanced in fre­quency from the original sine waves while the third order terms
are usually at a frequency close to the input frequencies. As a
result, the second and third order terms are specified separately.
The calculation of the intermodulation distortion is as per the
THD specification where it is the ratio of the rms sum of the
individual distortion products to the rms amplitude of the sum
of the fundamentals expressed in dBs.

–6–

REV. A

AD7859/AD7859L

PIN FUNCTION DESCRIPTION

Mnemonic Description

CONVST Convert Start. Logic input. A low to high transition on this input puts the track/hold into its hold

mode and starts conversion. When this input is not used, it should be tied to DV

RD Read Input. Active low logic input. Used in conjunction with CS to read from internal registers.
WR Write Input. Active low logic input. Used in conjunction with CS to write to internal registers.
CS Chip Select Input. Active low logic input. The device is selected when this input is active.

/ Reference Input/Output. This pin is connected to the internal reference through a series resistor and is the

REF

IN

REF

OUT

reference source for the analog-to-digital converter. The nominal reference voltage is 2.5 V and this appears at the
pin. This pin can be overdriven by an external reference or can be taken as high as AV
AV

AV

DD

, then the C

DD

Analog Supply Voltage, +3.0 V to +5.5 V.

pin should also be tied to AVDD.

REF1

AGND Analog Ground. Ground reference for track/hold, reference and DAC.
DV

DD

Digital Supply Voltage, +3.0 V to +5.5 V.
DGND Digital Ground. Ground reference point for digital circuitry.
C

REF1

Reference Capacitor (0.1 µF multilayer ceramic). This external capacitor is used as a charge source for the inter-

nal DAC. The capacitor should be tied between the pin and AGND.
C

REF2

Reference Capacitor (0.01 µF ceramic disc). This external capacitor is used in conjunction with the on-chip refer-

ence. The capacitor should be tied between the pin and AGND.
AIN1–AIN8 Analog Inputs. Eight analog inputs which can be used as eight single ended inputs (referenced to AGND) or four

pseudo differential inputs. Channel configuration is selected by writing to the control register. None of the inputs

can go below AGND or above AV

B Word/Byte input. When this input is at a logic 1, data is transferred to and from the AD7859/AD7859L in 16-bit

W/

at any time. See Table III for channel selection.

DD

words on pins DB0 to DB15. When this pin is at a Logic 0, byte transfer mode is enabled. Data is transferred on

pins DB0 to DB7 and pin DB8/HBEN assumes its HBEN functionality.
DB0–DB7 Data Bits 0 to 7. Three state data I/O pins that are controlled by

CS, RD and WR. Data output is straight binary

(unipolar mode) or twos complement (bipolar mode).
DB8/HBEN Data Bit 8/High Byte Enable. When W/

trolled by

CS, RD and WR. When W/B is low, this pin acts as the High Byte Enable pin. When HBEN is low,

B is high, this pin acts as Data Bit 7, a three state data I/O pin that is con-

then the low byte of data being written to or read from the AD7859/AD7859L is on DB0 to DB7. When HBEN

is high, then the high byte of data being written to or read from the AD7859/AD7859L is on DB0 to DB7.
DB9–DB15 Data Bits 9 to 15. Three state data I/O pins that are controlled by

CS, RD and WR. Data output is straight bi-

nary (unipolar mode) or twos complement (bipolar mode).
CLKIN Master Clock Signal for the device (4 MHz for AD7859, 1.8 MHz for AD7859L). Sets the conversion and calibra-

tion times.
CAL Calibration Input. A logic 0 in this pin resets all logic. A rising edge on this pin initiates a calibration. This input

overrides all other internal operations.
BUSY Busy Output. The busy output is triggered high when a conversion or a calibration is initiated, and remains high

until the conversion or calibration is completed.
SLEEP Sleep Input. This pin is used in conjunction with the PGMT0 and PGMT1 bits in the control register to deter-

mine the power-down mode. Please see the “Power-Down Options” section for details.
NC No connect pins. These pins should be left unconnected.

DD

.

. When this pin is tied to

DD

REV. A

–7–

AD7859/AD7859L

TEST

REGISTER

CALIBRATION

REGISTERS

STATUS

REGISTER

GAIN (1)

OFFSET (1)

DAC (8)

GAIN (1)

OFFSET (1)

OFFSET (1) GAIN (1)

01 10 11

00 01 10 11

CALSLT1, CALSLT0

DECODE

ADC OUTPUT

DATA REGISTER

00

RDSLT1, RDSLT0

DECODE

AD7859/AD7859L ON-CHIP REGISTERS

The AD7859/AD7859L powers up with a set of default conditions. The only writing that is required is to select the channel configu­ration. Without performing any other write operations, the AD7859/AD7859L still retains the flexibility for performing a full power­down and a full self-calibration.

Extra features and flexibility such as performing different power-down options, different types of calibrations, including system cali­bration, and software conversion start can be selected by writing to the part.

The AD7859/AD7859L contains a Control register, ADC output data register, Status register, Test register and 10 Cali-
bration registers. The control register is write-only, the ADC output data register and the status register are read-only, and the test
and calibration registers are both read/write registers. The test register is used for testing the part and should not be written to.

Addressing the On-Chip Registers

Writing

When writing to the AD7859/AD7859L, a 16-bit word of data must be transferred. The 16 bits of data is written as either a 16-bit
word, or as two 8-bit bytes, depending on the logic level at the W/
DB15, where DB0 is the LSB and DB15 is the MSB of the write. When W/
and data is transferred in two 8-bit bytes on pins DB0 to DB7, pin DB0 being the LSB of each transfer and pin DB7 being the MSB.
When writing to the AD7859/AD7859L in byte mode, the low byte must be written first followed by the high byte. The two MSBs
of the complete 16-bit word, ADDR1 and ADDR0, are decoded to determine which register is addressed, and the 14 LSBs are writ­ten to the addressed register. Table I shows the decoding of the address bits, while Figure 2 shows the overall write register hierarchy.

Table I. Write Register Addressing

ADDR1 ADDR0 Comment

0 0 This combination does not address any register.
0 1 This combination addresses the TEST REGISTER. The 14 LSBs of data are written to the test register.
1 0 This combination addresses the CALIBRATION REGISTERS. The 14 LSBs of data are written to the

selected calibration register.

1 1 This combination addresses the CONTROL REGISTER. The 14 LSBs of data are written to the control

register.

Reading

To read from the various registers the user must first write to Bits 6 and 7 in the Control Register, RDSLT0 and RDSLT1. These
bits are decoded to determine which register is addressed during a read operation. Table II shows the decoding of the read address
bits while Figure 3 shows the overall read register hierarchy. The power-up status of these bits is 00 so that the default read will be
from the ADC output data register. As with writing to the AD7859/AD7859L either word or byte mode can be used. When reading
from the calibration registers in byte mode, the low byte must be read first.

Once the read selection bits are set in the control register all subsequent read operations that follow are from the selected register un­til the read selection bits are changed in the control register.

Table II. Read Register Addressing

B pin. When W/B is high, the 16 bits are transferred on DB0 to

B is low, DB8/HBEN assumes its HBEN functionality

RDSLT1 RDSLT0 Comment

0 0 All successive read operations are from the ADC OUTPUT DATA REGISTER. This is the default power-

up setting. There is always four leading zeros when reading from the ADC output data register.

0 1 All successive read operations are from the TEST REGISTER.
1 0 All successive read operations are from the CALIBRATION REGISTERS.
1 1 All successive read operations are from the STATUS REGISTER.

ADDR1, ADDR0

DECODE

01 10 11

Figure 2. Write Register Hierarchy/Address Decoding

TEST

REGISTER

GAIN (1)

CALSLT1, CALSLT0

DECODE

OFFSET (1)

DAC (8)

00 01 10 11

CALIBRATION

REGISTERS

GAIN (1)

OFFSET (1)

OFFSET (1) GAIN (1)

CONTROL

REGISTER

Figure 3. Read Register Hierarchy/Address Decoding

–8–

REV. A

AD7859/AD7859L

CONTROL REGISTER

The arrangement of the control register is shown below. The control register is a write only register and contains 14 bits of data. The
control register is selected by putting two 1s in ADDR1 and ADDR0. The function of the bits in the control register is described
below. The power-up status of all bits is 0.

MSB

SGL/DIFF CHSLT2 CHSLT1 CHSLT0 PMGT1 PMGT0 RDSLT1

RDSLT0 AMODE CONVST CALMD CALSLT1 CALSLT0 STCAL

LSB

CONTROL REGISTER BIT FUNCTION DESCRIPTION

Bit Mnemonic Comment

13 SGL/

DIFF A 0 in this bit position configures the input channels for pseudo-differential mode. A 1 in this bit posi-

tion configures the input channels in single ended mode. Please see Table III for channel selection.

12 CHSLT2 These three bits are used to select the analog input on which the conversion is performed. The analog
11 CHSLT1 inputs can be configured as eight single-ended channels or four pseudo-differential channels. The
10 CHSLT0 default selection is AIN1 for the positive input and AIN2 for the negative input. Please see Table III for

channel selection information.

9 PMGT1 Power Management Bits. These two bits are used with the

SLEEP pin for putting the part into various

8 PMGT0 Power-Down modes (See Power-Down section for more details).
7 RDSLT1 Theses two bits determine which register is addressed for the read operations. Please see Table II.

6 RDSLT0
5 AMODE Analog Mode Bit. This bit has two different functions, depending on the status of the SGL/

When SGL/
this bit position selects the unipolar range, 0 to V
this bit position selects the bipolar range –V
+V

REF

swing from 0 V to +V

When SGL/

DIFF is 0, AMODE selects between unipolar and bipolar analog input ranges. A logic 0 in

(i.e., AIN(+) – AIN(–) = 0 to V

REF

/2 to +V

REF

/2). In this case AIN(–) needs to be tied to at least +V

.

REF

/2 (i.e., AIN(+) – AIN(–) = –V

REF

/2 to allow AIN(+) to have a full input

REF

DIFF is 1, AMODE selects the source for the AIN(–) channel of the sample and hold cir-

DIFF bit.

). A logic 1 in

REF

REF

/2 to

cuitry. If AMODE is a 0, AGND is selected. If AMODE is a 1, then AIN8 is selected. Please see
Table III for more information.

4 CONVST Conversion Start Bit. A logic 1 in this bit position starts a single conversion, and this bit is automatically

reset to 0 at the end of conversion. This bit may also be used in conjunction with system calibration (see

calibration section on page 21).
3 CALMD Calibration Mode Bit. A 0 here selects self-calibration and a 1 selects a system calibration (see Table IV).
2 CALSLT1 Calibration Selection Bits 1 and 0. These bits have two functions, depending on the STCAL bit.

1 CALSLT0 With the STCAL bit set to 1, the CALSLT1 and CALSLT0 bits, along with the CALMD bit, deter-

mine the type of calibration performed by the part (see Table IV).

With the STCAL bit set to 0, the CALSLT1 and CALSLT0 bits are decoded to address the calibration

register for read/write of calibration coefficients (see Table V for more details).
0 STCAL Start Calibration Bit. When STCAL is set to a 1, a calibration is performed, as determined by the

CALMD, CALSLT1 and CALSLT0 bits. Please see Table IV. When STCAL is set to a zero, no cali-

bration is performed.

REV. A

–9–