Analog Devices AD7858 Datasheet

3 V to 5 V Single Supply, 200 kSPS

a

FEATURES
Specified for V
AD7858—200 kSPS; AD7858L—100 kSPS
System and Self-Calibration with Autocalibration on

Power-Up
Eight Single-Ended or Four Pseudo-Differential Inputs
Low Power

AD7858: 12 mW (V

AD7858L: 4.5 mW (V
Automatic Power-Down After Conversion (25 ␮W)
Flexible Serial Interface:

8051/SPI™/QSPI™/␮P Compatible
24-Lead DIP, SOIC, and SSOP Packages

APPLICATIONS
Battery-Powered Systems (Personal Digital Assistants,

Medical Instruments, Mobile Communications)
Pen Computers
Instrumentation and Control Systems
High-Speed Modems

GENERAL DESCRIPTION

The AD7858/AD7858L are high-speed, low-power, 12-bit
ADCs that operate from a single 3 V or 5 V power supply, the
AD7858 being optimized for speed and the AD7858L for low
power. The ADC powers up with a set of default conditions at
which time it can be operated as a read-only ADC. The ADC
contains self-calibration and system calibration options to en­sure accurate operation over time and temperature and have a
number of power-down options for low-power applications.
The part powers up with a set of default conditions and can
operate as a read-only ADC.

The AD7858 is capable of 200 kHz throughput rate while the
AD7858L is capable of 100 kHz throughput rate. The input
track-and-hold acquires a signal in 500 ns and features a
pseudo-differential sampling scheme. The AD7858/AD7858L
voltage range is 0 to V
Input signal range is to the supply and the part is capable of con­verting full power signals to 100 kHz.

CMOS construction ensures low power dissipation of typically

4.5 mW for normal operation and 1.15 mW in power-down
mode with a throughput rate of 10 kSPS (V
is available in 24-lead, 0.3 inch-wide dual-in-line package
(DIP), 24-lead small outline (SOIC), and 24-lead small shrink
outline (SSOP) packages.

of 3 V to 5.5 V

DD

= 3 V)

DD

= 3 V)

DD

with straight binary output coding.

REF

= 3 V). The part

DD

8-Channel, 12-Bit Sampling ADC

AD7858/AD7858L*

FUNCTIONAL BLOCK DIAGRAM

AV

DD

REFIN/REF

C

C

AIN1

AIN8

OUT

REF1

REF2

CAL

I/P

T/H

MUX

2.5V

REFERENCE

BUF

CHARGE

REDISTRIBUTION

DAC

CALIBRATION
MEMORY AND
CONTROLLER

SERIAL INTERFACE/CONTROL REGISTER

SYNC

DIN DOUT SCLK

PRODUCT HIGHLIGHTS

1. Specified for 3 V and 5 V supplies.

2. Automatic calibration on power-up.

3. Flexible power management options including automatic
power-down after conversion.

4. Operates with reference voltages from 1.2 V to V

5. Analog input range from 0 V to V

6. Eight single-ended or four pseudo-differential input channels.

7. System and self-calibration.

8. Versatile serial I/O port (SPI/QSPI/8051/µP).

9. Lower power version AD7858L.

AGND

AD7858/

AD7858L

COMP

SAR AND ADC

CONTROL

.

DD

DD

DV

DGND

CLKIN

CONVST

BUSY

SLEEP

.

DD

*Patent pending.

See page 31 for data sheet index.
SPI and QSPI are trademarks of Motorola, Inc.

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

1, 2

AD7858/AD7858L–SPECIFICATIONS

Reference unless otherwise noted, f
200 kHz (AD7858), 100 kHz (AD7858L); SLEEP = Logic High; TA = T

P

arameter A Version1B Version

DYNAMIC PERFORMANCE

Signal to Noise + Distortion Ratio
(SNR) V
Total Harmonic Distortion (THD) –78 –78 dB max V
Peak Harmonic or Spurious Noise –78 –78 dB max VIN = 10 kHz Sine Wave, f

= 4 MHz (1.8 MHz B Grade (0ⴗC to +70ⴗC), 1 MHz A and B Grades (–40ⴗC to +85ⴗC) for L Version); f

CLKIN

to T

MIN

1

3

70 71 dB min Typically SNR is 72 dB

, unless otherwise noted.) Specifications in ( ) apply to the AD7858L.

MAX

Units Test Conditions/Comments

(AVDD = DVDD = +3.0 V to +5.5 V, REFIN/REF

= 10 kHz Sine Wave, f

IN

= 10 kHz Sine Wave, f

IN

= 200 kHz (100 kHz)

SAMPLE

= 200 kHz (100 kHz)

SAMPLE

= 200 kHz (100 kHz)

SAMPLE

Intermodulation Distortion (IMD)
Second Order Terms –78 –80 dB typ fa = 9.983 kHz, fb = 10.05 kHz, f
Third Order Terms –78 –80 dB typ fa = 9.983 kHz, fb = 10.05 kHz, f

= 200 kHz (100 kHz)

SAMPLE

= 200 kHz (100 kHz)

SAMPLE

Channel-to-Channel Isolation –90 –90 dB typ VIN = 25 kHz

DC ACCURACY Any Channel

Resolution 12 12 Bits
Integral Nonlinearity ± 1 ±1 LSB max 2.5 V External Reference VDD = 3 V, VDD = 5 V (B Grade Only)

±1 ± 0.5 LSB max 5 V External Reference V

DD

= 5 V

(±1) LSB max (L Version, 5 V External Reference, VDD = 5 V)

(±1) LSB max (L Version)

Differential Nonlinearity ±1 ± 1 LSB max Guaranteed No Missed Codes to 12 Bits. 2.5 V External

Reference VDD = 3 V, 5 V External Reference, VDD = 5 V

Total Unadjusted Error ±1 ± 1 LSB typ
Unipolar Offset Error ±5 ± 5 LSB max Typically ±2 LSBs

±2.5 ± 2.5 LSB max 5 V External Reference, VDD = 5 V
(± 3) (± 3) LSB max (L Version)
(± 1.5) (±1.5) LSB max (L Version, 5 V External Reference, VDD = 5 V)

Unipolar Offset Error Match 1.5 1.5 LSB max
Positive Full-Scale Error ± 4 ± 4 LSB max

±1.5 ± 1.5 LSB max 5 V External Reference, V

DD

= 5 V

Positive Full-Scale Error Match 1 1 LSB max

ANALOG INPUT

Input Voltage Ranges 0 to V

REF

0 to V

REF

Volts i.e., AIN(+) – AIN(–) = 0 to V

, AIN(–) can be biased

REF

up but AIN(+) cannot go below AIN(–)

Leakage Current ±1 ± 1 µA max
Input Capacitance 20 20 pF typ

REFERENCE INPUT/OUTPUT

REFIN Input Voltage Range 2.3/V

DD

2.3/V

DD

V min/max Functional from 1.2 V

Input Impedance 150 150 kΩ typ
REF

Output Voltage 2.3/2.7 2.3/2.7 V min/max

OUT

REF

Tempco 20 20 ppm/°C typ

OUT

LOGIC INPUTS

Input High Voltage, V

Input Low Voltage, V

Input Current, I
Input Capacitance, C

IN

IN

INH

INL

4

2.4 2.4 V min AV

2.1 2.1 V min AV

0.8 0.8 V max AV

0.6 0.6 V max AV

= DVDD = 4.5 V to 5.5 V

DD

= DVDD = 3.0 V to 3.6 V

DD

= DVDD = 4.5 V to 5.5 V

DD

= DVDD = 3.0 V to 3.6 V

DD

±10 ± 10 µA max Typically 10 nA, V
10 10 pF max

= 0 V or V

IN

DD

LOGIC OUTPUTS

Output High Voltage, V

Output Low Voltage, V

OL

OH

4 4 V min AV

2.4 2.4 V min AV

0.4 0.4 V max I

I

= 200 µA

SOURCE

= DVDD = 4.5 V to 5.5 V

DD

= DVDD = 3.0 V to 3.6 V

DD

= 0.8 mA

SINK

Floating-State Leakage Current ± 10 ± 10 µA max
Floating-State Output Capacitance410 10 pF max
Output Coding Straight (Natural) Binary

CONVERSION RATE

Conversion Time 4.6 (18) 4.6 µs max (L Versions Only, –40°C to +85°C, 1 MHz CLKIN)

(10) µs max (L Versions Only, 0°C to +70°C, 1.8 MHz CLKIN)

Track/Hold Acquisition Time 0.4 (1) 0.4 (1) µs min (L Versions Only)

= 2.5 V External

OUT

SAMPLE

=

–2–

REV. B

AD7858/AD7858L

Parameter A Version

1

B Version1Units Test Conditions/Comments

DYNAMIC PERFORMANCE

AV

DD, DVDD

I

DD

Normal Mode

Sleep Mode

5

6

+3.0/+5.5 +3.0/+5.5 V min/max

6 (1.9) 6 (1.9) mA max AV

5.5 (1.9) 5.5 (1.9) mA max AV

= DVDD = 4.5 V to 5.5 V. Typically 4.5 mA (1.5)

DD

= DVDD = 3.0 V to 3.6 V. Typically 4.0 mA (1.5 mA)

DD

With External Clock On 10 10 µA typ Full Power-Down. Power Management Bits in Control

Register Set as PMGT1 = 1, PMGT0 = 0

400 400 µA typ Partial Power-Down. Power Management Bits in

Control Register Set as PMGT1 = 1, PMGT0 = 1

With External Clock Off 5 5 µA max Typically 1 µA. Full Power-Down. Power Management Bits

in Control
Register Set as PMGT1 = 1, PMGT0 = 0

200 200 µA typ Partial Power-Down. Power Management Bits in Control

Register Set as PMGT1 = 1, PMGT0 = 1

Normal-Mode Power Dissipation 33 (10.5) 33 (10.5) mW max V

20 (6.85) 20 (6.85) mW max VDD = 3.6 V. Typically 15 mW (5.4); SLEEP = V

= 5.5 V. Typically 25 mW (8); SLEEP = V

DD

DD

DD

Sleep Mode Power Dissipation

With External Clock On 55 55 µW typ V

36 36 µW typ V

With External Clock Off 27.5 27.5 µW max V

= 5.5 V. SLEEP = 0 V

DD

= 3.6 V. SLEEP = 0 V

DD

= 5.5 V. Typically 5.5 µW; SLEEP = 0 V

DD

18 18 µW max VDD = 3.6 V. Typically 3.6 µW; SLEEP = 0 V

SYSTEM CALIBRATION

Offset Calibration Span
Gain Calibration Span

NOTES

1

Temperature ranges as follows: A, B Versions: –40°C to +85°C. For L Versions, A and B Versions f
B Version f

2

Specifications apply after calibration.

3

SNR calculation includes distortion and noise components.

4

Sample tested @ +25°C to ensure compliance.

5

All digital inputs @ DGND except for CONVST, SLEEP, CAL, and SYNC @ DVDD. No load on the digital outputs. Analog inputs @ AGND.

6

CLKIN @ DGND when external clock off. All digital inputs @ DGND except for CONVST, SLEEP, CAL, and SYNC @ DVDD. No load on the digital
outputs. Analog inputs @ AGND.

7

The Offset and Gain Calibration Spans are defined as the range of offset and gain errors that the AD7858/AD7858L can calibrate. Note also that these are voltage

= 1.8 MHz over 0°C to +70°C temperature range.

CLKIN

7

7

+0.05 × V
+1.025 × V

/–0.05 × V

REF

/–0.975 × V

REF

REF

V max/min Allowable Offset Voltage Span for Calibration
V max/min Allowable Full-Scale Voltage Span for Calibration

REF

= 1 MHz over –40°C to +85°C temperature range,

CLKIN

spans and are not absolute voltages ( i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–)
±0.05 × V
V

REF

, and the allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted out will be

REF

± 0.025 × V

). This is explained in more detail in the Calibration section of the data sheet.

REF

Specifications subject to change without notice.

REV. B

–3–

AD7858/AD7858L

TIMING SPECIFICATIONS

(AV

= DVDD = +3.0 V to +5.5 V; f

DD

1

TA = T

MIN

to T

, unless otherwise noted)

MAX

= 4 MHz for AD7858 and 1.8/1 MHz for AD7858L;

CLKIN

Limit at T

MIN

, T

MAX

(A, B Versions)

Parameter 5 V 3 V Units Description

f

CLKIN

2

500 500 kHz min Master Clock Frequency
4 4 MHz max

1.8 1.8 MHz max L Version, 0°C to +70°C, B Grade Only
1 1 MHz max L Version, –40°C to +85°C

f

SCLK

3

t

1

t

2

t

CONVERT

t

3

4

t

4

4

t

5

4

t

6

t

7

t

8

t

9

t

10

t

11

5

t

12

t

13

6

t

14

t

15

t

16

7

t

CAL

7

t

CAL1

7

t

CAL2

NOTES

1

Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
See Table XI and timing diagrams for different interface modes and Calibration.

2

Mark/Space ratio for the master clock input is 40/60 to 60/40.

3

The CONVST pulsewidth will apply here only for normal operation. When the part is in power-down mode, a different CONVST pulsewidth will apply
(see Power-Down section).

4

Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.

5

t12 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time, t12, quoted in the timing characteristics is the true bus
relinquish time of the part and is independent of the bus loading.

6

t14 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the Timing Characteristics is the
true delay of the part in turning off the output drivers and configuring the DIN line as an input. Once this time has elapsed the user can drive the DIN line
knowing that a bus conflict will not occur.

7

The typical time specified for the calibration times is for a master clock of 4 MHz. For the L version the calibration times will be longer than those quoted here due to
the 1.8/1 MHz master clock.

Specifications subject to change without notice.

4 4 MHz max
100 100 ns min CONVST Pulsewidth
50 90 ns max CONVST↓ to BUSY↑ Propagation Delay

4.6 4.6 µs max Conversion Time = 18 t
10 (18) 10 (18) µs max L Version 1.8 (1) MHz CLKIN. Conversion Time = 18 t
–0.4 t
⫿0.4 t

SCLK

SCLK

–0.4 t
⫿0.4 t

SCLK

SCLK

ns min SYNC↓ to SCLK↓ Setup Time (Noncontinuous SCLK Input)
ns min/max SYNC↓ to SCLK↓ Setup Time (Continuous SCLK Input)

CLKIN

CLKIN

50 90 ns max Delay from SYNC↓ Until DOUT Three-State Disabled
50 90 ns max Delay from SYNC↓ Until DIN Three-State Disabled
75 115 ns max Data Access Time After SCLK↓
40 60 ns min Data Setup Time Prior to SCLK↑
20 30 ns min Data Valid to SCLK Hold Time

0.4 t

0.4 t

SCLK

SCLK

0.4 t

0.4 t

SCLK

SCLK

ns min SCLK High Pulsewidth
ns min SCLK Low Pulsewidth

30 50 ns min SCLK↑ to SYNC↑ Hold Time (Noncontinuous SCLK)
30/0.4 t

SCLK

50/0.4 t

SCLK

ns min/max (Continuous SCLK)

50 50 ns max Delay from SYNC↑ Until DOUT Three-State Enabled
90 130 ns max Delay from SCLK↑ to DIN Being Configured as Output
50 90 ns max Delay from SCLK↑ to DIN Being Configured as Input

2.5 t

2.5 t

CLKIN

CLKIN

2.5 t

2.5 t

CLKIN

CLKIN

ns max CAL↑ to BUSY↑ Delay
ns max CONVST↓ to BUSY↑ Delay in Calibration Sequence

31.25 31.25 ms typ Full Self-Calibration Time, Master Clock Dependent
(125013 t

CLKIN

)

27.78 27.78 ms typ Internal DAC Plus System Full-Scale Calibration Time, Master
Clock Dependent (111114 t

CLKIN

)

3.47 3.47 ms typ System Offset Calibration Time, Master Clock Dependent
(13899 t

CLKIN

)

–4–

REV. B

AD7858/AD7858L

TYPICAL TIMING DIAGRAMS

Figures 2 and 3 show typical read and write timing diagrams for
serial Interface Mode 2. The reading and writing occurs after
conversion in Figure 2, and during conversion in Figure 3. To
attain the maximum sample rate of 100 kHz (AD7858L) or
200 kHz (AD7858), reading and writing must be performed
during conversion as in Figure 3. At least 400 ns acquisition
time must be allowed (the time from the falling edge of BUSY
to the next rising edge of CONVST) before the next conversion
begins to ensure that the part is settled to the 12-bit level. If the
user does not want to provide the CONVST signal, the conver­sion can be initiated in software by writing to the control register.

t

= 4.6␮s MAX, 10␮s MAX FOR L VERSION

CONVERT

t

= 100ns MIN, t4 = 50/90ns MAX 5V/3V, t7 = 40/60ns MIN 5V/3V

1

t

CONVERT

t

4

THREE-STATE

t

3

15616

t

DB15 DB11 DB0

t

7

DB15 DB11 DB0

CONVST (I/P)

BUSY (O/P)

SYNC (I/P)

SCLK (I/P)

DOUT (O/P)

DIN (I/P)

t

1

t

2

1.6mA

I

OL

OUTPUT

PIN

TO

100pF

C

L

200␮A

I

+2.1V

OH

Figure 1. Load Circuit for Digital Output Timing

Specifications

t

9

t

10

6

t

8

t

6

t

11

t

12

THREE-

STATE

Figure 2. AD7858/AD7858L Timing Diagram for Interface Mode 2 (Reading/Writing After Conversion)

t

= 4.6␮s MAX, 10␮s MAX FOR L VERSION

CONVERT

t

CONVST (I/P)

BUSY (O/P)

SYNC (I/P)

SCLK (I/P)

DOUT (O/P)

DIN (I/P)

= 100ns MIN,

t

1

t

2

1

t

4

THREE-STATE

t

= 50/90ns MAX 5V/3V,

4

t

CONVERT

t

3

15616

t

6

DB15 DB11 DB0

t

t

DB15 DB11 DB0

8

7

t

= 40/60ns MIN 5V/3V

7

t

9

t

10

t

6

t

11

t

12

THREE-

STATE

Figure 3. AD7858/AD7858L Timing Diagram for Interface Mode 2 (Reading/Writing During Conversion)

REV. B

–5–

AD7858/AD7858L

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

(TA = +25°C unless otherwise noted)

AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DV

to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DD

AV

to DVDD . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

DD

Analog Input Voltage to AGND . . . . –0.3 V to AV

Digital Input Voltage to DGND . . . . –0.3 V to DV

Digital Output Voltage to DGND . . . –0.3 V to DV
REF

IN

/REF

to AGND . . . . . . . . . –0.3 V to AVDD + 0.3 V

OUT

Input Current to Any Pin Except Supplies
Operating Temperature Range

Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C

1

2

. . . . . . . ±10 mA

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

DD

SOIC, SSOP Package, Power Dissipation . . . . . . . . . . 450 mW

Thermal Impedance . . . 75°C/W (SOIC) 115°C/W (SSOP)

θ

JA

θ

Thermal Impedance . . . . 25°C/W (SOIC) 35°C/W (SSOP)

JC

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

Transient currents of up to 100 mA will not cause SCR latch-up.

Storage Temperature Range . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 105°C/W

θ

JA

θ

Thermal Impedance . . . . . . . . . . . . . . . . . . . . 34.7°C/W

JC

Lead Temperature, (Soldering, 10 sec) . . . . . . . . . . +260°C

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7858/AD7858L features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.

ORDERING GUIDE

Linearity Power
Error Dissipation Package

Model (LSB)

1

(mW) Options

2

AD7858AN ± 1 20 N-24
AD7858BN ± 1/2 20 N-24
AD7858LAN
AD7858LBN

3

3

±1 6.85 N-24
±1 6.85 N-24

AD7858AR ±1 20 R-24
AD7858BR ± 1/2 20 R-24
AD7858LAR
AD7858LBR
AD7858LARS
EVAL-AD7858CB
EVAL-CONTROL BOARD

NOTES

1

Linearity error here refers to integral linearity error.

2

N = Plastic DIP; R = SOIC; RS = SSOP.

3

L signifies the low-power version.

4

This can be used as a stand-alone evaluation board or in conjunction with the EVAL-

CONTROL BOARD for evaluation/demonstration purposes.

5

This board is a complete unit allowing a PC to control and communicate with all

Analog Devices evaluation boards ending in the CB designators.

3

3

3

4

±1 6.85 R-24
±1 6.85 R-24
±1 6.85 RS-24

5

PIN CONFIGURATIONS

DIP, SOIC, AND SSOP

1

2

BUSY

3

SLEEP

/REF

4

OUT

DD

AD7858/

5

AD7858L

6

TOP VIEW

(Not to Scale)

7

8

9

10

11

12

AV

AGND

C

REF1

C

REF2

AIN1

AIN2 AIN7

AIN3

AIN4

REF

CONVST

IN

24

SYNC

23

SCLK

22

CLKIN

DIN

21

DOUT

20

19

DGND

18

DV

DD

17

CAL

AIN8

16

15

AIN6

14

AIN5

13

–6–

REV. B

AD7858/AD7858L

PIN FUNCTION DESCRIPTIONS

Pin Mnemonic Description

1 CONVST Convert Start. Logic Input. A low to high transition on this input puts the track/hold into its hold mode

and starts conversion. When this input is not used, it should be tied to DV

2 BUSY Busy Output. The busy output is triggered high by the falling edge of CONVST or rising edge of CAL,

and remains high until conversion is completed. BUSY is also used to indicate when the AD7858/
AD7858L has completed its on-chip calibration sequence.

3 SLEEP Sleep Input/Low-Power Mode. A Logic 0 initiates a sleep, and all circuitry is powered down including the

internal voltage reference provided there is no conversion or calibration being performed. Calibration
data is retained. A Logic 1 results in normal operation. See Power-Down section for more details.

4 REF

IN

/REF

OUT

Reference Input/Output. This pin is connected to the internal reference through a series resistor and is
the reference source for the analog-to-digital converter. The nominal reference voltage is 2.5 V and this
appears at the pin. This pin can be overdriven by an external reference or can be taken as high as AV

5AV

DD

When this pin is tied to AV
should also be tied to AV

Analog Positive Supply Voltage, +3.0 V to +5.5 V.

or when an externally applied reference approaches AVDD, the C

DD,

.

DD

6 AGND Analog Ground. Ground reference for track/hold, reference, and DAC.
7C

REF1

Reference Capacitor (0.1 µF Multilayer Ceramic). This external capacitor is used as a charge source for
the internal DAC. The capacitor should be tied between the pin and AGND.

8C

REF2

Reference Capacitor (0.01 µF Ceramic Disc). This external capacitor is used in conjunction with the on-
chip reference. The capacitor should be tied between the pin and AGND.

9–16 AIN1–AIN8 Analog Inputs. Eight analog inputs that can be used as eight single-ended inputs (referenced to AGND)

or four pseudo-differential inputs. Channel configuration is selected by writing to the control register.
Both the positive and negative inputs cannot go below AGND or above AV
tive input cannot go below the negative input. See Table III for channel selection.

17 CAL Calibration Input. This pin has an internal pull-up current source of 0.15 µA. A Logic 0 on this pin resets

all calibration control logic and initiates a calibration on its rising edge. There is the option of connecting
a 10 nF capacitor from this pin to DGND to allow for an automatic self-calibration on power-up. This
input overrides all other internal operations. If the autocalibration is not required, this pin should be tied
to a logic high.

18 DV

DD

Digital Supply Voltage, +3.0 V to +5.5 V.
19 DGND Digital Ground. Ground reference point for digital circuitry.
20 DOUT Serial Data Output. The data output is supplied to this pin as a 16-bit serial word.
21 DIN Serial Data Input. The data to be written is applied to this pin in serial form (16-bit word). This pin can

act as an input pin or as a I/O pin depending on the serial interface mode the part is in (see Table X).
22 CLKIN Master clock signal for the device (4 MHz AD7858, 1.8 MHz AD7858L). Sets the conversion and cali-

bration times.
23 SCLK Serial Port Clock. Logic Input. The user must provide a serial clock on this input.
24 SYNC Frame Sync. Logic Input. This pin is level triggered active low and frames the serial clock for the read

and write operations (see Table IX).

.

DD

REF1

at any time. Also the posi-

DD

DD

pin

.

REV. B

–7–

AD7858/AD7858L

TERMINOLOGY
Integral Nonlinearity

1

This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The end­points of the transfer function are zero scale, a point 1/2 LSB
below the first code transition, and full scale, a point 1/2 LSB
above the last code transition.

Differential Nonlinearity

This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.

Total Unadjusted Error

This is the deviation of the actual code from the ideal code tak­ing all errors into account (Gain, Offset, Integral Nonlinearity, and
other errors) at any point along the transfer function.

Unipolar Offset Error

This is the deviation of the first code transition (00 . . . 000 to
00 . . . 001) from the ideal AIN(+) voltage (AIN(–) + 1/2 LSB).

Positive Full-Scale Error

This is the deviation of the last code transition from the ideal
AIN(+) voltage (AIN(–) + Full Scale – 1.5 LSB) after the offset
error has been adjusted out.

Channel-to-Channel Isolation

Channel-to-channel isolation is a measure of crosstalk between
the channels. It is measured by applying a full-scale 25 kHz
signal to the other seven channels and determining how much
that signal is attenuated in the channel of interest. The figure
given is the worst case for all channels.

Track/Hold Acquisition Time

The track/hold amplifier returns into track mode and the end of
conversion. Track/hold acquisition time is the time required for
the output of the track/hold amplifier to reach its final value,
within ±1/2 LSB, after the end of conversion.

Signal to (Noise + Distortion) Ratio

This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the sum of all nonfundamental signals
up to half the sampling frequency (f

/2), excluding dc. The ratio

S

is dependent on the number of quantization levels in the digitiza­tion process; the more levels, the smaller the quantization noise.
The theoretical signal to (noise + distortion) ratio for an ideal
N-bit converter with a sine wave input is given by:

Signal to (Noise + Distortion) = (6.02 N +1.76) dB

Thus for a 12-bit converter, this is 74 dB.

1

AIN(+) refers to the positive input of the pseudo differential pair, and AIN(–)
refers to the negative analog input of the pseudo differential pair or to AGND
depending on the channel configuration.

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7858/AD7858L, it is
defined as:

2

2

2

2

2

+ V

)

5

6

THD dB

()

= 20 log

(V

+ V

+ V

2

3

+ V

4

V

1

where V1 is the rms amplitude of the fundamental and V2, V3,

, V5, and V6 are the rms amplitudes of the second through the

V

4

sixth harmonics.

Peak Harmonic or Spurious Noise

Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to f

/2 and excluding dc) to the rms value of the

S

fundamental. Normally, the value of this specification is deter­mined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor, it will be a
noise peak.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are
those for which neither m nor n are equal to zero. For example,
the second order terms include (fa + fb) and (fa – fb), while the
third order terms include (2fa + fb), (2fa – fb), (fa + 2fb), and
(fa – 2fb).

Testing is performed using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used. In
this case, the second order terms are usually distanced in fre­quency from the original sine waves, while the third order terms
are usually at a frequency close to the input frequencies. As a
result, the second and third order terms are specified separately.
The calculation of the intermodulation distortion is as per the
THD specification where it is the ratio of the rms sum of the
individual distortion products to the rms amplitude of the sum
of the fundamentals expressed in dBs.

–8–

REV. B

AD7858/AD7858L

ON-CHIP REGISTERS

The AD7858/AD7858L powers up with a set of default conditions. The only writing required is to select the channel configuration.
Without performing any other write operations the AD7858/AD7858L still retains the flexibility for performing a full power-down
and a full self-calibration.

Extra features and flexibility, such as performing different power-down options, different types of calibrations including system
calibration, and software conversion start, can be selected by further writing to the part.

The AD7858/AD7858L contains a Control Register, ADC Output Data Register, Status Register, Test Register, and
10 Calibration Registers. The control register is write-only, the ADC output data register and the status register are read-only, and
the test and calibration registers are both read/write registers. The Test Register is used for testing the part and should not be written to.

Addressing the On-Chip Registers

Writing

A write operation to the AD7858/AD7858L consists of 16 bits. The two MSBs, ADDR0 and ADDR1, are decoded to determine
which register is addressed, and the subsequent 14 bits of data are written to the addressed register. It is not until all 16 bits are
written that the data is latched into the addressed registers. Table I shows the decoding of the address bits while Figure 4 shows the
overall write register hierarchy.

Table I. Write Register Addressing

ADDR1 ADDR0 Comment

0 0 This combination does not address any register so the subsequent 14 data bits are ignored.
0 1 This combination addresses the TEST REGISTER. The subsequent 14 data bits are written to the test

register.

1 0 This combination addresses the CALIBRATION REGISTERS. The subsequent 14 data bits are written

to the selected calibration register.

1 1 This combination addresses the CONTROL REGISTER. The subsequent 14 data bits are written to the

control register.

Reading

To read from the various registers the user must first write to Bits 6 and 7 in the Control Register, RDSLT0 and RDSLT1. These
bits are decoded to determine which register is addressed during a read operation. Table II shows the decoding of the read address
bits while Figure 5 shows the overall read register hierarchy. The power-up status of these bits is 00 so that the default read will be
from the ADC output data register.

Once the read selection bits are set in the Control Register, all subsequent read operations that follow will be from the selected regis­ter until the read selection bits are changed in the Control Register.

Table II. Read Register Addressing

RDSLT1 RDSLT0 Comment

0 0 All successive read operations will be from ADC OUTPUT DATA REGISTER. This is the power-up

default setting. There will always be 4 leading zeros when reading from the ADC Output Data Register.
0 1 All successive read operations will be from TEST REGISTER.
1 0 All successive read operations will be from CALIBRATION REGISTERS.
1 1 All successive read operations will be from STATUS REGISTER.

RDSLT1, RDSLT0

DECODE

01 10 11

TEST

REGISTER

GAIN(1)

OFFSET(1)

DAC(8)

00 01 10 1 1

CALIBRATION

REGISTERS

GAIN(1)

OFFSET(1)

OFFSET(1) GAIN(1)

STATUS

REGISTER

CALSLT1, CALSLT0

DECODE

ADDR1, ADDR0

DECODE

01 10 11

TEST

REGISTER

GAIN(1)

OFFSET(1)

DAC(8)

00 01 10 11

CALIBRATION

REGISTERS

GAIN(1)

OFFSET(1)

OFFSET(1) GAIN(1)

CONTROL

REGISTER

00

ADC OUTPUT

DATA REGISTER

CALSLT1, CALSLT0

DECODE

Figure 4. Write Register Hierarchy/Address Decoding

REV. B

Figure 5. Read Register Hierarchy/Address Decoding

–9–

AD7858/AD7858L

CONTROL REGISTER

The arrangement of the Control Register is shown below. The control register is a write only register and contains 14 bits of data.
The control register is selected by putting two 1s in ADDR1 and ADDR0. The function of the bits in the control register are de­scribed below. The power-up status of all bits is 0.

MSB

SGL/DIFF CH2 CH1 CH0 PMGT1 PMGT0 RDSLT1

RDSLT0 2/3 MODE CONVST CALMD CALSLT1 CALSLT0 STCAL

LSB

CONTROL REGISTER BIT FUNCTION DESCRIPTION

Bit Mnemonic Comment

13 SGL/DIFF A 0 in this bit position configures the input channels in pseudo-differential mode. A 1 in this bit position

configures the input channels in single-ended mode (see Table III).

12 CH2 These three bits are used to select the channel on which the conversion is performed. The channels can
11 CH1 be configured as eight single-ended channels or four pseudo-differential channels. The default selection
10 CH0 is AIN1 for the positive input and AIN2 for the negative input (see Table III for channel selection).

9 PMGT1 Power Management Bits. These two bits are used with the SLEEP pin for putting the part into various
8 PMGT0 Power-Down Modes (see Power-Down section for more details).

7 RDSLT1 Theses two bits determine which register is addressed for the read operations (see Table II).
6 RDSLT0

52/3 MODE Interface Mode Select Bit. With this bit set to 0, Interface Mode 2 is enabled. With this bit set to 1,

Interface Mode 1 is enabled where DIN is used as an output as well as an input. This bit is set to 0 by
default after every read cycle; thus when using the Two-Wire Interface Mode, this bit needs to be set to
1 in every write cycle.

4 CONVST Conversion Start Bit. A logic one in this bit position starts a single conversion, and this bit is automati-

cally reset to 0 at the end of conversion. This bit may also be used in conjunction with system calibration

(see Calibration section.)
3 CALMD Calibration Mode Bit. A 0 here selects self-calibration, and a 1 selects a system calibration (see Table IV).
2 CALSLT1 Calibration Selection Bits and Start Calibration Bit. These bits have two functions.

1 CALSLT0 With the STCAL bit set to 1 the CALSLT1 and CALSLT0 bits determine the type of calibration per
0 STCAL formed by the part (see Table IV). The STCAL bit is automatically reset to 0 at the end of calibration.

With the STCAL bit set to 0 the CALSLT1 and CALSLT0 bits are decoded to address the calibration

register for read/write of calibration coefficients (see section on the Calibration Registers for more details).

–10–

REV. B