Analog Devices AD7856KR, AD7856ARS, AD7856AR, AD7856AN Datasheet

5 V Single Supply, 8-Channel

a

FEATURES
Single 5␣ V Supply
285 kSPS Throughput Rate
Self- and System Calibration with Autocalibration on

Power-Up
Eight Single-Ended or Four Pseudo-Differential Inputs
Low Power: 60 mW Typ
Automatic Power-Down After Conversion (2.5␣ ␮W Typ)
Flexible Serial Interface: 8051/SPI™/QSPI™/␮P Compatible
24-Lead DIP, SOIC and SSOP Packages

APPLICATIONS
Battery-Powered Systems (Personal Digital Assistants,

Medical Instruments, Mobile Communications)
Pen Computers
Instrumentation and Control Systems
High Speed Modems

GENERAL DESCRIPTION

The AD7856 is a high speed, low power, 14-bit ADC that oper­ates from a single 5 V power supply. The ADC powers up with
a set of default conditions at which time it can be operated as a
read only ADC. The ADC contains self-calibration and system
calibration options to ensure accurate operation over time and
temperature and it has a number of power-down options for low
power applications.

The AD7856 is capable of 285 kHz throughput rate. The input
track-and-hold acquires a signal in 500 ns and features a pseudo­differential sampling scheme. The AD7856 voltage range is 0 to
V

with straight binary output coding. Input signal range is to

REF

the supply and the part is capable of converting full power sig­nals to 10 MHz.

CMOS construction ensures low power dissipation of typically
60 mW for normal operation and 5.1 mW in power-down mode
at 10 kSPS throughput rate. The part is available in 24-lead,

0.3 inch-wide dual in-line package (DIP), 24-lead small outline
(SOIC) and 24-lead small shrink outline (SSOP) packages.
Please see page 31 for data sheet index.

14-Bit 285 kSPS Sampling ADC

AD7856

FUNCTIONAL BLOCK DIAGRAM

DD

AD7856

COMP

SAR + ADC

CONTROL

.

AGND

DD

.

DV

DD

DGND

CLKIN

CONVST

BUSY

SLEEP

AV

DD

REFIN/REF

C

C

AIN1
AIN8

REF1

REF2

CAL

OUT

.....

....

I/P

T/H

MUX

4.096V

REFERENCE

BUF

CHARGE

REDISTRIBUTION

DAC

CALIBRATION
MEMORY AND
CONTROLLER

SERIAL INTERFACE/CONTROL REGISTER

SYNC

DIN DOUT SCLK

PRODUCT HIGHLIGHTS

1. Single 5 V supply.

2. Automatic calibration on power-up.

3. Flexible power management options including automatic
power-down after conversion.

4. Operates with reference voltages from 1.2 V to V

5. Analog input range from 0 V to V

6. Eight single-ended or four pseudo-differential input channels.

7. Self- and system calibration.

8. Versatile serial I/O port (SPI/QSPI/8051/µP).

SPI and QSPI are trademarks of Motorola, Inc.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1998

AD7856–SPECIFICATIONS

REFIN/REF

= 4.096 V External Reference unless otherwise noted, SLEEP = Logic High; TA = T

OUT

1, 2

A Grade: f
f

= 4 MHz, (0ⴗC to +105ⴗC), f

CLKIN

= 6 MHz, (–40ⴗC to +105ⴗC), f

CLKIN

SAMPLE

to T

MIN

= 285 kHz; K Grade:

SAMPLE

= 102 kHz; (AVDD = DVDD = +5.0 V ⴞ 5%,

, unless otherwise noted.) Specifica-

MAX

tions apply for Mode 2 operation, standard 3-wire SPI interface; refer to Detailed Timing section for Mode 1 Specifications.

Parameter A Version1K Version1Units Test Conditions/Comments

DYNAMIC PERFORMANCE f

Signal to Noise + Distortion Ratio

3

(SNR) 78 78 dB min 79.5 dB typ
Total Harmonic Distortion (THD) –86 –86 dB max –95 dB typ
Peak Harmonic or Spurious Noise –87 –87 dB max –95 dB typ
Intermodulation Distortion (IMD)

Second Order Terms –86 –90 dB typ fa = 9.983 kHz, fb = 10.05 kHz
Third Order Terms –86 –90 dB typ fa = 9.983 kHz, fb = 10.05 kHz
Channel-to-Channel Isolation –90 –90 dB typ VIN = 25 kHz

DC ACCURACY Any Channel

Resolution 14 14 Bits

Integral Nonlinearity ±2 LSB max 4.096 V External Reference, V

±2 LSB typ

Differential Nonlinearity ±2 LSB max Guaranteed No Missed Codes to 13 Bits.

±2 LSB typ

Offset Error ±10 LSB max

±10 ±5 LSB typ
Offset Error Match ±3 LSB max
Positive Full-Scale Error ±10 LSB max

±10 LSB typ
Positive Full-Scale Error Match ±2 LSB max

ANALOG INPUT

Input Voltage Ranges 0 to V

REF

0 to V

REF

Volts i.e., AIN(+) – AIN(–) = 0 to V

Leakage Current ±1 ±1 µA max

Input Capacitance 20 20 pF typ

REFERENCE INPUT/OUTPUT

REF

Input Voltage Range 4.096/V

IN

DD

2.3/V

DD

V min/max Functional from 1.2 V

Input Impedance 150 150 kΩ typ Resistor Connected to Internal Reference Node

REF

Output Voltage 3.696/4.496 3.696/4.496 V min/max

OUT

REF

Tempco 20 20 ppm/°C typ

OUT

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance, C

IN

IN

INH

INL

4

VDD – 1.0 VDD – 1.0 V min

0.4 0.4 V max

±1 ±1 µA max Typically 10 nA, V

10 10 pF max

LOGIC OUTPUTS

Output High Voltage, V
Output Low Voltage, V

Floating-State Leakage Current ±1 ±1 µA max

Floating-State Output Capacitance

OH

OL

4

VDD – 0.4 VDD – 0.4 V min I

0.4 0.4 V max I

10 10 pF max
Output Coding Straight (Natural) Binary

CONVERSION RATE

Conversion Time 3.5 5.25 µs max 21 CLKIN Cycles
Track/Hold Acquisition Time 0.33 0.5 µs min

= 10 kHz

IN

= 5 V

DD

, AIN(–) Can Be

REF

Biased Up, but AIN(+) Cannot Go Below AIN(–)

= 0 V or V

SOURCE

= 0.8 mA

SINK

IN

= 200 µA

DD

–2–

REV. A

AD7856

Parameter A Version

1

K Version1Units Test Conditions/Comments

POWER PERFORMANCE

AV

DD, DVDD

I

DD

Normal Mode
Sleep Mode

5

6

+4.75/+5.25 +4.75/+5.25 V min/max

17 17 mA max AV

= DVDD = 4.75 V to 5.25 V. Typically 12 mA

DD

With External Clock On 30 10 µA typ Full Power-Down. Power Management Bits in Con-

trol Register Set as PMGT1 = 1, PMGT0 = 0

400 500 µA typ Partial Power-Down. Power Management Bits in

Control Register Set as PMGT1 = 1, PMGT0 = 1

With External Clock Off 5 5 µA max Typically 0.5 µA. Full Power-Down. Power Manage-

ment. Bits in Control Register Set as PMGT1 = 1,
PMGT0 = 0

200 200 µA typ Partial Power-Down. Power Management Bits in

Control Register Set as PMGT1 = 1, PMGT0 = 1

Normal Mode Power Dissipation 89.25 89.25 mW max V

= 5.25 V. Typically 60 mW; SLEEP = V

DD

DD

Sleep Mode Power Dissipation

With External Clock On 52.5 52.5 µW typ V

= 5.25 V. SLEEP = 0 V

DD

With External Clock Off 26.25 26.25 µW max VDD = 5.25 V. Typically 5.25 µW; SLEEP = 0 V

SYSTEM CALIBRATION

Offset Calibration Span
Gain Calibration Span

NOTES

1

Temperature ranges as follows: A Version: –40°C to +105°C. K Version: 0°C to +105°C.

2

Specifications apply after calibration.

3

SNR calculation includes distortion and noise components.

4

Sample tested @ +25°C to ensure compliance.

5

All digital inputs @ DGND except for CONVST, SLEEP, CAL and SYNC @ DVDD. No load on the digital outputs. Analog inputs @ AGND.

6

CLKIN @ DGND when external clock off. All digital inputs @ DGND except for CONVST, SLEEP, CAL, and SYNC @ DVDD. No load on the digital outputs.
Analog inputs @ AGND.

7

The Offset and Gain Calibration Spans are defined as the range of offset and gain errors that the AD7856 can calibrate. Note also that these are voltage spans and are
not absolute voltages (i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–) ±0.0375 × V
the allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted out will be V
This is explained in more detail in the Calibration section of the data sheet.

Specifications subject to change without notice.

7

7

+0.0375 × V
+1.01875 × V

/–0.0375 × V

REF

/–0.98125 × V

REF

V max/min Allowable Offset Voltage Span for Calibration

REF

V max/min Allowable Full-Scale Voltage Span for Calibration

REF

± 0.01875 × V

REF

REF

, and

REF

).

–3–REV. A

AD7856

TIMING SPECIFICATIONS

1

(VDD = 5 V; TA = T

MIN

to T

, unless otherwise noted. A Grade: f

MAX

= 6 MHz; K Grade: f

CLKIN

CLKIN

= 4 MHz.)

␣ ␣ ␣ Limit at T

MIN

, T

MAX

Parameter A Version K Version Units Description

f

CLKIN

2

500 500 kHz min Master Clock Frequency
6 4 MHz max

f

SCLK

3

t

1

t

2

t

CONVERT

t

3

4

t

4

4

t

5

4

t

6

t

7

t

8

t

9

t

10

t

11

5

t

12

t

13

6

t

14

t

15

t

16

t

CAL

t

CAL1

t

CAL2

NOTES

1

Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
See Table X and timing diagrams for different interface modes and calibration.

2

Mark/Space ratio for the master clock input is 40/60 to 60/40.

3

The CONVST pulsewidth here only applies for normal operation. When the part is in power-down mode, a different CONVST pulsewidth will apply
(see Power-Down section).

4

Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.

5

t12 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time, t12, quoted in the timing characteristics is the true bus
relinquish time of the part and is independent of the bus loading.

6

t14 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time, t
true delay of the part in turning off the output drivers and configuring the DIN line as an input. Once this time has elapsed the user can drive the DIN line
knowing that a bus conflict will not occur.

Specifications subject to change without notice.

6 4 MHz max
100 100 ns min CONVST Pulsewidth

50 50 ns max CONVST↓ to BUSY↑ Propagation Delay

3.5 5.25 µs max Conversion Time = 20 t

–0.4 t

±0.4 t

SCLK

SCLK

–0.4 t

±0.4 t

SCLK

SCLK

ns min SYNC↓ to SCLK↓ Setup Time (Noncontinuous SCLK Input)
ns min/max SYNC↓ to SCLK↓ Setup Time (Continuous SCLK Input)

CLKIN

30 50 ns max Delay from SYNC↓ Until DOUT 3-State Disabled
30 50 ns max Delay from SYNC↓ Until DIN 3-State Disabled
45 75 ns max Data Access Time After SCLK↓
30 40 ns min Data Setup Time Prior to SCLK↑

20 20 ns min Data Valid to SCLK Hold Time

0.4 t

0.4 t

SCLK

SCLK

0.4 t

0.4 t

SCLK

SCLK

ns min SCLK High Pulsewidth
ns min SCLK Low Pulsewidth

30 30 ns min SCLK↑ to SYNC↑ Hold Time (Noncontinuous SCLK)

30/0.4 t

SCLK

30/0.4 t

ns min/max (Continuous SCLK)

SCLK

50 50 ns max Delay from SYNC↑ Until DOUT 3-State Enabled
90 90 ns max Delay from SCLK↑ to DIN Being Configured as Output
50 50 ns max Delay from SCLK↑ to DIN Being Configured as Input

2.5 t

2.5 t

CLKIN

CLKIN

2.5 t

2.5 t

CLKIN

CLKIN

ns max CAL↑ to BUSY↑ Delay
ns max CONVST↓ to BUSY↑ Delay in Calibration Sequence

41.7 62.5 ms typ Full Self-Calibration Time, Master Clock Dependent
(250026 t

CLKIN

)

37.04 55.5 ms typ Internal DAC Plus System Full-Scale Cal Time, Master
Clock Dependent (222228 t

CLKIN

)

4.63 6.94 ms typ System Offset Calibration Time, Master Clock Dependent
(27798 t

CLKIN

)

) and timed from a voltage level of 1.6 V.

DD

, quoted in the Timing Characteristics is the

14

–4–

REV. A

AD7856

TYPICAL TIMING DIAGRAMS

Figures 2 and 3 show typical read and write timing diagrams for
serial Interface Mode 2. The reading and writing occurs after
conversion in Figure 2, and during conversion in Figure 3. To
attain the maximum sample rate of 285 kHz, reading and writ­ing must be performed during conversion as in Figure 3. At
least 330 ns acquisition time must be allowed (the time from
the falling edge of BUSY to the next rising edge of CONVST)
before the next conversion begins to ensure that the part is
settled to the 14-bit level. If the user does not want to provide
the CONVST signal, the conversion can be initiated in software
by writing to the control register.

t

= 3.5ms MAX, 5.25ms MAX FOR K VERSION

CONVERT

t

= 100ns MIN, t4 = 30/50ns MAX A/K, t7 = 30/40ns MIN A/K

t

CONVST (I/P)

BUSY (O/P)

SYNC (I/P)

SCLK (I/P)

DOUT (O/P) DB0

DIN (I/P)

1

t

2

1

t

CONVERT

t

4

THREE-STATE

t

3

DB15

1

t

DB15

t

7

I

1.6mA

OL

TO OUTPUT

PIN

C

L

100pF

I

200mA

OL

Figure 1. Load Circuit for Digital Output Timing
Specifications

t

DB0

11

t

12

THREE-

STATE

t

9

5

616

t

10

DB11

t

6

DB11

6

t

8

+2.1V

Figure 2. Timing Diagram for Interface Mode 2 (Reading/Writing After Conversion)

t

= 3.5ms MAX, 5.25ms MAX FOR K VERSION

CONVERT

t

= 100ns MIN,

t

CONVST (I/P)

BUSY (O/P)

SYNC (I/P)

SCLK (I/P)

DOUT (O/P) DB0

DIN (I/P)

1

t

2

1

t

4

THREE-STATE

t

3

DB15

t

4

1

DB15

t

7

= 30/50ns MAX A/K,

t

CONVERT

5

t

6

t

8

DB11

t

= 30/40ns MIN A/K

7

t

9

616

t

10

t

6

DB11

DB0

t

11

t

12

THREE-

STATE

Figure 3. Timing Diagram for Interface Mode 2 (Reading/Writing During Conversion)

–5–REV. A

AD7856

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

(T

= +25°C unless otherwise noted)

A

1

AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . ␣ –0.3 V to +7 V

to DGND . . . . . . . . . . . . . . . . . . . . . . .␣ –0.3 V to +7 V

DV

DD

AV

to DVDD␣ . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

DD

Analog Input Voltage to AGND . . . .␣ –0.3 V to AV

Digital Input Voltage to DGND . . . . –0.3 V to DV

Digital Output Voltage to DGND . . . –0.3 V to DV
REF

/REF

IN

Input Current to Any Pin Except Supplies

to AGND . . . . . . . . .␣ –0.3 V to AVDD + 0.3 V

OUT

2

␣ . . . . . . . ±10 mA

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

DD

Operating Temperature Range Commercial

A Version . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +105°C

K Version . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +105°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . 105°C/W

θ

JA

θ

Thermal Impedance . . . . . . . . . . . . . . . . . . . . 34.7°C/W

JC

Lead Temperature, (Soldering, 10 secs) . . . . . . . . .+260°C

SOIC, SSOP Package, Power Dissipation . . . . . . . . . 450 mW

Thermal Impedance . 75°C/W (SOIC) 115°C/W (SSOP)

θ

JA

Thermal Impedance . . 25°C/W (SOIC) 35°C/W (SSOP)

θ

JC

Lead Temperature, Soldering

Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . .+215°C

Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C

ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >1 kV

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi­tions for extended periods may affect device reliability.

2

Transient currents of up to 100 mA will not cause SCR latch-up.

ORDERING GUIDE

Linearity
Error Package

Model (LSB)

1

Options

2

AD7856AN ±2 typ N-24
AD7856AR ±2 typ R-24
AD7856KR ±2 R-24
AD7856ARS ±2 typ RS-24

EVAL-AD7856CB
EVAL-CONTROL BOARD

NOTES

1

Linearity error here refers to integral linearity error.

2

N = Plastic DIP; R = SOIC; RS = SSOP.

3

This can be used as a stand-alone evaluation board or in conjunction with the
EVAL-CONTROL BOARD for evaluation/demonstration purposes.

4

This board is a complete unit allowing a PC to control and communicate with
all Analog Devices evaluation boards ending in the CB designators.

3

4

PIN CONFIGURATIONS

(DIP, SOIC AND SSOP)

REF

CONVST

BUSY

SLEEP

/REF

IN

AGND
C

C

AV

REF1
REF2

AIN1
AIN2
AIN3
AIN4

OUT

DD

1
2
3
4
5

AD7856

6

TOP VIEW

(Not to Scale)

7
8

9
10
11
12

24
23

22
21

20
19
18
17
16
15
14
13

SYNC

SCLK
CLKIN
DIN
DOUT
DGND
DV

DD

CAL

AIN8
AIN7

AIN6
AIN5

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7856 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

–6–

REV. A

AD7856

PIN FUNCTION DESCRIPTIONS

Pin Mnemonic Description

1 CONVST Convert Start. Logic Input. A low to high transition on this input puts the track/hold into its hold mode

and starts conversion. When this input is not used, it should be tied to DVDD.

2 BUSY Busy Output. The busy output is triggered high by the falling edge of␣ CONVST or rising edge of CAL,

and remains high until conversion is completed. BUSY is also used to indicate when the AD7856 has
completed its on-chip calibration sequence.

3 SLEEP Sleep Input/Low Power Mode. A Logic 0 initiates a sleep, and all circuitry is powered down, including

the internal voltage reference, provided there is no conversion or calibration being performed. Calibration
data is retained. A Logic 1 results in normal operation. See Power-Down section for more details.

4 REF

5AV
6 AGND Analog Ground. Ground reference for track/hold, reference and DAC.
7C

8C

9–16 AIN1–AIN8 Analog Inputs. Eight analog inputs that can be used as eight single-ended inputs (referenced to AGND)

17 CAL Calibration Input. This pin has an internal pull-up current source of 0.15 µA. A falling edge on this pin

18 DV
19 DGND Digital Ground. Ground reference point for digital circuitry.
20 DOUT Serial Data Output. The data output is supplied to this pin as a 16-bit serial word.
21 DIN Serial Data Input. The data to be written is applied to this pin in serial form (16-bit word). This pin can

22 CLKIN Master clock signal for the device (A Grade: 6 MHz; K Grade: 4 MHz). Sets the conversion and calibra-

23 SCLK Serial Port Clock. Logic Input. The user must provide a serial clock on this input.
24 SYNC Frame Sync. Logic Input. This pin is level triggered active low and frames the serial clock for the read

DD

REF1

REF2

DD

IN

/REF

Reference Input/Output. This pin is connected to the internal reference through a series resistor and is

OUT

the reference source for the analog-to-digital converter. The nominal reference voltage is 4.096 V and
this appears at the pin. This pin can be overdriven by an external reference or can be taken as high as

. When this pin is tied to AV

AV

DD

C

pin should also be tied to AVDD.

REF1

or when an externally applied reference approaches AV

DD,

Analog Positive Supply Voltage, +5.0 V ± 5%.

Reference Capacitor (0.1 µF Multilayer Ceramic in parallel with a 470 nF NPO type). This external

capacitor is used as a charge source for the internal DAC. The capacitor should be tied between the pin
and AGND.

Reference Capacitor (0.01 µF Multilayer Ceramic). This external capacitor is used in conjunction with

the on-chip reference. The capacitor should be tied between the pin and AGND.

or four pseudo-differential inputs. Channel configuration is selected by writing to the control register.
Both the positive and negative inputs cannot go below AGND or above AV

at any time. Also the posi-

DD

tive input cannot go below the negative input. See Table III for channel selection.

resets all calibration control logic and initiates a calibration on its rising edge. There is the option of
connecting a 10 nF capacitor from this pin to DGND to allow for an automatic self-calibration on
power-up. This input overrides all other internal operations. If the autocalibration is not required, this
pin should be tied to a logic high.

Digital Supply Voltage, +5.0 V ± 5%.

act as an input pin or as a I/O pin depending on the serial interface mode the part is in (see Table X).

tion times.

and write operations (see Table IX).

DD,

the

–7–REV. A

AD7856

TERMINOLOGY

1

Integral Nonlinearity

This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The end­points of the transfer function are zero scale, a point 1/2 LSB
below the first code transition, and full scale, a point 1/2 LSB
above the last code transition.

Differential Nonlinearity

This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.

Total Unadjusted Error

This is the deviation of the actual code from the ideal code
taking all errors into account (Gain, Offset, Integral Nonlinearity
and other errors) at any point along the transfer function.

Unipolar Offset Error

This is the deviation of the first code transition (00␣ .␣ .␣ .␣ 000 to
00␣ .␣ .␣ .␣ 001) from the ideal AIN(+) voltage (AIN(–) + 1/2 LSB).

Positive Full-Scale Error

This is the deviation of the last code transition from the ideal
AIN(+) voltage (AIN(–) + Full Scale – 1.5 LSB) after the offset
error has been adjusted out.

Channel-to-Channel Isolation

Channel-to-channel isolation is a measure of crosstalk between
the channels. It is measured by applying a full-scale 25 kHz
signal to the other seven channels and determining how much
that signal is attenuated in the channel of interest. The figure
given is the worst case for all channels.

Track/Hold Acquisition Time

The track/hold amplifier returns into track mode and the end of
conversion. Track/Hold acquisition time is the time required for
the output of the track/hold amplifier to reach its final value,

within ±1/2 LSB, after the end of conversion.

Signal to (Noise + Distortion) Ratio

This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the sum of all nonfundamental signals
up to half the sampling frequency (f

/2), excluding dc. The ratio

S

is dependent on the number of quantization levels in the digiti­zation process; the more levels, the smaller the quantization
noise. The theoretical signal to (noise + distortion) ratio for an
ideal N-bit converter with a sine wave input is given by:

Signal to (Noise + Distortion) = (6.02 N + 1.76) dB

Thus for a 14-bit converter, this is 86 dB.

Total Harmonic Distortion

Total Harmonic Distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7856, it is defined as:

2

2

2

2

2

+V

5

6

THD (dB) = 20 log

V

+V

+V

2

3

+V

4

V

1

where V1 is the rms amplitude of the fundamental and V2, V3,

, V5 and V6 are the rms amplitudes of the second through the

V

4

sixth harmonics.

Peak Harmonic or Spurious Noise

Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to f

/2 and excluding dc) to the rms value of the

S

fundamental. Normally, the value of this specification is deter­mined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor, it will be a
noise peak.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion

products at sum and difference frequencies of mfa ± nfb where

m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are
those for which neither m nor n are equal to zero. For example,
the second order terms include (fa + fb) and (fa – fb), while the
third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and
(fa – 2fb).

Testing is performed using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used. In
this case, the second order terms are usually distanced in fre­quency from the original sine waves, while the third order terms
are usually at a frequency close to the input frequencies. As a
result, the second and third order terms are specified separately.
The calculation of the intermodulation distortion is as per the
THD specification where it is the ratio of the rms sum of the
individual distortion products to the rms amplitude of the sum
of the fundamentals expressed in dBs.

Full Power Bandwidth

The Full Power Bandwidth (FPBW) of the AD7856 is that
frequency at which the amplitude of the reconstructed (using
FFTs) fundamental (neglecting harmonics and SNR) is reduced
by 3 dB for a full-scale input.

NOTE

1

AIN(+) refers to the positive input of the pseudo-differential pair, and AIN(–)
refers to the negative analog input of the pseudo-differential pair or to AGND
depending on the channel configuration.

–8–

REV. A

AD7856

ON-CHIP REGISTERS

The AD7856 powers up with a set of default conditions. The only writing that is required is to select the channel configuration.
Without performing any other write operations the AD7856 still retains the flexibility for performing a full power-down, and a full
self-calibration.

Extra features and flexibility such as performing different power-down options, different types of calibrations including system cali­bration, and software conversion start can be selected by further writing to the part.

The AD7856 contains a Control Register, ADC Output Data Register, Status Register, Test Register and ten Calibration
Registers. The control register is write only, the ADC output data register and the status register are read only, and the test and
calibration registers are both read/write registers. The Test Register is used for testing the part and should not be written to.

Addressing the On-Chip Registers

Writing

A write operation to the AD7856 consists of 16 bits. The two MSBs, ADDR0 and ADDR1, are decoded to determine which register
is addressed, and the subsequent 14 bits of data are written to the addressed register. It is not until all 16 bits are written that the
data is latched into the addressed registers. Table I shows the decoding of the address bits while Figure 4 shows the overall write
register hierarchy.

Table I. Write Register Addressing

ADDR1 ADDR0 Comment

0 0 This combination does not address any register so the subsequent 14 data bits are ignored.
0 1 This combination addresses the TEST REGISTER. The subsequent 14 data bits are written to the

test register.

1 0 This combination addresses the CALIBRATION REGISTERS. The subsequent 14 data bits are

written to the selected calibration register.

1 1 This combination addresses the CONTROL REGISTER. The subsequent 14 data bits are written

to the control register.

Reading

To read from the various registers the user must first write to Bits 6 and 7 in the Control Register, RDSLT0 and RDSLT1. These
bits are decoded to determine which register is addressed during a read operation. Table II shows the decoding of the read address
bits while Figure 5 shows the overall read register hierarchy. The power-up status of these bits is 00 so that the default read will be
from the ADC output data register.

Once the read selection bits are set in the Control Register, all subsequent read operations that follow will be from the selected regis­ter until the read selection bits are changed in the Control Register.

Table II. Read Register Addressing

RDSLT1 RDSLT0 Comment

0 0 All successive read operations will be from ADC OUTPUT DATA REGISTER. This is the power-

up default setting. There will always be two leading zeros when reading from the ADC Output Data

Register.
0 1 All successive read operations will be from TEST REGISTER.
1 0 All successive read operations will be from CALIBRATION REGISTERS.
1 1 All successive read operations will be from STATUS REGISTER.

ADDR1, ADDR0

DECODE

01 10 11

TEST

REGISTER

CALIBRATION

REGISTERS

CONTROL
REGISTER

00

ADC OUTPUT

DATA REGISTER

RDSLT1, RDSLT0

DECODE

01 10 11

TEST

REGISTER

CALIBRATION

REGISTERS

STATUS

REGISTER

CALSLT1, CALSLT0

DECODE

GAIN(1)

OFFSET(1)

DAC(8)

00 01 10 11

GAIN(1)

OFFSET(1)

OFFSET(1) GAIN(1)

Figure 4. Write Register Hierarchy/Address Decoding

CALSLT1, CALSLT0

DECODE

GAIN(1)

OFFSET(1)

DAC(8)

00 01 10 11

GAIN(1)

OFFSET(1)

OFFSET(1)

Figure 5. Read Register Hierarchy/Address Decoding

–9–REV. A

GAIN(1)

AD7856

CONTROL REGISTER

The arrangement of the Control Register is shown below. The control register is a write only register and contains 14 bits of data.
The control register is selected by putting two 1s in ADDR1 and ADDR0. The function of the bits in the control register are de­scribed below. The power-up status of all bits is 0.

MSB

SGL/DIFF CH2 CH1 CH0 PMGT1 PMGT0 RDSLT1

RDSLT0 2/3 MODE CONVST CALMD CALSLT1 CALSLT0 STCAL

LSB

CONTROL REGISTER BIT FUNCTION DESCRIPTION

Bit Mnemonic Comment

13 SGL/DIFF A 0 in this bit position configures the input channels in pseudo-differential mode. A 1 in this bit position

configures the input channels in single-ended mode (see Table III).

12 CH2 These three bits are used to select the channel on which the conversion is performed. The channels can
11 CH1 be configured as eight single-ended channels or four pseudo-differential channels. The default selection
10 CH0 is AIN1 for the positive input and AIN2 for the negative input (see Table III for channel selection).

9 PMGT1 Power Management Bits. These two bits are used with the SLEEP pin for putting the part into various
8 PMGT0 power-down modes (see Power-Down section for more details).

7 RDSLT1 These two bits determine which register is addressed for the read operations (see Table II).
6 RDSLT0
52/3 MODE Interface Mode Select Bit. With this bit set to 0, Interface Mode 2 is enabled. With this bit set to 1,

Interface Mode 1 is enabled where DIN is used as an output as well as an input. This bit is set to 0 by
default after every read cycle; thus when using the Two-Wire Interface Mode, this bit needs to be set to
1 in every write cycle.

4 CONVST Conversion Start Bit. A logic one in this bit position starts a single conversion, and this bit is automatically

reset to 0 at the end of conversion. This bit may also used in conjunction with system calibration (see

Calibration section.)
3 CALMD Calibration Mode Bit. A 0 here selects self-calibration, and a 1 selects a system calibration (see Table IV).
2 CALSLT1 Calibration Selection Bits and Start Calibration Bit. These bits have two functions.

1 CALSLT0 With the STCAL bit set to 1 the CALSLT1 and CALSLT0 bits determine the type of calibration per­0 STCAL formed by the part (see Table IV). The STCAL bit is automatically reset to 0 at the end of calibration.

With the STCAL bit set to 0 the CALSLT1 and CALSLT0 bits are decoded to address the calibration

register for read/write of calibration coefficients (see section on the Calibration Registers for more details).

–10–

REV. A