Analog Devices AD7851CB, AD7851KR, AD7851KN, AD7851ARS, AD7851AR Datasheet

AIN(+)

AIN(–)

C

REF1

C

REF2

CAL

AV

DD

AGND

AGND

DV

DD

DGND

AMODE

CLKIN

SLEEP

CONVST

BUSY

SYNC

SM1 SM2 DIN DOUT SCLK

POLARITY

CHARGE

REDISTRIBUTION

DAC

COMP

4.096 V

REFERENCE

AD7851

BUF

T/H

SAR + ADC

CONTROL

CALIBRATION

MEMORY

AND CONTROLLER

SERIAL INTERFACE / CONTROL REGISTER

REFIN/

REF

OUT

14-Bit 333 kSPS

a

FEATURES
Single 5 V Supply
333 kSPS Throughput Rate/62 LSB DNL—A Grade
285 kSPS Throughput Rate/61 LSB DNL—K Grade
A & K Grades Guaranteed to 1258C/238 kSPS

Throughput Rate
Pseudo-Differential Input with Two Input Ranges
System and Self-Calibration with Autocalibration on

Power-Up
Read/Write Capability of Calibration Data
Low Power: 60 mW typ
Power-Down Mode: 5 mW typ Power Consumption
Flexible Serial Interface:

8051/SPI/QSPI/ mP Compatible
24-Pin DIP, SOIC and SSOP Packages

APPLICATIONS
Digital Signal Processing
Speech Recognition and Synthesis
Spectrum Analysis
DSP Servo Control
Instrumentation and Control Systems
High Speed Modems
Automotive

Serial A/D Converter

AD7851

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

The AD7851 is a high speed, 14-bit ADC that operates from a
single 5 V power supply. The ADC powers-up with a set of
default conditions at which time it can be operated as a read­only ADC. The ADC contains self-calibration and system­calibration options to ensure accurate operation over time and
temperature and has a number of power-down options for low
power applications.

The AD7851 is capable of 333 kHz throughput rate. The input
track-and-hold acquires a signal in 0.33 µs and features a
pseudo-differential sampling scheme. The AD7851 has the
added advantage of two input voltage ranges (0 V to V

/2 to +V

REF

DD

–V
is to V
to 20 MHz.

CMOS construction ensures low power dissipation (60 mW typ)
with power-down mode (5 µW typ). The part is available in 24-

/2 centered about V

REF

and the part is capable of converting full-power signals

/2). Input signal range

REF

REF,

and

pin, 0.3 inch-wide dual-in-line package (DIP), 24-lead small
outline (SOIC) and 24-lead small shrink outline (SSOP) packages.

*Patent pending.

See Page 35 for data sheet index.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

PRODUCT HIGHLIGHTS

1. Single 5 V supply.

2. Operates with reference voltages from 4 V to V

3. Analog input ranges from 0 V to V

DD

.

DD

.

4. System and self-calibration including power-down mode.

5. Versatile serial I/O port.

© Analog Devices, Inc., 1996

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] Fax: [phone]

AD7851–SPECIFICA TIONS

238 kHz; (AVDD = DVDD = +5.0 V 6 5%, REFIN/REF

Parameter A

= 4.096 V External Reference; SLEEP = Logic High; TA = T

OUT

1

1, 2

K

A Grade: f
(08C to +858C), f

1

= 7 MHz (–408C to +858C), f

CLKIN

= 285 kHz; A and K Grade: f

SAMPLE

= 333 kHz; K Grade: f

SAMPLE

CLKIN

to T

MIN

Units Test Conditions/Comments

CLKIN

= 5 MHz (to +1258C), f

, unless otherwise noted)

MAX

= 6 MHz

SAMPLE

DYNAMIC PERFORMANCE

Signal-to-Noise + Distortion Ratio3 (SNR) 77 78 dB mi n Typically SNR is 79.5 dB

V

Total Harmonic Distortion (THD) –86 –86 dB max V

= 10 kHz, Sine Wave, f

IN

= 10 kHz, Sine Wave, f

IN

SAMPLE
SAMPLE

= 333 kHz
= 333 kHz,

Typically –96 dB

Peak Harmonic or Spurious Noise –87 –87 dB max V

= 10 kHz, f

IN

SAMPLE

= 333 kHz

Intermodulation Distortion (IMD)

Second Order Terms –86 –90 dB typ fa = 9.983 kHz, fb = 10.05 kHz, f
Third Order Terms –86 –90 dB typ fa = 9.983 kHz, fb = 10.05 kHz, f

SAMPLE
SAMPLE

= 333 kHz
= 333 kHz

Full Power Bandwidth 20 20 MHz typ @ 3 dB
DC ACCURACY

Resolution 14 14 Bits
Integral Nonlinearity ±2 ±1 LSB max
Differential Nonlinearity ±2 ±1 LSB max Guaranteed No Missed Codes to 14 Bits
Unipolar Offset Error ±10 ±10 LSB max Review: “Adjusting the Offset Calibration
Positive Full-Scale Error ±10 ±10 LSB max Register” in the “Calibration Registers” section
Negative Full-Scale Error ±10 ±10 LSB typ of the data sheet.
Bipolar Zero Error ±1 ±1 LSB typ

ANALOG INPUT

Input Voltage Ranges 0 V to V

REF

0 V to V

Volts i.e., AIN(+) – AIN(–) = 0 V to V

REF

, AIN(–) can be

REF

biased up but AIN(+) cannot go below AIN(–).

±V

/2 ±V

REF

/2 Volts i.e., AIN(+) – AIN(–) = –V

REF

/2 to +V

REF

/2, AIN(–)

REF

should be biased up and AIN(+) can go below

AIN(–) but cannot go below 0 V.
Leakage Current ±1 ±1 µA max
Input Capacitance 20 20 pF typ

=

REFERENCE INPUT/OUTPUT

REFIN Input Voltage Range 4/V

DD

4/V

DD

V min/max Functional from 1.2 V
Input Impedance 150 150 kΩ typ Resistor Connected to Internal Reference Node
REF
REF

Output Voltage 3.696/4.496 3.696/4.496 V min/max

OUT

Tempco 50 50 ppm/°C typ

OUT

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance, C

INL

IN

IN

INH

5

VDD – 1.0 VDD – 1.0 V min

0.4 0.4 V max
±10 ±10 µA max V
10 10 pF max

= 0 V or V

IN

DD

LOGIC OUTPUTS

Output High Voltage, V
Output Low Voltage, V
Floating-State Leakage Current ±10 ±10 µA max
Floating-State Output Capacitance

OH

OL

5

VDD – 0.4 VDD – 0.4 V min I

0.4 0.4 V max I
10 10 pF max

SOURCE

= 0.8 mA

SINK

= 200 µA

Output Coding Straight (Natural) Binary Unipolar Input Range

2s Complement Bipolar Input Range

CONVERSION RATE

Conversion Time 2.78 3.25 µs max 19.5 CLKIN Cycles
Conversion + T/H Acquisition Time 3.0 3.5 µs max 21 CLKIN Cycles Throughput Rate

–2–

REV. A

AD7851

Parameter A

1

1

K

Units Test Conditions/Comments

POWER PERFORMANCE

AV

DD, DVDD

I

DD

Normal Mode
Sleep Mode

5

6

+4.75/+5.25 +4.75/+5.25 V min/max
17 17 mA max AV

12 mA.

= DVDD = 4.75 V to 5.25 V. Typically

DD

With External Clock On 20 20 µA typ Full Power-Down. Power management bits

in control register set as PMGT1 = 1, PMGT0 = 0.

600 600 µA typ Partial Power-Down. Power management bits in

control register set as PMGT1 = 1, PMGT0 = 1.

With External Clock Off 10 10 µA max Typically 1 µA. Full Power-Down. Power

management bits in control register set as
PMGT1 = 1, PMGT0 = 0.

300 300 µA typ Partial Power-Down. Power management bits in

control register set as PMGT1 = 1, PMGT0 = 1.

Normal Mode Power Dissipation 89.25 89.25 mW max V

= 5.25 V: Typically 63 mW; SLEEP = VDD.

DD

Sleep Mode Power Dissipation

With External Clock On 105 105 µW typ VDD = 5.25 V; SLEEP = 0 V
With External Clock Off 52.5 52.5 µW max VDD = 5.25 V; Typically 5.25 µW; SLEEP = 0 V

SYSTEM CALIBRATION

Offset Calibration Span
Gain Calibration Span

NOTES

1

Temperature ranges as follows: A Version, –40°C to +125°C; K Version, 0°C to +125°C.

2

Specifications apply after calibration.

3

SNR calculation includes distortion and noise components.

4

Sample tested @ +25°C to ensure compliance.

5

All digital inputs @ DGND except for CONVST, SLEEP , CAL, and SYNC @ DVDD. No load on the digital outputs. Analog inputs @ AGND.

6

CLKIN @ DGND when external clock off. All digital inputs @ DGND except for CONVST, SLEEP, CAL, and SYNC @ DVDD. No load on the digital outputs.
Analog inputs @ AGND.

7

The offset and gain calibration spans are defined as the range of offset and gain errors that the AD7851 can calibrate. Note also that these are voltage spans and are
not absolute voltages (i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–) ± 0.05 × V
allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted out will be V
explained in more detail in the calibration section of the data sheet.

Specifications subject to change without notice.

7

7

+0.05 × V
+1.025 × V

/–0.05 × V

REF

/–0.975 × V

REF

REF

V max/min Allowable Offset Voltage Span for Calibration
V max/min Allowable Full-Scale Voltage Span for Calibratio

REF

± 0.025 × V

REF

REF

). This is

REF

n

, and the

REV. A

–3–

AD7851

1

(AV

TIMING SPECIFICATIONS

Limit at T

MIN

, T

= DVDD = +5.0 V 6 5%; f

DD

MAX

Parameter A, K Units Description

2

f

CLKIN

3

f

SCLK

4

t

1

t

2

t

CONVERT

t

3

t

4

5

t

5

5

t

5A

5

t

6

t

7

t

8

6

t

9

6

t

10

t

11

t

11A

7

t

12

t

13

8

t

14

t

15

t

16

9

t

CAL

9

t

CAL1

9

t

CAL2

t

DELAY

NOTES
Descriptions that refer to SCLK↑ (rising) or SCLK↓ (falling) edges here are with the POLARITY pin HIGH. For the POLARITY pin LOW then the opposite edge of

SCLK will apply.

1

Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. See

Table X and timing diagrams for different interface modes and calibration.

2

Mark/Space ratio for the master clock input is 40/60 to 60/40.

3

For Interface Modes 1, 2, 3 the SCLK max frequency will be 10 MHz. For Interface Modes 4 and 5 the SCLK will be an output and the frequency will be f

4

The CONVST pulse width will here only apply for normal operation. When the part is in power-down mode, a different CONVST pulse width will apply (see Power-

Down section).

5

Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.

6

For self-clocking mode (Interface Modes 4, 5) the nominal SCLK high and low times will be 0.5 t

7

t12 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated

back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t12, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.

8

t14 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated

back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics is the true delay of the part in
turning off the output drivers and configuring the DIN line as an input. Once this time has elapsed the user can drive the DIN line knowing that a bus conflict will
not occur.

9

The typical time specified for the calibration times is for a master clock of 6 MHz.

Specifications subject to change without notice.

500 kHz min Master Clock Frequency
7 MHz max
10 MHz max Interface Modes 1, 2, 3 (External Serial Clock)
f

CLK IN

MHz max Interface Modes 4, 5 (Internal Serial Clock)
100 ns min CONVST Pulse Width
50 ns max CONVST↓ to BUSY↑ Propagation Delay

3.25 µs max Conversion Time = 20 t
–0.4 t
±0.4 t

0.6 t

SCLK

SCLK

SCLK

ns min SYNC↓ to SCLK↓ Setup Time (Noncontinuous SCLK Input)

ns min/max SYNC↓ to SCLK↓ Setup Time (Continuous SCLK Input)

ns min SYNC↓ to SCLK↓ Setup Time. Interface Mode 4 Only
30 ns max Delay from SYNC↓ until DOUT 3-State Disabled
30 ns max Delay from SYNC↓ until DIN 3-State Disabled
45 ns max Data Access Time After SCLK↓
30 ns min Data Setup Time Prior to SCLK↑
20 ns min Data Valid to SCLK Hold Time

0.4 t

0.4 t

SCLK
SCLK

ns min SCLK High Pulse Width (Interface Modes 4 and 5)

ns min SCLK Low Pulse Width (Interface Modes 4 and 5)
30 ns min SCLK↑ to SYNC↑ Hold Time (Noncontinuous SCLK)
30/0.4 t

SCLK

ns min/max (Continuous SCLK) Does Not Apply to Interface Mode 3
50 ns max SCLK↑ to SYNC↑ Hold Time
50 ns max Delay from SYNC↑ until DOUT 3-State Enabled
90 ns max Delay from SCLK↑ to DIN Being Configured as Output
50 ns max Delay from SCLK↑ to DIN Being Configured as Input

2.5 t

2.5 t

CLKIN
CLKIN

ns max CAL↑ to BUSY↑ Delay

ns max CONVST↓ to BUSY↑ Delay in Calibration Sequence

41.7 ms typ Full Self-Calibration Time, Master Clock Dependent (250026

37.04 ms typ Internal DAC Plus System Full-Scale Cal Time, Master Clock

4.63 ms typ System Offset Calibration Time, Master Clock Dependent
65 ns max Delay from CLK to SCLK

= 6 MHz, TA = T

CLKIN

t

CLKIN

)

MIN

Dependent (222228 t
(27798 t

CLKIN

SCLK

)

= 0.5 t

CLKIN

to T

, unless otherwise noted)

MAX

CLKIN

)

CLKIN

.

CLKIN

.

–4–

REV. A

AD7851

TYPICAL TIMING DIAGRAMS

Figures 2 and 3 show typical read and write timing diagrams.
Figure 2 shows the reading and writing after conversion in In­terface Modes 2 and 3. To attain the maximum sample rate of
285 kHz in Interface Modes 2 and 3, reading and writing must
be performed during conversion. Figure 3 shows the timing dia­gram for Interface Modes 4 and 5 with sample rate of 285 kHz.
At least 330 ns acquisition time must be allowed (the time from
the falling edge of BUSY to the next rising edge of

CONVST)
before the next conversion begins to ensure that the part is
settled to the 14-bit level. If the user does not want to provide
the

CONVST signal, the conversion can be initiated in software

by writing to the control register.

t

= 3.25µs MAX, t1 = 100ns MIN,

CONVERT

= 30ns MAX, t7 = 30ns MIN

t

5

15

t

6

DB15

t

7

DB15 DB0

CONVST (I/P)

BUSY (O/P)

SYNC (I/P)

SCLK (I/P)

DOUT (O/P)

DIN (I/P)

POLARITY PIN LOGIC HIGH

t

1

t

2

t

CONVERT

3-STATE

t

3

t

5

I

TO

OUTPUT

PIN

50pF

1.6mA

C

L

200µA

OL

I

OH

Figure 1. Load Circuit for Digital Output Timing
Specifications

t

9

6

t

10

t

6

t

8

DB11

t

11

16

t

12

DB0DB11

3-STATE

+2.1V

Figure 2. AD7851 Timing Diagram (Typical Read and Write Operation for Interface Modes 2, 3)

t

= 3.25µs MAX, t1 = 100ns MIN,

CONVERT

= 30ns MAX, t7 = 30ns MIN

t

5

t

CONVERT

t

9

t

6

DB11

t

11

6

t

10

16

DB0DB11

t

12

3-STATE

CONVST (I/P)

BUSY (O/P)

SYNC (O/P)

SCLK (O/P)

DOUT (O/P)

DIN (I/P)

POLARITY PIN LOGIC HIGH

t

1

t

2

t

5

3-STATE

t

7

DB15 DB0

t

4

15

DB15

t

8

Figure 3. AD7851 Timing Diagram (Typical Read and Write Operation for Interface Modes 4, 5)

REV. A

–5–

AD7851

ABSOLUTE MAXIMUM RATINGS

1

(TA = +25°C unless otherwise noted)

AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DV

to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DD

AV

to DVDD . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

DD

Analog Input Voltage to AGND . . . . –0.3 V to AV

Digital Input Voltage to DGND . . . . –0.3 V to DV

Digital Output Voltage to DGND . . . –0.3 V to DV
REF

/REF

IN

Input Current to Any Pin Except Supplies

to AGND . . . . . . . . . –0.3 V to AVDD + 0.3 V

OUT

2

. . . . . . . . ±10 mA

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

DD

Operating Temperature Range

Commercial (A, K Versions) . . . . . . . . . . –40°C to +125°C

Storage Temperature Range . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW

θ

Thermal Impedance . . . . . . . . . . . . . . . . . . . . 105°C/W

JA

θ

Thermal Impedance . . . . . . . . . . . . . . . . . . . . 34.7°C/W

JC

Lead Temperature, (Soldering, 10 secs) . . . . . . . . . . +260°C

SOIC, SSOP Package, Power Dissipation . . . . . . . . . 450 mW

θ

Thermal Impedance . . . 75°C/W (SOIC) 115°C/W (SSOP)

JA

θ

Thermal Impedance . . . . 25°C/W (SOIC) 35°C/W (SSOP)

JC

Lead Temperature, Soldering

Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >1.5 kV

NOTES

1

Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

2

Transient currents of up to 100 mA will not cause SCR latch-up.

PINOUT FOR DIP, SOIC AND SSOP

24
23
22
21
20
19
18
17
16
15
14
13

SYNC

SCLK
CLKIN
DIN
DOUT
DGND
DV

DD

CAL

SM2
SM1
POLARITY
AMODE

REF

CONVST

BUSY

SLEEP

/REF

IN

AGND
C
C
AIN(+)
AIN(–)

AGND

AV

REF
REF

OUT

DD

NC

1
2

10
11
12

1
2
3
4
5

AD7851

TOP VIEW

6

(Not to Scale)

7
8
9

ORDERING GUIDE

1

Linearity

Temp Error Throughput Throughput Package

Model Range (LSB)

2

Rate @ +1258C Options

3

AD7851AN –40°C to +85°C ±2 333 kSPS 238 kSPS N-24
AD7851KN 0°C to +85°C ±1 285 kSPS 238 kSPS N-24
AD7851AR –40°C to +85°C ±2 333 kSPS 238 kSPS R-24
AD7851KR 0°C to +85°C ±1 285 kSPS 238 kSPS R-24
AD7851ARS –40 °C to +85°C ±2 333 kSPS 238 kSPS RS-24
EVAL-AD7851CB
EVAL-CONTROL BOARD

NOTES

1

Both A and K Grades are guaranteed up to 125°C, but at a lower throughput of 238 kHz (5 MHz).

2

Linearity error refers to the integral linearity error.

3

N = Plastic DIP; R = SOIC; RS = SSOP.

4

This can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL BOARD for evaluation/demonstration

purposes.

5

This board is a complete unit allowing a PC to control and communicate with all Analog Devices, Inc. evaluation boards ending in the

CB designators.

4

5

.

–6–

REV. A

AD7851

TERMINOLOGY

Integral Nonlinearity

This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The end­points of the transfer function are zero scale, a point 1/2 LSB
below the first code transition, and full scale, a point 1/2 LSB
above the last code transition.

Differential Nonlinearity

This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.

Total Unadjusted Error

This is the deviation of the actual code from the ideal code tak­ing all errors into account (Gain, Offset, Integral Nonlinearity,
and other errors) at any point along the transfer function.

Unipolar Offset Error

This is the deviation of the first code transition (00 . . . 000 to
00 . . . 001) from the ideal AIN(+) voltage (AIN(–) + 1/2 LSB)
when operating in the unipolar mode.

Positive Full-Scale Error

This applies to the unipolar and bipolar modes and is the devia­tion of the last code transition from the ideal AIN(+) voltage
(AIN(–) + Full Scale – 1.5 LSB) after the offset error has been
adjusted out.

Negative Full-Scale Error

This applies to the bipolar mode only and is the deviation of the
first code transition (00 . . . 000 to 00 . . . 001) from the ideal
AIN(+) voltage (AIN(–) – V

/2 + 0.5 LSB).

REF

Bipolar Zero Error

This is the deviation of the midscale transition (all 0s to all 1s)
from the ideal AIN(+) voltage (AIN(–) – 1/2 LSB).

Track/Hold Acquisition Time

The track/hold amplifier returns into track mode and the end of
conversion. Track/Hold acquisition time is the time required for
the output of the track/hold amplifier to reach its final value,
within ±1/2 LSB, after the end of conversion.

Signal to (Noise + Distortion) Ratio

This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the sum of all nonfundamental sig­nals up to half the sampling frequency (f

/2), excluding dc. The

S

ratio is dependent on the number of quantization levels in the
digitization process; the more levels, the smaller the quantiza­tion noise. The theoretical signal to (noise + distortion) ratio for
an ideal N-bit converter with a sine wave input is given by:

Signal to (Noise + Distortion) = (6.02 N +1.76)dB

Thus for a 14-bit converter, this is 86 dB.

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7851, it is defined as:

2

2

2

2

2



+V

5

6



THD(dB) =20log



+V

+V

V

2



3

+V

4

V

1

where V1 is the rms amplitude of the fundamental and V2, V3,
V

, V5 and V6 are the rms amplitudes of the second through the

4

sixth harmonics.

Peak Harmonic or Spurious Noise

Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to f

/2 and excluding dc) to the rms value of the

S

fundamental. Normally, the value of this specification is deter­mined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor, it will be a
noise peak.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are
those for which neither m nor n are equal to zero. For example,
the second order terms include (fa + fb) and (fa – fb), while the
third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and
(fa – 2fb).

Testing is performed using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used. In
this case, the second order terms are usually distanced in fre­quency from the original sine waves while the third order terms
are usually at a frequency close to the input frequencies. As a
result, the second and third order terms are specified separately.
The calculation of the intermodulation distortion is as per the
THD specification where it is the ratio of the rms sum of the
individual distortion products to the rms amplitude of the sum
of the fundamentals expressed in dBs.

Power Supply Rejection Ratio

Power Supply Rejection Ratio (PSRR) is defined as the ratio of
the power in ADC output at frequency f to the power of the full­scale sine wave applied to the supply voltage (V

). The units

DD

are in LSB, %of FS per % of supply voltage, or expressed loga­rithmically, in dB (PSRR (dB) = 10 log(Pf/Pfs)).

Full Power Bandwidth

The Full Power Bandwidth (FPBW) is that frequency at which
the amplitude of the reconstructed (using FFTs) fundamental
(neglecting harmonics and SNR) is reduced by 3 dB for a full­scale input.

REV. A

–7–

AD7851

PIN FUNCTION DESCRIPTION

Pin Mnemonic Description

1

CONVST Convert Start. Logic input. A low to high transition on this input puts the track/hold into its hold mode and

starts conversion. When this input is not used, it should be tied to DV

2 BUSY Busy Output. The busy output is triggered high by the falling edge of

remains high until conversion is completed. BUSY is also used to indicate when the AD7851 has completed
its on-chip calibration sequence.

3

SLEEP Sleep Input/Low Power Mode. A logic 0 initiates a sleep and all circuitry is powered down including the in-

ternal voltage reference provided there is no conversion or calibration being performed. Calibration data is
retained. A logic 1 results in normal operation. See Power-Down section for more details.

4 REF

/ Reference Input/Output. This pin is connected to the internal reference through a series resistor and is the

IN

REF

OUT

reference source for the analog-to-digital converter. The nominal reference voltage is 4.096 V and this ap­pears at the pin. This pin can be overdriven by an external reference or can be taken as high as AV

5AV

DD

When this pin is tied to AV
Analog Positive Supply Voltage, +5.0 V ± 5%.

, then the C

DD

pin should also be tied to AVDD.

REF1

6, 12 AGND Analog Ground. Ground reference for track/hold, reference and DAC.
7C

REF1

Reference Capacitor (0.01 µF ceramic disc in parallel with a 470 nF NPO type). This external capacitor is
used as a charge source for the internal DAC. The capacitor should be tied between the pin and AGND.

8C

REF2

Reference Capacitor (0.01 µF ceramic disc in parallel with a 470 nF NPO type). This external capacitor is
used in conjunction with the on-chip reference. The capacitor should be tied between the pin and AGND.

9 AIN(+) Analog Input. Positive input of the pseudo-differential analog input. Cannot go below AGND or above

AV

at any time, and cannot go below AIN(–) when the unipolar input range is selected.

DD

10 AIN(–) Analog Input. Negative input of the pseudo-differential analog input. Cannot go below AGND or above

at any time.

AV

DD

11 NC No Connect Pin.
13 AMODE Analog Mode Pin. This pin allows two different analog input ranges to be selected. A logic 0 selects range 0

(i.e., AIN(+) – AIN(–) = 0 to V

to V

REF

AIN(–) cannot go below AGND. A logic 1 selects range –V
–V

/2 to +V

REF

+V

/2 to allow AIN(+) to go from 0 V to +V

REF

/2). In this case AIN(+) cannot go below AGND so that AIN(–) needs to be biased to

REF

). In this case AIN(+) cannot go below AIN(–) and

REF

REF

V.

/2 to +V

REF

14 POLARITY Serial Clock Polarity. This pin determines the active edge of the serial clock (SCLK). Toggling this pin will

reverse the active edge of the serial clock (SCLK). A logic 1 means that the serial clock (SCLK) idles high
and a logic 0 means that the serial clock (SCLK) idles low. It is best to refer to the timing diagrams and
Table X for the SCLK active edges.

15 SM1 Serial Mode Select Pin. This pin is used in conjunction with the SM2 pin to give different modes of opera-

tion as described in Table XI.

16 SM2 Serial Mode Select Pin. This pin is used in conjunction with the SM1 pin to give different modes of opera-

tion as described in Table XI.

17

CAL Calibration Input. This pin has an internal pull-up current source of 0.15 µA. A logic 0 on this pin resets all

logic and initiates a calibration on its rising edge. There is the option of connecting a 10nF capacitor from
this pin to AGND to allow for an automatic self calibration on power-up. This input overrides all other
internal operations.

18 DV

DD

Digital Supply Voltage, +5.0 V ± 5%.
19 DGND Digital Ground. Ground reference point for digital circuitry.
20 DOUT Serial Data Output. The data output is supplied to this pin as a 16-bit serial word.
21 DIN Serial Data Input. The data to be written is applied to this pin in serial form (16-bit word). This pin can act

as an input pin or as a I/O pin depending on the serial interface mode the part is in (see Table XI).
22 CLKIN Master Clock Signal for the device (6 MHz or 7 MHz). Sets the conversion and calibration times.
23 SCLK Serial Port Clock. Logic input/output. The SCLK pin is configured as an input or output, dependent on the

type of serial data transmission (self-clocking or external-clocking) that has been selected by the SM1 and

SM2 pins. The SCLK idles high or low depending on the state of the POLARITY pin.

SYNC This pin can be an input level triggered active low (similar to a chip select in one case and to a frame sync

24

in the other) or an output (similar to a frame sync) pin depending on SM1, SM2 (see Table XI).

.

DD

CONVST or rising edge of CAL, and

.

DD

/2 (i.e., AIN(+) – AIN(–) =

REF

–8–

REV. A

AD7851

RDSLT1, RDSLT0

DECODE

TEST

REGISTER

CALIBRATION

REGISTERS

STATUS

REGISTER

GAIN (1)

OFFSET (1)

DAC (8)

GAIN (1)

OFFSET (1)

OFFSET (1) GAIN (1)

01 10 11

00 01 10 11

CALSLT1, CALSLT0

DECODE

ADC OUTPUT

DATA REGISTER

00

AD7851 ON-CHIP REGISTERS

The AD7851 powers up with a set of default conditions, and the user need not ever write to the device. In this case the AD7851 will
operate as a Read-Only ADC. The AD7851 still retains the flexibility for performing a full power-down, and a full self-calibration.
Note that the DIN pin should be tied to DGND for operating the AD7851 as a Read-Only ADC.

Extra features and flexibility such as performing different power-down options, different types of calibrations including system cali­bration, and software conversion start can be selected by writing to the part.

The AD7851 contains a Control register, ADC output data register, Status register, Test register and 10 Calibration regis-
ters. The control register is write-only, the ADC output data register and the status register are read-only, and the test and calibra­tion registers are both read/write registers. The test register is used for testing the part and should not be written to.

Addressing the On-Chip Registers

Writing

A write operation to the AD7851 consists of 16 bits. The two MSBs, ADDR0 and ADDR1, are decoded to determine which register
is addressed, and the subsequent 14 bits of data are written to the addressed register. It is not until all 16 bits are written that the
data is latched into the addressed register. Table I shows the decoding of the address bits, while Figure 4 shows the overall write reg­ister hierarchy.

Table I. Write Register Addressing

ADDR1 ADDR0 Comment

0 0 This combination does not address any register so the subsequent 14 data bits are ignored.
0 1 This combination addresses the TEST REGISTER. The subsequent 14 data bits are written to the test register.
1 0 This combination addresses the CALIBRATION REGISTERS. The subsequent 14 data bits are written

to the selected calibration register.

1 1 This combination addresses the CONTROL REGISTER. The subsequent 14 data bits are written to the

control register.

Reading

To read from the various registers the user must first write to Bits 6 and 7 in the Control Register, RDSLT0 and RDSLT1. These
bits are decoded to determine which register is addressed during a read operation. Table II shows the decoding of the read address
bits while Figure 5 shows the overall read register hierarchy. The power-up status of these bits is 00 so that the default read will be
from the ADC output data register.

Once the read selection bits are set in the control register all subsequent read operations that follow will be from the selected register
until the read selection bits are changed in the control register.

Table II. Read Register Addressing

RDSLT1 RDSLT0 Comment

0 0 All successive read operations will be from ADC OUTPUT DATA REGISTER. This is the power-up de-

fault setting. There will always be four leading zeros when reading from the ADC output data register.
0 1 All successive read operations will be from TEST REGISTER.
1 0 All successive read operations will be from CALIBRATION REGISTERS.
1 1 All successive read operations will be from STATUS REGISTER.

ADDR1, ADDR0

DECODE

01 10 11

TEST

REGISTER

GAIN (1)

OFFSET (1)

DAC (8)

CALSLT1, CALSLT0

DECODE

Figure 4. Write Register Hierarchy/Address Decoding

00 01 10 11

CALIBRATION

REGISTERS

GAIN (1)

OFFSET (1)

OFFSET (1) GAIN (1)

CONTROL
REGISTER

Figure 5. Read Register Hierarchy/Address Decoding

REV. A

–9–

AD7851

CONTROL REGISTER

The arrangement of the control register is shown below. The control register is a write only register and contains 14 bits of data. The
control register is selected by putting two 1s in ADDR1 and ADDR0. The function of the bits in the control register are described
below. The power-up status of all bits is 0.

MSB

ZERO ZERO ZERO ZERO PMGT1 PMGT0 PMGT1

RDSLT0 2/

Bit Mnemonic Comment

13 ZERO These four bits must be set to 0 when writing to the control register.
12 ZERO
11 ZERO
10 ZERO

9 PMGT1 Power Management Bits. These two bits are used with the
8 PMGT0 power-down modes (see Power-Down section for more details).

7 RDSLT1 Theses two bits determine which register is addressed for the read operations. See Table II.
6 RDSLT0

52/

4 CONVST Conversion Start Bit. A logic one in this bit position starts a single conversion, and this bit is automati-

3 CALMD Calibration Mode Bit. A 0 here selects self-calibration and a 1 selects a system calibration (see Table III).
2 CALSLT1 Calibration Selection Bits and Start Calibration Bit. These bits have two functions.

1 CALSLT0 With the STCAL bit set to 1, the CALSLT1 and CALSLT0 bits determine the type of calibration per­0 STCAL formed by the part (see Table III). The STCAL bit is automatically reset to 0 at the end of calibration.

3 MODE Interface Mode Select Bit. With this bit set to 0, Interface Mode 2 is enabled. With this bit set to 1,

Interface Mode 1 is enabled where DIN is used as an output as well as an input. This bit is set to 0 by
default after every read cycle; thus when using Interface Mode 1, this bit needs to be set to 1 in every
write cycle.

cally reset to 0 at the end of conversion. This bit may also used in conjunction with system calibration
(see Calibration section on page 21).

With the STCAL bit set to 0, the CALSLT1 and CALSLT0 bits are decoded to address the calibration
register for read/write of calibration coefficients (see section on the calibration registers for more details).

3 MODE CONVST CALMD CALST1 CALSLT0 STCAL

LSB

Control Register Bit Function Description

SLEEP pin for putting the part into various

Table III. Calibration Selection

CALMD CALSLT1 CALSLT0 Calibration Type

00 0 A full internal calibration is initiated where the internal DAC is calibrated followed by the

internal gain error and finally the internal offset error is calibrated out. This is the default setting.

0 0 1 Here the internal gain error is calibrated out followed by the internal offset error calibrated

out.
0 1 0 This calibrates out the internal offset error only.
0 1 1 This calibrates out the internal gain error only.
10 0 A full system calibration is initiated here where first the internal DAC is calibrated, fol-

lowed by the system gain error, and finally the system offset error is calibrated out.
1 0 1 Here the system gain error is calibrated out followed by the system offset error.
1 1 0 This calibrates out the system offset error only.
1 1 1 This calibrates out the system gain error only.

–10–

REV. A

AD7851

STATUS REGISTER

The arrangement of the status register is shown below. The status register is a read-only register and contains 16 bits of data. The
status register is selected by first writing to the control register and putting two 1s in RDSLT1 and RDSLT0. The function of the
bits in the status register are described below. The power-up status of all bits is 0.

START

WRITE TO CONTROL REGISTER

SETTING RDSLT0 = RDSLT1 = 1

READ STATUS REGISTER

Figure 6. Flowchart for Reading the Status Register

MSB

ZERO BUSY ZERO ZERO ZERO ZERO PMGT1 PMGT0

RDSLT1 RDSLT0 2/

3 MODE X CALMD CALSLT1 CALSLT0 STCAL

LSB

Status Register Bit Function Description

Bit Mnemonic Comment

15 ZERO This bit is always 0.
14 BUSY Conversion/Calibration Busy Bit. When this bit is 1, this indicates that there is a conversion or calibration

in progress. When this bit is 0, there is no conversion or calibration in progress.

13 ZERO These four bits are always 0.
12 ZERO
11 ZERO
10 ZERO

9 PMGT1 Power Management Bits. These bits along with the

SLEEP pin will indicate if the part is in a power-down

8 PMGT0 mode or not. See Table VI in Power-Down Section for description.
7 ONE Both these bits are always 1 indicating it is the status register that is being read. See Table II.

6 ONE
52/

3 MODE Interface Mode Select Bit. With this bit 0, the device is in Interface Mode 2. With this bit 1, the device is in

Interface Mode 1. This bit is reset to 0 after every read cycle.
4 X Don’t care bit.
3 CALMD Calibration Mode Bit. A 0 in this bit indicates a self-calibration is selected, and a 1 in this bit indicates a

system calibration is selected (see Table III).
2 CALSLT1 Calibration Selection Bits and Start Calibration Bit. The STCAL bit is read as a 1 if a calibration is in

1 CALSLT0 progress and as a 0 if there is no calibration in progress. The CALSLT1 and CALSLT0 bits indicate
0 STCAL which of the calibration registers are addressed for reading and writing (see section on the Calibration

Registers for more details).

REV. A

–11–