Analog Devices AD7851CB, AD7851KR, AD7851KN, AD7851ARS, AD7851AR Datasheet

...

Download

AIN(+)

AIN(–)

REF1

REF2

CAL

AGND

DGND

AMODE

CLKIN

SLEEP

CONVST

BUSY

SYNC

SM1 SM2 DIN DOUT SCLK

POLARITY

CHARGE

REDISTRIBUTION

DAC

COMP

4.096 V

REFERENCE

AD7851

BUF

T/H

SAR + ADC

CONTROL

CALIBRATION

MEMORY

AND CONTROLLER

SERIAL INTERFACE / CONTROL REGISTER

REFIN/

REF

OUT

14-Bit 333 kSPS

FEATURES Single 5 V Supply 333 kSPS Throughput Rate/62 LSB DNL—A Grade 285 kSPS Throughput Rate/61 LSB DNL—K Grade A & K Grades Guaranteed to 1258C/238 kSPS

Throughput Rate Pseudo-Differential Input with Two Input Ranges System and Self-Calibration with Autocalibration on

Power-Up Read/Write Capability of Calibration Data Low Power: 60 mW typ Power-Down Mode: 5 mW typ Power Consumption Flexible Serial Interface:

8051/SPI/QSPI/ mP Compatible 24-Pin DIP, SOIC and SSOP Packages

APPLICATIONS Digital Signal Processing Speech Recognition and Synthesis Spectrum Analysis DSP Servo Control Instrumentation and Control Systems High Speed Modems Automotive

Serial A/D Converter

AD7851

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

The AD7851 is a high speed, 14-bit ADC that operates from a single 5 V power supply. The ADC powers-up with a set of default conditions at which time it can be operated as a readonly ADC. The ADC contains self-calibration and systemcalibration options to ensure accurate operation over time and temperature and has a number of power-down options for low power applications.

The AD7851 is capable of 333 kHz throughput rate. The input track-and-hold acquires a signal in 0.33 µs and features a pseudo-differential sampling scheme. The AD7851 has the added advantage of two input voltage ranges (0 V to V

/2 to +V

REF

–V is to V to 20 MHz.

CMOS construction ensures low power dissipation (60 mW typ) with power-down mode (5 µW typ). The part is available in 24-

/2 centered about V

REF

and the part is capable of converting full-power signals

/2). Input signal range

REF

REF,

and

pin, 0.3 inch-wide dual-in-line package (DIP), 24-lead small outline (SOIC) and 24-lead small shrink outline (SSOP) packages.

*Patent pending.

See Page 35 for data sheet index.

REV. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

PRODUCT HIGHLIGHTS

1. Single 5 V supply.

2. Operates with reference voltages from 4 V to V

3. Analog input ranges from 0 V to V

4. System and self-calibration including power-down mode.

5. Versatile serial I/O port.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703

AD7851–SPECIFICA TIONS

238 kHz; (AVDD = DVDD = +5.0 V 6 5%, REFIN/REF

Parameter A

= 4.096 V External Reference; SLEEP = Logic High; TA = T

OUT

1, 2

A Grade: f (08C to +858C), f

= 7 MHz (–408C to +858C), f

CLKIN

= 285 kHz; A and K Grade: f

SAMPLE

= 333 kHz; K Grade: f

SAMPLE

CLKIN

to T

MIN

Units Test Conditions/Comments

CLKIN

= 5 MHz (to +1258C), f

, unless otherwise noted)

MAX

= 6 MHz

SAMPLE

DYNAMIC PERFORMANCE

Signal-to-Noise + Distortion Ratio3 (SNR) 77 78 dB mi n Typically SNR is 79.5 dB

Total Harmonic Distortion (THD) –86 –86 dB max V

= 10 kHz, Sine Wave, f

SAMPLE SAMPLE

= 333 kHz = 333 kHz,

Typically –96 dB

Peak Harmonic or Spurious Noise –87 –87 dB max V

= 10 kHz, f

SAMPLE

= 333 kHz

Intermodulation Distortion (IMD)

Second Order Terms –86 –90 dB typ fa = 9.983 kHz, fb = 10.05 kHz, f Third Order Terms –86 –90 dB typ fa = 9.983 kHz, fb = 10.05 kHz, f

SAMPLE SAMPLE

= 333 kHz = 333 kHz

Full Power Bandwidth 20 20 MHz typ @ 3 dB DC ACCURACY

Resolution 14 14 Bits Integral Nonlinearity ±2 ±1 LSB max Differential Nonlinearity ±2 ±1 LSB max Guaranteed No Missed Codes to 14 Bits Unipolar Offset Error ±10 ±10 LSB max Review: “Adjusting the Offset Calibration Positive Full-Scale Error ±10 ±10 LSB max Register” in the “Calibration Registers” section Negative Full-Scale Error ±10 ±10 LSB typ of the data sheet. Bipolar Zero Error ±1 ±1 LSB typ

ANALOG INPUT

Input Voltage Ranges 0 V to V

REF

0 V to V

Volts i.e., AIN(+) – AIN(–) = 0 V to V

REF

, AIN(–) can be

REF

biased up but AIN(+) cannot go below AIN(–).

±V

/2 ±V

REF

/2 Volts i.e., AIN(+) – AIN(–) = –V

REF

/2 to +V

REF

/2, AIN(–)

REF

should be biased up and AIN(+) can go below

AIN(–) but cannot go below 0 V. Leakage Current ±1 ±1 µA max Input Capacitance 20 20 pF typ

REFERENCE INPUT/OUTPUT

REFIN Input Voltage Range 4/V

4/V

V min/max Functional from 1.2 V Input Impedance 150 150 kΩ typ Resistor Connected to Internal Reference Node REF REF

Output Voltage 3.696/4.496 3.696/4.496 V min/max

OUT

Tempco 50 50 ppm/°C typ

OUT

LOGIC INPUTS

Input High Voltage, V Input Low Voltage, V Input Current, I Input Capacitance, C

INL

INH

VDD – 1.0 VDD – 1.0 V min

0.4 0.4 V max ±10 ±10 µA max V 10 10 pF max

= 0 V or V

LOGIC OUTPUTS

Output High Voltage, V Output Low Voltage, V Floating-State Leakage Current ±10 ±10 µA max Floating-State Output Capacitance

VDD – 0.4 VDD – 0.4 V min I

0.4 0.4 V max I 10 10 pF max

SOURCE

= 0.8 mA

SINK

= 200 µA

Output Coding Straight (Natural) Binary Unipolar Input Range

2s Complement Bipolar Input Range

CONVERSION RATE

Conversion Time 2.78 3.25 µs max 19.5 CLKIN Cycles Conversion + T/H Acquisition Time 3.0 3.5 µs max 21 CLKIN Cycles Throughput Rate

–2–

REV. A

AD7851

Parameter A

Units Test Conditions/Comments

POWER PERFORMANCE

DD, DVDD

Normal Mode Sleep Mode

+4.75/+5.25 +4.75/+5.25 V min/max 17 17 mA max AV

12 mA.

= DVDD = 4.75 V to 5.25 V. Typically

With External Clock On 20 20 µA typ Full Power-Down. Power management bits

in control register set as PMGT1 = 1, PMGT0 = 0.

600 600 µA typ Partial Power-Down. Power management bits in

control register set as PMGT1 = 1, PMGT0 = 1.

With External Clock Off 10 10 µA max Typically 1 µA. Full Power-Down. Power

management bits in control register set as PMGT1 = 1, PMGT0 = 0.

300 300 µA typ Partial Power-Down. Power management bits in

control register set as PMGT1 = 1, PMGT0 = 1.

Normal Mode Power Dissipation 89.25 89.25 mW max V

= 5.25 V: Typically 63 mW; SLEEP = VDD.

Sleep Mode Power Dissipation

With External Clock On 105 105 µW typ VDD = 5.25 V; SLEEP = 0 V With External Clock Off 52.5 52.5 µW max VDD = 5.25 V; Typically 5.25 µW; SLEEP = 0 V

SYSTEM CALIBRATION

Offset Calibration Span Gain Calibration Span

NOTES

Temperature ranges as follows: A Version, –40°C to +125°C; K Version, 0°C to +125°C.

Specifications apply after calibration.

SNR calculation includes distortion and noise components.

Sample tested @ +25°C to ensure compliance.

All digital inputs @ DGND except for CONVST, SLEEP , CAL, and SYNC @ DVDD. No load on the digital outputs. Analog inputs @ AGND.

CLKIN @ DGND when external clock off. All digital inputs @ DGND except for CONVST, SLEEP, CAL, and SYNC @ DVDD. No load on the digital outputs. Analog inputs @ AGND.

The offset and gain calibration spans are defined as the range of offset and gain errors that the AD7851 can calibrate. Note also that these are voltage spans and are not absolute voltages (i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–) ± 0.05 × V allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted out will be V explained in more detail in the calibration section of the data sheet.

Specifications subject to change without notice.

+0.05 × V +1.025 × V

/–0.05 × V

REF

/–0.975 × V

REF

V max/min Allowable Offset Voltage Span for Calibration V max/min Allowable Full-Scale Voltage Span for Calibratio

REF

± 0.025 × V

REF

). This is

REF

, and the

REV. A

–3–

AD7851

(AV

TIMING SPECIFICATIONS

Limit at T

MIN

, T

= DVDD = +5.0 V 6 5%; f

MAX

Parameter A, K Units Description

CLKIN

SCLK

CONVERT

11A

CAL

CAL1

CAL2

DELAY

NOTES Descriptions that refer to SCLK↑ (rising) or SCLK↓ (falling) edges here are with the POLARITY pin HIGH. For the POLARITY pin LOW then the opposite edge of

SCLK will apply.

Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. See

Table X and timing diagrams for different interface modes and calibration.

Mark/Space ratio for the master clock input is 40/60 to 60/40.

For Interface Modes 1, 2, 3 the SCLK max frequency will be 10 MHz. For Interface Modes 4 and 5 the SCLK will be an output and the frequency will be f

The CONVST pulse width will here only apply for normal operation. When the part is in power-down mode, a different CONVST pulse width will apply (see Power-

Down section).

Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.

For self-clocking mode (Interface Modes 4, 5) the nominal SCLK high and low times will be 0.5 t

t12 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated

back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t12, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading.

t14 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated

back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics is the true delay of the part in turning off the output drivers and configuring the DIN line as an input. Once this time has elapsed the user can drive the DIN line knowing that a bus conflict will not occur.

The typical time specified for the calibration times is for a master clock of 6 MHz.

Specifications subject to change without notice.

500 kHz min Master Clock Frequency 7 MHz max 10 MHz max Interface Modes 1, 2, 3 (External Serial Clock) f

CLK IN

MHz max Interface Modes 4, 5 (Internal Serial Clock) 100 ns min CONVST Pulse Width 50 ns max CONVST↓ to BUSY↑ Propagation Delay

3.25 µs max Conversion Time = 20 t –0.4 t ±0.4 t

0.6 t

SCLK

ns min SYNC↓ to SCLK↓ Setup Time (Noncontinuous SCLK Input)

ns min/max SYNC↓ to SCLK↓ Setup Time (Continuous SCLK Input)

ns min SYNC↓ to SCLK↓ Setup Time. Interface Mode 4 Only 30 ns max Delay from SYNC↓ until DOUT 3-State Disabled 30 ns max Delay from SYNC↓ until DIN 3-State Disabled 45 ns max Data Access Time After SCLK↓ 30 ns min Data Setup Time Prior to SCLK↑ 20 ns min Data Valid to SCLK Hold Time

0.4 t

SCLK SCLK

ns min SCLK High Pulse Width (Interface Modes 4 and 5)

ns min SCLK Low Pulse Width (Interface Modes 4 and 5) 30 ns min SCLK↑ to SYNC↑ Hold Time (Noncontinuous SCLK) 30/0.4 t

SCLK

ns min/max (Continuous SCLK) Does Not Apply to Interface Mode 3 50 ns max SCLK↑ to SYNC↑ Hold Time 50 ns max Delay from SYNC↑ until DOUT 3-State Enabled 90 ns max Delay from SCLK↑ to DIN Being Configured as Output 50 ns max Delay from SCLK↑ to DIN Being Configured as Input

2.5 t

CLKIN CLKIN

ns max CAL↑ to BUSY↑ Delay

ns max CONVST↓ to BUSY↑ Delay in Calibration Sequence

41.7 ms typ Full Self-Calibration Time, Master Clock Dependent (250026

37.04 ms typ Internal DAC Plus System Full-Scale Cal Time, Master Clock

4.63 ms typ System Offset Calibration Time, Master Clock Dependent 65 ns max Delay from CLK to SCLK

= 6 MHz, TA = T

CLKIN

)

MIN

Dependent (222228 t (27798 t

CLKIN

SCLK

)

= 0.5 t

CLKIN

to T

, unless otherwise noted)

MAX

CLKIN

)

CLKIN

–4–

REV. A

AD7851

TYPICAL TIMING DIAGRAMS

Figures 2 and 3 show typical read and write timing diagrams. Figure 2 shows the reading and writing after conversion in Interface Modes 2 and 3. To attain the maximum sample rate of 285 kHz in Interface Modes 2 and 3, reading and writing must be performed during conversion. Figure 3 shows the timing diagram for Interface Modes 4 and 5 with sample rate of 285 kHz. At least 330 ns acquisition time must be allowed (the time from the falling edge of BUSY to the next rising edge of

CONVST) before the next conversion begins to ensure that the part is settled to the 14-bit level. If the user does not want to provide the

CONVST signal, the conversion can be initiated in software

by writing to the control register.

= 3.25µs MAX, t1 = 100ns MIN,

CONVERT

= 30ns MAX, t7 = 30ns MIN

DB15

DB15 DB0

CONVST (I/P)

BUSY (O/P)

SYNC (I/P)

SCLK (I/P)

DOUT (O/P)

DIN (I/P)

POLARITY PIN LOGIC HIGH

CONVERT

3-STATE

OUTPUT

50pF

1.6mA

200µA

Figure 1. Load Circuit for Digital Output Timing Specifications

DB11

DB0DB11

3-STATE

+2.1V

Figure 2. AD7851 Timing Diagram (Typical Read and Write Operation for Interface Modes 2, 3)

= 3.25µs MAX, t1 = 100ns MIN,

CONVERT

= 30ns MAX, t7 = 30ns MIN

CONVERT

DB11

DB0DB11

3-STATE

CONVST (I/P)

BUSY (O/P)

SYNC (O/P)

SCLK (O/P)

DOUT (O/P)

DIN (I/P)

POLARITY PIN LOGIC HIGH

3-STATE

DB15 DB0

DB15

Figure 3. AD7851 Timing Diagram (Typical Read and Write Operation for Interface Modes 4, 5)

REV. A

–5–

AD7851

ABSOLUTE MAXIMUM RATINGS

(TA = +25°C unless otherwise noted)

AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

to DVDD . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

Analog Input Voltage to AGND . . . . –0.3 V to AV

Digital Input Voltage to DGND . . . . –0.3 V to DV

Digital Output Voltage to DGND . . . –0.3 V to DV REF

/REF

Input Current to Any Pin Except Supplies

to AGND . . . . . . . . . –0.3 V to AVDD + 0.3 V

OUT

. . . . . . . . ±10 mA

+ 0.3 V

Operating Temperature Range

Commercial (A, K Versions) . . . . . . . . . . –40°C to +125°C

Storage Temperature Range . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . 105°C/W

Thermal Impedance . . . . . . . . . . . . . . . . . . . . 34.7°C/W

Lead Temperature, (Soldering, 10 secs) . . . . . . . . . . +260°C

SOIC, SSOP Package, Power Dissipation . . . . . . . . . 450 mW

Thermal Impedance . . . 75°C/W (SOIC) 115°C/W (SSOP)

Thermal Impedance . . . . 25°C/W (SOIC) 35°C/W (SSOP)

Lead Temperature, Soldering

Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >1.5 kV

NOTES

Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Transient currents of up to 100 mA will not cause SCR latch-up.

PINOUT FOR DIP, SOIC AND SSOP

24 23 22 21 20 19 18 17 16 15 14 13

SYNC

SCLK CLKIN DIN DOUT DGND DV

CAL

SM2 SM1 POLARITY AMODE

REF

CONVST

BUSY

SLEEP

/REF

AGND C C AIN(+) AIN(–)

AGND

REF REF

OUT

1 2

10 11 12

1 2 3 4 5

AD7851

TOP VIEW

(Not to Scale)

7 8 9

ORDERING GUIDE

Linearity

Temp Error Throughput Throughput Package

Model Range (LSB)

Rate @ +1258C Options

AD7851AN –40°C to +85°C ±2 333 kSPS 238 kSPS N-24 AD7851KN 0°C to +85°C ±1 285 kSPS 238 kSPS N-24 AD7851AR –40°C to +85°C ±2 333 kSPS 238 kSPS R-24 AD7851KR 0°C to +85°C ±1 285 kSPS 238 kSPS R-24 AD7851ARS –40 °C to +85°C ±2 333 kSPS 238 kSPS RS-24 EVAL-AD7851CB EVAL-CONTROL BOARD

NOTES

Both A and K Grades are guaranteed up to 125°C, but at a lower throughput of 238 kHz (5 MHz).

Linearity error refers to the integral linearity error.

N = Plastic DIP; R = SOIC; RS = SSOP.

This can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL BOARD for evaluation/demonstration

purposes.

This board is a complete unit allowing a PC to control and communicate with all Analog Devices, Inc. evaluation boards ending in the

CB designators.

–6–

REV. A

AD7851

TERMINOLOGY

Integral Nonlinearity

This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point 1/2 LSB below the first code transition, and full scale, a point 1/2 LSB above the last code transition.

Differential Nonlinearity

This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC.

Total Unadjusted Error

This is the deviation of the actual code from the ideal code taking all errors into account (Gain, Offset, Integral Nonlinearity, and other errors) at any point along the transfer function.

Unipolar Offset Error

This is the deviation of the first code transition (00 . . . 000 to 00 . . . 001) from the ideal AIN(+) voltage (AIN(–) + 1/2 LSB) when operating in the unipolar mode.

Positive Full-Scale Error

This applies to the unipolar and bipolar modes and is the deviation of the last code transition from the ideal AIN(+) voltage (AIN(–) + Full Scale – 1.5 LSB) after the offset error has been adjusted out.

Negative Full-Scale Error

This applies to the bipolar mode only and is the deviation of the first code transition (00 . . . 000 to 00 . . . 001) from the ideal AIN(+) voltage (AIN(–) – V

/2 + 0.5 LSB).

REF

Bipolar Zero Error

This is the deviation of the midscale transition (all 0s to all 1s) from the ideal AIN(+) voltage (AIN(–) – 1/2 LSB).

Track/Hold Acquisition Time

The track/hold amplifier returns into track mode and the end of conversion. Track/Hold acquisition time is the time required for the output of the track/hold amplifier to reach its final value, within ±1/2 LSB, after the end of conversion.

Signal to (Noise + Distortion) Ratio

This is the measured ratio of signal to (noise + distortion) at the output of the A/D converter. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (f

/2), excluding dc. The

ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by:

Signal to (Noise + Distortion) = (6.02 N +1.76)dB

Thus for a 14-bit converter, this is 86 dB.

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7851, it is defined as:





THD(dB) =20log





where V1 is the rms amplitude of the fundamental and V2, V3, V

, V5 and V6 are the rms amplitudes of the second through the

sixth harmonics.

Peak Harmonic or Spurious Noise

Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to f

/2 and excluding dc) to the rms value of the

fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for parts where the harmonics are buried in the noise floor, it will be a noise peak.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa ± nfb where m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are those for which neither m nor n are equal to zero. For example, the second order terms include (fa + fb) and (fa – fb), while the third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).

Testing is performed using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. As a result, the second and third order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dBs.

Power Supply Rejection Ratio

Power Supply Rejection Ratio (PSRR) is defined as the ratio of the power in ADC output at frequency f to the power of the fullscale sine wave applied to the supply voltage (V

). The units

are in LSB, %of FS per % of supply voltage, or expressed logarithmically, in dB (PSRR (dB) = 10 log(Pf/Pfs)).

Full Power Bandwidth

The Full Power Bandwidth (FPBW) is that frequency at which the amplitude of the reconstructed (using FFTs) fundamental (neglecting harmonics and SNR) is reduced by 3 dB for a fullscale input.

REV. A

–7–

AD7851

PIN FUNCTION DESCRIPTION

Pin Mnemonic Description

CONVST Convert Start. Logic input. A low to high transition on this input puts the track/hold into its hold mode and

starts conversion. When this input is not used, it should be tied to DV

2 BUSY Busy Output. The busy output is triggered high by the falling edge of

remains high until conversion is completed. BUSY is also used to indicate when the AD7851 has completed its on-chip calibration sequence.

SLEEP Sleep Input/Low Power Mode. A logic 0 initiates a sleep and all circuitry is powered down including the in-

ternal voltage reference provided there is no conversion or calibration being performed. Calibration data is retained. A logic 1 results in normal operation. See Power-Down section for more details.

4 REF

/ Reference Input/Output. This pin is connected to the internal reference through a series resistor and is the

REF

OUT

reference source for the analog-to-digital converter. The nominal reference voltage is 4.096 V and this appears at the pin. This pin can be overdriven by an external reference or can be taken as high as AV

5AV

When this pin is tied to AV Analog Positive Supply Voltage, +5.0 V ± 5%.

, then the C

pin should also be tied to AVDD.

REF1

6, 12 AGND Analog Ground. Ground reference for track/hold, reference and DAC. 7C

REF1

Reference Capacitor (0.01 µF ceramic disc in parallel with a 470 nF NPO type). This external capacitor is used as a charge source for the internal DAC. The capacitor should be tied between the pin and AGND.

REF2

Reference Capacitor (0.01 µF ceramic disc in parallel with a 470 nF NPO type). This external capacitor is used in conjunction with the on-chip reference. The capacitor should be tied between the pin and AGND.

9 AIN(+) Analog Input. Positive input of the pseudo-differential analog input. Cannot go below AGND or above

at any time, and cannot go below AIN(–) when the unipolar input range is selected.

10 AIN(–) Analog Input. Negative input of the pseudo-differential analog input. Cannot go below AGND or above

at any time.

11 NC No Connect Pin. 13 AMODE Analog Mode Pin. This pin allows two different analog input ranges to be selected. A logic 0 selects range 0

(i.e., AIN(+) – AIN(–) = 0 to V

to V

REF

AIN(–) cannot go below AGND. A logic 1 selects range –V –V

/2 to +V

REF

/2 to allow AIN(+) to go from 0 V to +V

REF

/2). In this case AIN(+) cannot go below AGND so that AIN(–) needs to be biased to

REF

). In this case AIN(+) cannot go below AIN(–) and

REF

/2 to +V

REF

14 POLARITY Serial Clock Polarity. This pin determines the active edge of the serial clock (SCLK). Toggling this pin will

reverse the active edge of the serial clock (SCLK). A logic 1 means that the serial clock (SCLK) idles high and a logic 0 means that the serial clock (SCLK) idles low. It is best to refer to the timing diagrams and Table X for the SCLK active edges.

15 SM1 Serial Mode Select Pin. This pin is used in conjunction with the SM2 pin to give different modes of opera-

tion as described in Table XI.

16 SM2 Serial Mode Select Pin. This pin is used in conjunction with the SM1 pin to give different modes of opera-

tion as described in Table XI.

CAL Calibration Input. This pin has an internal pull-up current source of 0.15 µA. A logic 0 on this pin resets all

logic and initiates a calibration on its rising edge. There is the option of connecting a 10nF capacitor from this pin to AGND to allow for an automatic self calibration on power-up. This input overrides all other internal operations.

18 DV

Digital Supply Voltage, +5.0 V ± 5%. 19 DGND Digital Ground. Ground reference point for digital circuitry. 20 DOUT Serial Data Output. The data output is supplied to this pin as a 16-bit serial word. 21 DIN Serial Data Input. The data to be written is applied to this pin in serial form (16-bit word). This pin can act

as an input pin or as a I/O pin depending on the serial interface mode the part is in (see Table XI). 22 CLKIN Master Clock Signal for the device (6 MHz or 7 MHz). Sets the conversion and calibration times. 23 SCLK Serial Port Clock. Logic input/output. The SCLK pin is configured as an input or output, dependent on the

type of serial data transmission (self-clocking or external-clocking) that has been selected by the SM1 and

SM2 pins. The SCLK idles high or low depending on the state of the POLARITY pin.

SYNC This pin can be an input level triggered active low (similar to a chip select in one case and to a frame sync

in the other) or an output (similar to a frame sync) pin depending on SM1, SM2 (see Table XI).

CONVST or rising edge of CAL, and

/2 (i.e., AIN(+) – AIN(–) =

REF

–8–

REV. A

AD7851

RDSLT1, RDSLT0

DECODE

TEST

CALIBRATION

REGISTERS

STATUS

GAIN (1)

OFFSET (1)

DAC (8)

GAIN (1)

OFFSET (1)

OFFSET (1) GAIN (1)

01 10 11

00 01 10 11

CALSLT1, CALSLT0

DECODE

ADC OUTPUT

DATA REGISTER

AD7851 ON-CHIP REGISTERS

The AD7851 powers up with a set of default conditions, and the user need not ever write to the device. In this case the AD7851 will operate as a Read-Only ADC. The AD7851 still retains the flexibility for performing a full power-down, and a full self-calibration. Note that the DIN pin should be tied to DGND for operating the AD7851 as a Read-Only ADC.

Extra features and flexibility such as performing different power-down options, different types of calibrations including system calibration, and software conversion start can be selected by writing to the part.

The AD7851 contains a Control register, ADC output data register, Status register, Test register and 10 Calibration regis- ters. The control register is write-only, the ADC output data register and the status register are read-only, and the test and calibration registers are both read/write registers. The test register is used for testing the part and should not be written to.

Addressing the On-Chip Registers

Writing

A write operation to the AD7851 consists of 16 bits. The two MSBs, ADDR0 and ADDR1, are decoded to determine which register is addressed, and the subsequent 14 bits of data are written to the addressed register. It is not until all 16 bits are written that the data is latched into the addressed register. Table I shows the decoding of the address bits, while Figure 4 shows the overall write register hierarchy.

Table I. Write Register Addressing

ADDR1 ADDR0 Comment

0 0 This combination does not address any register so the subsequent 14 data bits are ignored. 0 1 This combination addresses the TEST REGISTER. The subsequent 14 data bits are written to the test register. 1 0 This combination addresses the CALIBRATION REGISTERS. The subsequent 14 data bits are written

to the selected calibration register.

1 1 This combination addresses the CONTROL REGISTER. The subsequent 14 data bits are written to the

control register.

Reading

To read from the various registers the user must first write to Bits 6 and 7 in the Control Register, RDSLT0 and RDSLT1. These bits are decoded to determine which register is addressed during a read operation. Table II shows the decoding of the read address bits while Figure 5 shows the overall read register hierarchy. The power-up status of these bits is 00 so that the default read will be from the ADC output data register.

Once the read selection bits are set in the control register all subsequent read operations that follow will be from the selected register until the read selection bits are changed in the control register.

Table II. Read Register Addressing

RDSLT1 RDSLT0 Comment

0 0 All successive read operations will be from ADC OUTPUT DATA REGISTER. This is the power-up de-

fault setting. There will always be four leading zeros when reading from the ADC output data register. 0 1 All successive read operations will be from TEST REGISTER. 1 0 All successive read operations will be from CALIBRATION REGISTERS. 1 1 All successive read operations will be from STATUS REGISTER.

ADDR1, ADDR0

DECODE

01 10 11

TEST

GAIN (1)

OFFSET (1)

DAC (8)

CALSLT1, CALSLT0

DECODE

Figure 4. Write Register Hierarchy/Address Decoding

00 01 10 11

CALIBRATION

REGISTERS

GAIN (1)

OFFSET (1)

OFFSET (1) GAIN (1)

CONTROL REGISTER

Figure 5. Read Register Hierarchy/Address Decoding

REV. A

–9–

AD7851

CONTROL REGISTER

The arrangement of the control register is shown below. The control register is a write only register and contains 14 bits of data. The control register is selected by putting two 1s in ADDR1 and ADDR0. The function of the bits in the control register are described below. The power-up status of all bits is 0.

MSB

ZERO ZERO ZERO ZERO PMGT1 PMGT0 PMGT1

RDSLT0 2/

Bit Mnemonic Comment

13 ZERO These four bits must be set to 0 when writing to the control register. 12 ZERO 11 ZERO 10 ZERO

9 PMGT1 Power Management Bits. These two bits are used with the 8 PMGT0 power-down modes (see Power-Down section for more details).

7 RDSLT1 Theses two bits determine which register is addressed for the read operations. See Table II. 6 RDSLT0

52/

4 CONVST Conversion Start Bit. A logic one in this bit position starts a single conversion, and this bit is automati-

3 CALMD Calibration Mode Bit. A 0 here selects self-calibration and a 1 selects a system calibration (see Table III). 2 CALSLT1 Calibration Selection Bits and Start Calibration Bit. These bits have two functions.

1 CALSLT0 With the STCAL bit set to 1, the CALSLT1 and CALSLT0 bits determine the type of calibration per0 STCAL formed by the part (see Table III). The STCAL bit is automatically reset to 0 at the end of calibration.

3 MODE Interface Mode Select Bit. With this bit set to 0, Interface Mode 2 is enabled. With this bit set to 1,

Interface Mode 1 is enabled where DIN is used as an output as well as an input. This bit is set to 0 by default after every read cycle; thus when using Interface Mode 1, this bit needs to be set to 1 in every write cycle.

cally reset to 0 at the end of conversion. This bit may also used in conjunction with system calibration (see Calibration section on page 21).

With the STCAL bit set to 0, the CALSLT1 and CALSLT0 bits are decoded to address the calibration register for read/write of calibration coefficients (see section on the calibration registers for more details).

3 MODE CONVST CALMD CALST1 CALSLT0 STCAL

LSB

Control Register Bit Function Description

SLEEP pin for putting the part into various

Table III. Calibration Selection

CALMD CALSLT1 CALSLT0 Calibration Type

00 0 A full internal calibration is initiated where the internal DAC is calibrated followed by the

internal gain error and finally the internal offset error is calibrated out. This is the default setting.

0 0 1 Here the internal gain error is calibrated out followed by the internal offset error calibrated

out. 0 1 0 This calibrates out the internal offset error only. 0 1 1 This calibrates out the internal gain error only. 10 0 A full system calibration is initiated here where first the internal DAC is calibrated, fol-

lowed by the system gain error, and finally the system offset error is calibrated out. 1 0 1 Here the system gain error is calibrated out followed by the system offset error. 1 1 0 This calibrates out the system offset error only. 1 1 1 This calibrates out the system gain error only.

–10–

REV. A

AD7851

STATUS REGISTER

The arrangement of the status register is shown below. The status register is a read-only register and contains 16 bits of data. The status register is selected by first writing to the control register and putting two 1s in RDSLT1 and RDSLT0. The function of the bits in the status register are described below. The power-up status of all bits is 0.

START

WRITE TO CONTROL REGISTER

SETTING RDSLT0 = RDSLT1 = 1

READ STATUS REGISTER

Figure 6. Flowchart for Reading the Status Register

MSB

ZERO BUSY ZERO ZERO ZERO ZERO PMGT1 PMGT0

RDSLT1 RDSLT0 2/

3 MODE X CALMD CALSLT1 CALSLT0 STCAL

LSB

Status Register Bit Function Description

Bit Mnemonic Comment

15 ZERO This bit is always 0. 14 BUSY Conversion/Calibration Busy Bit. When this bit is 1, this indicates that there is a conversion or calibration

in progress. When this bit is 0, there is no conversion or calibration in progress.

13 ZERO These four bits are always 0. 12 ZERO 11 ZERO 10 ZERO

9 PMGT1 Power Management Bits. These bits along with the

SLEEP pin will indicate if the part is in a power-down

8 PMGT0 mode or not. See Table VI in Power-Down Section for description. 7 ONE Both these bits are always 1 indicating it is the status register that is being read. See Table II.

6 ONE 52/

3 MODE Interface Mode Select Bit. With this bit 0, the device is in Interface Mode 2. With this bit 1, the device is in

Interface Mode 1. This bit is reset to 0 after every read cycle. 4 X Don’t care bit. 3 CALMD Calibration Mode Bit. A 0 in this bit indicates a self-calibration is selected, and a 1 in this bit indicates a

system calibration is selected (see Table III). 2 CALSLT1 Calibration Selection Bits and Start Calibration Bit. The STCAL bit is read as a 1 if a calibration is in

1 CALSLT0 progress and as a 0 if there is no calibration in progress. The CALSLT1 and CALSLT0 bits indicate 0 STCAL which of the calibration registers are addressed for reading and writing (see section on the Calibration

Registers for more details).

REV. A

–11–

AD7851

START

WRITE TO CAL REGISTER

(ADDR1 = 1, ADDR0 = 0)

FINISHED

LAST

WRITE

OPERATION

ABORT

YES

CAL REGISTER POINTER IS

AUTOMATICALLY RESET

WRITE TO CONTROL REGISTER SETTING STCAL = 0

AND CALSLT1, CALSLT0 = 00, 01, 10, 11

CAL REGISTER POINTER IS

AUTOMATICALLY INCREMENTED

CALIBRATION REGISTERS

The AD7851 has 10 calibration registers in all, 8 for the DAC, 1 for the offset and 1 for gain. Data can be written to or read from all 10 calibration registers. In self and system calibration the part automatically modifies the calibration registers; only if the user needs to modify the calibration registers should an attempt be made to read from and write to the calibration registers.

Addressing the Calibration Registers

The calibration selection bits in the control register CALSLT1 and CALSLT0 determine which of the calibration registers are addressed (see Table IV). The addressing applies to both the read and write operations for the calibration registers. The user should not attempt to read from and write to the calibration registers at the same time.

Table IV. Calibration Register Addressing

CALSLT1 CALSLT0 Comment

0 0 This combination addresses the Gain (1), Offset (1) and DAC Registers (8). Ten registers in total. 0 1 This combination addresses the Gain (1) and Offset (1) Registers. Two registers in total. 1 0 This combination addresses the Offset Register. One register in total. 1 1 This combination addresses the Gain Register. One register in total.

Writing to/Reading from the Calibration Registers

For writing to the calibration registers a write to the control register is required to set the CALSLT0 and CALSLT1 bits. For reading from the calibration registers a write to the control register is required to set the CALSLT0 and CALSLT1 bits, but also to set the RDSLT1 and RDSLT0 bits to 10 (this addresses the calibration registers for reading). The calibration register pointer is reset on writing to the control register setting the CALSLT1 and CALSLT0 bits, or upon completion of all the calibration register write/read operations. When reset it points to the first calibration register in the selected write/read sequence. The calibration register pointer will point to the gain calibration register upon reset in all but one case, this case being where the offset calibration register is selected on its own (CALSLT1 = 1, CALSLT0 = 0). Where more than one calibration register is being accessed, the calibration register pointer will be automatically incremented after each calibration register write/read operation. The order in which the 10 calibration registers are arranged is shown in Figure 7. The user may abort at any time before all the calibration register write/read operations are completed, and the next control register write operation will reset the calibration register pointer. The flowchart in Figure 8 shows the sequence for writing to the calibration registers and Figure 9 for reading.

CAL REGISTER

ADDRESS POINTER

CALIBRATION REGISTERS

GAIN REGISTER

OFFSET REGISTER

DAC 1st MSB REGISTER

When reading from the calibration registers there will always be two leading zeros for each of the registers. When operating in serial Interface Mode 1, the read operations to the calibration registers cannot be aborted. The full number of read operations must be completed (see section on serial Interface Mode 1 timing for more detail).

(1) (2)

(3)

CALIBRATION REGISTER ADDRESS POINTER POSITION IS DETERMINED BY THE NUMBER OF CALIBRATION REGISTERS ADDRESSED AND THE NUMBER OF READ/WRITE OPERATIONS.

Figure 7. Calibration Register Arrangement

DAC 8th MSB REGISTER

(10)

Figure 8. Flowchart for Writing to the Calibration Registers

–12–

REV. A

AD7851

START

WRITE TO CONTROL REGISTER SETTING STCAL = 0, RDSLT1 = 1,

RDSLT0 = 0, AND CALSLT1, CALSLT0 = 00, 01, 10, 11

CAL REGISTER POINTER IS

AUTOMATICALLY RESET

READ CAL REGISTER

CAL REGISTER POINTER IS

AUTOMATICALLY INCREMENTED

LAST

WRITE

OPERATION

ABORT

FINISHED

YES

Figure 9. Flowchart for Reading from the Calibration Registers

Adjusting the Offset Calibration Register

The offset calibration register contains 16 bits, two leading zeros and 14 data bits. By changing the contents of the offset register, different amounts of offset on the analog input signal can be compensated for. Increasing the number in the offset calibration register compensates for negative offset on the analog input signal, and decreasing the number in the offset calibration register compensates for positive offset on the analog input signal. The default value of the offset calibration register is 0010 0000 0000 0000 approximately. This is not an exact value, but the value in the offset register should be close to this value. Each of the 14 data bits in the offset register is binary weighted; the MSB has a weighting of 5% of the reference voltage, the MSB-1 has a weighting of 2.5%, the MSB-2 has a weighting of 1.25%, and so on down to the LSB which has a weighting of 0.0006%.

This gives a resolution of ±0.0006% of V More accurately the resolution is ±(0.05 × V

approximately.

REF

)/213 volts =

REF

±0.015 mV, with a 2.5 V reference. The maximum offset that can be compensated for is ± 5% of the reference voltage, which equates to ±125 mV with a 2.5 V reference and ±250 mV with a 5 V reference.

Q. If a +20 mV offset is present in the analog input signal and the

reference voltage is 2.5 V, what code needs to be written to the offset register to compensate for the offset?

A. 2.5 V reference implies that the resolution in the offset reg-

ister is 5% × 2.5 V/2

= 0.015 mV. +20 mV/0.015 mV =

1310.72; rounding to the nearest number gives 1311. In binary terms this is 0101 0001 1111, therefore decrease the offset register by 0101 0001 1111.

This method of compensating for offset in the analog input signal allows for fine tuning the offset compensation. If the offset on the analog input signal is known, there will be no need to apply the offset voltage to the analog input pins and do a system calibration. The offset compensation can take place in software.

Adjusting the Gain Calibration Register

The gain calibration register contains 16 bits, two leading 0s and 14 data bits. The data bits are binary weighted as in the offset calibration register. The gain register value is effectively multiplied by the analog input to scale the conversion result over the full range. Increasing the gain register compensates for a smaller analog input range and decreasing the gain register compensates for a larger input range. The maximum analog input range that the gain register can compensate for is 1.025 times the reference voltage, and the minimum input range is 0.975 times the reference voltage.

REV. A

–13–

AD7851

CIRCUIT INFORMATION

The AD7851 is a fast, 14-bit single supply A/D converter. The part requires an external 6/7 MHz master clock (CLKIN), two C

capacitors, a CONVST signal to start conversion and

REF

power supply decoupling capacitors. The part provides the user with track/hold, on-chip reference, calibration features, A/D converter and serial interface logic functions on a single chip. The A/D converter section of the AD7851 consists of a conventional successive-approximation converter based around a capacitor DAC. The AD7851 accepts an analog input range of 0 V to +V

where the reference can be tied to VDD. The refer-

ence input to the part is buffered onchip. A major advantage of the AD7851 is that a conversion can be

initiated in software as well as applying a signal to the

CONVST

pin. Another innovative feature of the AD7851 is self-calibration on power-up, which is initiated having a 0.01µF capacitor from the

CAL pin to AGND, to give superior dc accuracy. The part should be allowed 150 ms after power-up to perform this automatic calibration before any reading or writing takes place. The part is available in a 24-pin SSOP package and this offers the user considerable space saving advantages over alternative solutions.

CONVERTER DETAILS

The master clock for the part must be applied to the CLKIN pin. Conversion is initiated on the AD7851 by pulsing the CONVST input or by writing to the control register and setting the CONVST bit to 1. On the rising edge of

CONVST (or at the end of the control register write operation), the on-chip track/hold goes from track to hold mode. The falling edge of the CLKIN signal which follows the rising edge of the edge of CONVST signal initiates the conversion, provided the rising edge of

CONVST occurs at least 10 ns typically before this CLKIN edge. The conversion cycle will take 18.5 CLKIN periods from this CLKIN falling edge. If the 10 ns setup time is

not met, the conversion will take 19.5 CLKIN periods. The maximum specified conversion time is 3.25 µs (6 MHz ) and

2.8 µs (7 MHz) for the A and K Grades respectively for the AD7851 (19.5 t

CLKIN = 6/7 MHz). When a conversion

CLKIN,

is completed, the BUSY output goes low, and then the result of the conversion can be read by accessing the data through the serial interface. To obtain optimum performance from the part, the read operation should not occur during the conversion or 500 ns prior to the next

CONVST rising edge. However, the maximum throughput rates are achieved by reading/writing during conversion, and reading/writing during conversion is likely to degrade the Signal to (Noise + Distortion) by only 0.5 dBs. The AD7851 can operate at throughput rates up to 333 kHz. For the AD7851 a conversion takes 19.5 CLKIN periods, 2 CLKIN periods are needed for the acquisition time giving a full cycle time of 3.59 µs (= 279 kHz, CLKIN = 6 MHz) for the K grade and 3.08 µs (= 325 kHz, CLKIN = 7 MHz) for the A grade.

TYPICAL CONNECTION DIAGRAM

Figure 10 shows a typical connection diagram for the AD7851. The DIN line is tied to DGND so that no data is written to the part. The AGND and the DGND pins are connected together at the device for good noise suppression. The

CAL pin has a

0.01 µF capacitor to enable an automatic self-calibration on power-up. The SCLK and having SM1 and SM2 at DV

SYNC are configured as outputs by

. The conversion result is output

in a 16-bit word with 2 leading zeros followed by the MSB of the 14-bit result. Note that after the AV

and DVDD power-up,

the part will require 150 ms for the internal reference to settle and for the automatic calibration on power-up to be completed.

For applications where power consumption is a major concern, the

SLEEP pin can be connected to DGND. See Power-Down

section for more detail on low power applications.

ANALOG (5V)

SUPPLY

0V TO V

UNIPOLAR RANGE

AUTO CAL ON

POWER-UP

REFERENCE

ANALOG (5V)

SUPPLY

REF

INPUT

0.01µF

47nF

0.01µF

OPTIONAL

EXTERNAL

10µF

470nF

0.01µF

AD1584/REF198

10µF

0.01µF

AIN(+) AIN(–)

AMODE

REF1

REF2

SLEEP

POLARITY

CAL

AGND

DGND

0.1µF

AVDDDV

AD7851

/REF

REF

7MHz/6MHz

OSCILLATOR

0.1µF

OUT

0.01µF

CLKIN

SCLK

CONVST

SYNC

DOUT

INTERNAL REFERENCE

MASTER

CLOCK

SERIAL CLOCK OUTPUT

FRAME SYNC OUTPUT

SERIAL DATA OUTPUT

DIN

SM1

SM2

SELECTION BITS

INPUT

SERIAL MODE

Figure 10. Typical Circuit

–14–

333kHz/285kHz PULSE

GENERATOR

CONVERSION

START INPUT

DIN AT DGND => NO WRITING TO DEVICE

CH1

CH2

CH3

CH4

OSCILLOSCOPE

2 LEADING ZEROS

FOR ADC DATA

REV. A

AD7851

THD – dB

INPUT FREQUENCY – kHz

–50

–60

–110

–100

–80

–90

–70

1 16610 20 50

THD VS. FREQUENCY FOR DIFFERENT SOURCE IMPEDANCES

RIN = 560Ω

RIN = 10Ω, 10nF

AS IN FIGURE 13

140120100

IC1

+5V

10kΩ

V+

V–

10kΩ

10Ω

AD820

–V

REF

/2 TO +V

REF

10µF

0.1µF

10nF (NPO)

TO AIN(+) OF AD7851

ANALOG INPUT

The equivalent circuit of the analog input section is shown in Figure 11. During the acquisition interval the switches are both in the track position and the AIN(+) charges the 20 pF capacitor through the 125 Ω resistance. On the rising edge of CONVST switches SW1 and SW2 go into the hold position retaining charge on the 20 pF capacitor as a sample of the signal on AIN(+). The AIN(–) is connected to the 20 pF capacitor, and this unbalances the voltage at node A at the input of the comparator. The capacitor DAC adjusts during the remainder of the conversion cycle to restore the voltage at node A to the correct value. This action transfers a charge, representing the analog input signal, to the capacitor DAC which in turn forms a digital representation of the analog input signal. The voltage on the AIN(–) pin directly influences the charge transferred to the capacitor DAC at the hold instant. If this voltage changes during the conversion period, the DAC representation of the analog input voltage will be altered. Therefore it is most important that the voltage on the AIN(–) pin remains constant during the conversion period. Furthermore, it is recommended that the AIN(–) pin is always connected to AGND or to a fixed dc voltage.

125Ω

AIN(+)

AIN(–)

REF2

125Ω

TRACK

HOLD

SW1

NODE A

TRACK

SW2

20pF

HOLD

CAPACITOR

DAC

COMPARATOR

Figure 11. Analog Input Equivalent Circuit

Acquisition Time

The track and hold amplifier enters its tracking mode on the falling edge of the BUSY signal. The time required for the track and hold amplifier to acquire an input signal will depend on how quickly the 20 pF input capacitance is charged. The acquisition time is calculated using the formula:

= 9 × (RIN + 125 Ω) × 20 pF

ACQ

where R

is the source impedance of the input signal, and

125 Ω, 20 pF is the input R, C.

DC/AC Applications

For dc applications high source impedances are acceptable, provided there is enough acquisition time between conversions to charge the 20 pF capacitor. The acquisition time can be calculated from the above formula for different source impedances. For example with R

= 5 kΩ, the required acquisition time will

be 922 ns. For ac applications, removing high frequency components from

the analog input signal is recommended by use of an RC lowpass filter on the AIN(+) pin, as shown in Figure 13. In applications where harmonic distortion and signal to noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances will significantly affect the ac performance of the ADC. This may necessitate the use of an input buffer amplifier. The choice of the op amp will be a function of the particular application.

REV. A

–15–

When no amplifier is used to drive the analog input the source impedance should be limited to low values. The maximum source impedance will depend on the amount of total harmonic distortion (THD) that can be tolerated. The THD will increase as the source impedance increases and performance will degrade. Figure 12 shows a graph of the total harmonic distortion vs. analog input signal frequency for different source impedances. With the setup as in Figure 13, the THD is at the –90dB level. With a source impedance of 1 kΩ and no capacitor on the AIN(+) pin, the THD increases with frequency.

Figure 12. THD vs. Analog Input Frequency

In a single supply application (5 V), the V+ and V– of the op amp can be taken directly from the supplies to the AD7851 which eliminates the need for extra external power supplies. When operating with rail-to-rail inputs and outputs at frequencies greater than 10 kHz, care must be taken in selecting the particular op amp for the application. In particular, for single supply applications the input amplifiers should be connected in a gain of –1 arrangement to get the optimum performance. Figure 13 shows the arrangement for a single supply application with a 10 Ω and 10 nF low-pass filter (cutoff frequency 320 kHz) on the AIN(+) pin. Note that the 10 nF is a capacitor with good linearity to ensure good ac performance. Recommended single supply op amp is the AD820.

Figure 13. Analog Input Buffering

AD7851

+FS –1LSB

OUTPUT

CODE

111...111

111...110

111...101

111...100

000...011

000...001

000...000

000...010

VIN = (AIN(+) – AIN(–)), INPUT VOLTAGE

1LSB

1LSB =

16384

– 1 LSB

FS = V

REF

1LSB =

16384

OUTPUT

CODE

REF

011...111

011...110

000...001

000...000

100...001

100...000

100...010

VIN = (AIN(+) – AIN(–)), INPUT VOLTAGE

+ FS

111...111

REF

/2) –1 LSB

REF

/2) +1 LSB

Input Ranges

The analog input range for the AD7851 is 0 V to V

in both

REF

the unipolar and bipolar ranges. The only difference between the unipolar range and the bipolar

range is that in the bipolar range the AIN(–) has to be biased up to +V

/2 and the output coding is 2s complement (See Table

REF

V and Figures 14 and 15). The unipolar or bipolar mode is selected by the AMODE pin (0 for the unipolar range and 1 for the bipolar range).

Table V. Analog Input Connections

Analog Input Input Connections Connection Range AIN(+) AIN(–) Diagram AMODE

REF

/2 biased about V

AGND Figure 8 DGND V

/2 Figure 9 DV

REF

/2. Output code format is 2s complement.

REF

0 V to V ±V

REF

NOTES

Output code format is straight binary.

Range is ±V

Note that the AIN(–) pin on the AD7851 can be biased up above AGND in the unipolar mode also, if required. The advantage of biasing the lower end of the analog input range away from AGND is that the user does not have to have the analog input swing all the way down to AGND. This has the advantage in true single supply applications that the input amplifier does not have to swing all the way down to AGND. The upper end of the analog input range is shifted up by the same amount. Care must be taken so that the bias applied does not shift the upper end of the analog input above the AV where the reference is the supply, AV

supply. In the case

, the AIN(–) must be

tied to AGND in unipolar mode.

4.096 V/16384 = 0.25 mV when V

= 4.096 V. The ideal in-

REF

put/output transfer characteristic for the unipolar range is shown in Figure 16.

Figure 16. AD7851 Unipolar Transfer Characteristic

Figure 15 shows the AD7851’s ± V

/2 bipolar analog input

REF

configuration (where AIN(+) cannot go below 0 V so for the full bipolar range then the AIN(–) pin should be biased to +V

REF

/2). Once again the designed code transitions occur midway between successive integer LSB values. The output coding is 2s complement with 1 LSB = 16384 = 4.096 V/16384 = 0.25 mV. The ideal input/output transfer characteristic is shown in Figure 17.

TRACK AND HOLD

AMPLIFIER

DOUT

AD7851

Unipolar Input Configuration

REF

STRAIGHT BINARY FORMAT

= 0 TO V

REF

UNIPOLAR

ANALOG

INPUT RANGE

SELECTED

Figure 14. 0 V to V

AIN(+)

AIN(–)

AMODE

Transfer Functions

For the unipolar range the designed code transitions occur midway between successive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs . . . FS –3/2 LSBs). The output coding is straight binary for the unipolar range with 1 LSB = FS/16384 =

TRACK AND HOLD

AMPLIFIER

DOUT

2S COMPLEMENT FORMAT

AD7851

/2 Bipolar Input Configuration

REF

= 0 TO V

REF

UNIPOLAR

ANALOG

INPUT RANGE

SELECTED

Figure 15.±V

AIN(+)

AIN(–)

AMODE

/2 about V

–16–

Figure 17. AD7851 Bipolar Transfer Characteristic

REV. A

AD7851

REFERENCE SECTION

For specified performance, it is recommended that when using an external reference this reference should be between 4 V and the analog supply AV

. The connections for the relevant refer-

ence pins are shown in the typical connection diagrams. If the internal reference is being used, the REF

/REF

pin should

OUT

have a 100 nF capacitor connected to AGND very close to the REF

/REF

pin. These connections are shown in Figure 18.

OUT

If the internal reference is required for use external to the ADC, it should be buffered at the REF

/REF

pin and a 100 nF

OUT

connected from this pin to AGND. The typical noise performance for the internal reference, with 5 V supplies is 150 nV/√

Hz @

1 kHz and dc noise is 100 µV p-p.

0.01µF

OUT

10Ω

AD7851

0.1µF

ANALOG

SUPPLY

+5V

0.01µF

0.01µF 47nF

10µF

470nF

0.1µF

REF1

REF2

REFIN/REF

AD7851 PERFORMANCE CURVES

Figure 20 shows a typical FFT plot for the AD7851 at 333 kHz sample rate and 10 kHz input frequency.

–20

–40

–60

SNR – dB

–80

–100

–120

0 10020

40 60 80

FREQUENCY – kHz

AVDD = DVDD = 5V

= 333 kHz

SAMPLE

= 10kHz

SNR = 79.5dB THD = –95.2

Figure 20. FFT Plot

Figure 21 shows the SNR versus Frequency for 5 V supply and a 4.096 external references (5 V reference is typically 1dB better performance).

Figure 18. Relevant Connections When Using Internal Reference

The other option is that the REFIN/REF

pin be overdriven

OUT

by connecting it to an external reference. This is possible due to the series resistance from the REF

/REF

pin to the internal

OUT

reference. This external reference can have a range that includes AV

. When using AVDD as the reference source, the 100 nF

capacitor from the REF close as possible to the REF

/REF

pin to AGND should be as

OUT

/REF

pin, and also the C

OUT

REF1

pin should be connected to AVDD to keep this pin at the same level as the reference. The connections for this arrangement are shown in Figure 19. When using AV add a resistor in series with the AV effect of filtering the noise associated with the AV

ANALOG

SUPPLY

+5V

10µF

10Ω

0.01µF

0.01µF 47nF

it may be necessary to

supply. This will have the

470nF

0.1µF

REF1

REF2

REFIN/REF

10Ω

AD7851

OUT

supply.

0.1µF

S(N+D) RATIO – dB

10 80 100

0 16620 50 120 140

INPUT FREQUENCY – kHz

Figure 21. SNR vs. Frequency

Figure 22 shows the Power Supply Rejection Ratio versus Frequency for the part. The Power Supply Rejection Ratio is defined as the ratio of the power in ADC output at frequency f to the power of a full-scale sine wave.

PSRR (dB) = 10 log (Pf/Pfs)

Pf = Power at frequency f in ADC output, Pfs = power of a full-

scale sine wave. Here a 100 mV peak-to-peak sine wave is coupled onto the AV

supply while the digital supply is left

unaltered.

Figure 19. Relevant Connections When Using AVDD as the Reference

REV. A

–17–

AD7851

–72

= DVDD = 5.0V

–74

100mV pk-pk SINEWAVE ON AV

REFIN = 4.098 EXT REFERENCE

–76

–78

–80

–82

PSRR – dB

–84

–86

–88

–90

0.91 10013.4 25.7 38.3 50.3 INPUT FREQUENCY – kHz

63.5 74.8 87.4

Figure 22. PSRR vs. Frequency

POWER-DOWN OPTIONS

The AD7851 provides flexible power management to allow the user to achieve the best power performance for a given throughput rate. The power management options are selected by programming the power management bits, PMGT1 and PMGT0, in the control register and by use of the

SLEEP pin. Table VI summarizes the power-down options that are available and how they can be selected by using either software, hardware or a combination of both. The AD7851 can be fully or partially powered down. When fully powered down, all the on-chip circuitry is powered down and I

is 1 µA typ. If a partial power-down is

selected, then all the on-chip circuitry except the reference is powered down and I

is 400 µA typ. The choice of full or par-

tial power-down does not give any significant improvement in throughput with a power-down between conversions. This is discussed in the next section—Power-Up Times. But a partial power-down does allow the on-chip reference to be used externally even though the rest of the AD7851 circuitry is powered down. It also allows the AD7851 to be powered up faster after

a long power-down period when using the on-chip reference (See Power-Up Times—Using On-Chip Reference).

When using the

SLEEP pin, the power management bits PMGT1 and PMGT0 should be set to zero (default status on power-up). Bringing the

SLEEP pin logic high ensures normal operation, and the part does not power down at any stage. This may be necessary if the part is being used at high throughput rates when it is not possible to power down between conversions. If the user wishes to power down between conversions at lower throughput rates (i.e., <100 kSPS for the AD7851) to achieve better power performances, then the

SLEEP pin should

be tied logic low. If the power-down options are to be selected in software only,

then the

SLEEP pin should be tied logic high. By setting the power management bits PMGT1 and PMGT0 as shown in Table VI, a Full Power-Down, Full Power-Up, Full PowerDown Between Conversions, and a Partial Power-Down Between Conversions can be selected.

A combination of hardware and software selection can also be used to achieve the desired effect.

Table VI. Power Management Options

PMGT1 PMGT0 SLEEP Bit Bit Pin Comment

0 0 0 Full Power-Down Between

Conversions (HW/SW)

0 0 1 Full Power-Up (HW/SW) 0 1 X Full Power-Down Between

Conversions (SW)

1 0 X Full Power-Down (SW) 1 1 X Partial Power-Down Between

Conversions (SW)

NOTE SW = Software selection, HW = Hardware selection.

ANALOG

(+5V)

SUPPLY

0V TO V

REF

INPUT

AUTO POWER-

DOWN AFTER CONVERSION

AUTO CAL ON

POWER-UP

CURRENT, I = 12mA TYP

UNIPOLAR RANGE

0.01µF

47nF

0.01µF

OPTIONAL

EXTERNAL

REFERENCE

470nF

0.01µF

10µF

0.01µF 0.1µF

AVDDDV

AIN(+)

AIN(–)

AMODE

REF1

REF2

SLEEP

POLARITY

CAL

AGND

DGND

REF198

AD7851

/REF

REF

OUT

0.01µF

CLKIN

SCLK

CONVST

SYNC

DOUT

DIN

SM1 SM2

INTERNAL REFERENCE

SERIAL CLOCK OUTPUT

SERIAL DATA OUTPUT

Figure 23. Typical Low Power Circuit

–18–

6/7MHz

OSCILLATOR

MASTER

CLOCK

INPUT

285/333kHz PULSE

GENERATOR

CONVERSION

START INPUT

DIN AT DGND => NO WRITING TO DEVICE

SERIAL MODE SELECTION BITS

3-WIRE MODE

SELECTED

LOW POWER

µC/µP

REV. A

AD7851

POWER-UP TIMES Using An External Reference

When the AD7851 are powered up, the parts are powered up from one of two conditions. First, when the power supplies are initially powered up and, secondly, when the parts are powered up from either a hardware or software power-down (see last section).

When AV

and DVDD are powered up, the AD7851 enters a

mode whereby the CONVST signal initiates a timeout followed by a self-calibration. The total time taken for this time-out and calibration is approximately 35 ms—see Calibration on Power-Up in the calibration section of this data sheet. During power-up the functionality of the not power down until the end of the calibration if

SLEEP pin is disabled, i.e., the part will

SLEEP is tied

logic low. The power-up calibration mode can be disabled if the user writes to the control register before a

CONVST signal is applied. If the time out and self-calibration are disabled, then the user must take into account the time required by the AD7851 to power up before a self-calibration is carried out. This power-up time is the time taken for the AD7851 to power up when power is first applied (300 µs typ) or the time it takes the external reference to settle to the 14-bit level—whichever is the longer.

The AD7851 powers up from a full hardware or software power-down in 5 µs typ. This limits the throughput which the part is capable of to 120 kSPS for the K Grade and 126kSPS for the A Grade when powering down between conversions. Figure 24 shows how power-down between conversions is implemented using the power-down between conversions option by using the

CONVST pin. The user first selects the

SLEEP

pin and the power management bits, PMGT1 and PMGT0, in the control register. See last section. In this mode the AD7851 automatically enters a full power-down at the end of a conversion, i.e., when BUSY goes low. The falling edge of the next CONVST pulse causes the part to power up. Assuming the external reference is left powered up, the AD7851 should be ready for normal operation 5 µs after this falling edge. The rising edge of

CONVST initiates a conversion so the CONVST pulse should be at least 5 µs wide. The part automatically powers down on completion of the conversion. Where the software convert start is used, the part may be powered up in software before a conversion is initiated.

START CONVERSION ON RISING EDGE

POWER-UP ON FALLING EDGE

5µs 3.25µs

CONVST

BUSY

POWER-UP

TIME

CONVERT

NORMAL

OPERATION

FULL

POWER-DOWN

POWER-UP

TIME

Figure 24. Using the CONVST Pin to Power Up the AD7851 for a Conversion

Using The Internal (On-Chip) Reference

As in the case of an external reference, the AD7851 can power up from one of two conditions, power-up after the supplies are connected or power-up from hardware/software power-down.

When using the on-chip reference and powering up when AV

and DVDD are first connected, it is recommended that the power-up calibration mode be disabled as explained above. When using the on-chip reference, the power-up time is effectively the time it takes to charge up the external capacitor on the REF

/REF

pin. This time is given by the equation:

OUT

= 9 × R × C

where R ≈ 150K and C = external capacitor. The recommended value of the external capacitor is 100nF;

this gives a power-up time of approximately 135ms before a calibration is initiated and normal operation should commence.

When C

is fully charged, the power-up time from a hardware

REF

or software power-down reduces to 5µs. This is because an internal switch opens to provide a high impedance discharge path for the reference capacitor during power-down—see Figure

25. An added advantage of the low charge leakage from the reference capacitor during power-down is that even though the reference is being powered down between conversions, the reference capacitor holds the reference voltage to within 0.5LSBs with throughput rates of 100 samples/second and over with a full power-down between conversions. A high input impedance op amp like the AD707 should be used to buffer this reference capacitor if it is being used externally. Note, if the AD7851 is left in its powered-down state for more than 100ms, the charge on C

will start to leak away and the power-up time will

REF

increase. If this long power-up time is a problem, the user can use a partial power-down for the last conversion so the reference remains powered up.

REFIN/REF

EXTERNAL

CAPACITOR

SWITCH OPENS

DURING POWER-DOWN

OUT

BUF

AD7851

ON-CHIP

REFERENCE

TO OTHER CIRCUITRY

Figure 25. On-Chip Reference During Power-Down

POWER VS. THROUGHPUT RATE

The main advantage of a full power-down after a conversion is that it significantly reduces the power consumption of the part at lower throughput rates. When using this mode of operation, the AD7851 is only powered up for the duration of the conversion. If the power-up time of the AD7851 is taken to be 5µs and it is assumed that the current during power up is 12mA typ, then power consumption as a function of throughput can easily be calculated. The AD7851 has a conversion time of

3.25 µs with a 6 MHz external clock. This means the AD7851 consumes 12 mA typ for 8.25 µs in every conversion cycle if the parts are powered down at the end of a conversion. The graph, Figure 26, shows the power consumption of the AD7851 as a function of throughput. Table VII lists the power consumption for various throughput rates.

REV. A

–19–

AD7851

Table VII. Power Consumption vs. Throughput

Power

Throughput Rate AD7851

1 kSPS 9 mW 2 kSPS 18mW

100

POWER – mW

0.1

0.01 0 20002001400 600 800 1000 1200 1400 1600 1800

Figure 26. Power vs. Throughput AD7851

THROUGHPUT RATE – Hz

NOTE When setting the power-down mode by writing to the part, it is recommended to be operating in an interface mode other than Interface Modes 4, and 5. This way the user has more control to initiate power-down, and power-up commands.

CALIBRATION SECTION Calibration Overview

The automatic calibration that is performed on power-up ensures that the calibration options covered in this section will not be required in a significant amount of applications. The user will not have to initiate a calibration unless the operating conditions change (CLKIN frequency, analog input mode, reference voltage, temperature, and supply voltages). The AD7851 have a number of calibration features that may be required in some applications and there are a number of advantages in performing these different types of calibration. First, the internal errors in the ADC can be reduced significantly to give superior dc performance; and second, system offset and gain errors can be removed. This allows the user to remove reference errors (whether it be internal or external reference) and to make use of the full dynamic range of the AD7851 by adjusting the analog input range of the part for a specific system.

There are two main calibration modes on the AD7851, self-calibration and system calibration. There are various options in both self-calibration and system calibration as outlined previously in Table III. All the calibration functions can be initiated by pulsing the

CAL pin or by writing to the control register and setting the STCAL bit to 1. The timing diagrams that follow involve using the

CAL pin.

The duration of each of the different types of calibrations is given in Table VIII for the AD7851 with a 6 MHz/7 MHz master clock. These calibration times are master clock dependent.

Table VIII. Calibration Times (AD7851 with 6 MHz CLKIN)

Type of Self- or System Calibration Time

Full 41.7 ms Gain + Offset 9.26 ms Offset 4.63 ms Gain 4.63 ms

Automatic Calibration on Power-On

The CAL pin has a 0.15 µA pull-up current source connected to it internally to allow for an automatic full self-calibration on power-on. A full self-calibration will be initiated on power-on if a 10 nF capacitor is connected from the The internal current source connected to the

CAL pin to AGND.

CAL pin charges

up the external capacitor and the time required to charge the external capacitor will be 100 ms approximately. This time is large enough to ensure that the internal reference is settled before the calibration is performed. However, if an external reference is being used, this reference must have stabilized before the automatic calibration is initiated (if larger time than 100 ms is required then a larger capacitor on the

CAL pin should be used). After this 100 ms has elapsed, the calibration will be performed which will take 42 ms/36 ms (6 MHz /7 MHz CLKIN). Therefore 142 ms/136 ms should be allowed before operating the part. After calibration, the part is accurate to the 14-bit level and the specifications quoted on the data sheet apply. There will be no need to perform another calibration unless the operating conditions change or unless a system calibration is required.

Self-Calibration Description

There are a four different calibration options within the selfcalibration mode. There is a full self-calibration where the DAC, internal offset, and internal gain errors are calibrated out. Then, there is the (Gain + Offset) self-calibration which calibrates out the internal gain error and then the internal offset errors. The internal DAC is not calibrated here. Finally, there are the self-offset and self-gain calibrations which calibrate out the internal offset errors and the internal gain errors respectively.

The internal capacitor DAC is calibrated by trimming each of the capacitors in the DAC. It is the ratio of these capacitors to each other that is critical, and so the calibration algorithm ensures that this ratio is at a specific value by the end of the calibration routine. For the offset and gain there are two separate capacitors, one of which is trimmed when an offset or gain calibration is performed. Again it is the ratio of these capacitors to the capacitors in the DAC that is critical and the calibration algorithm ensures that this ratio is at a specified value for both the offset and gain calibrations.

In bipolar mode the midscale error is adjusted for an offset calibration and the positive full-scale error is adjusted for the gain calibration; in unipolar mode the zero-scale error is adjusted for an offset calibration and the positive full-scale error is adjusted for a gain calibration.

–20–

REV. A

AD7851

SYSTEM OFFSET

CALIBRATION

FOLLOWED BY

SYSTEM GAIN CALIBRATION

SYS OFFSET

REF

– 1LSB

AGND

MAX SYSTEM OFFSET

IS ±5% OF V

REF

MAX SYSTEM FULL SCALE

IS ±2.5% FROM V

REF

ANALOG INPUT RANGE

REF

– 1LSB

ANALOG INPUT RANGE

SYS OFFSET

AGND

MAX SYSTEM OFFSET

IS ±5% OF V

REF

+ SYS OFFSET

SYS F.S.

MAX SYSTEM FULL SCALE

IS ±2.5% FROM V

REF

SYS F.S.

Self-Calibration Timing

The diagram of Figure 27 shows the timing for a full selfcalibration. Here the BUSY line stays high for the full length of the self-calibration. A self-calibration is initiated by bringing the CAL pin low (which initiates an internal reset) and then high again or by writing to the control register and setting the STCAL bit to 1 (note that if the part is in a power-down mode, the CAL pulse width must take account of the power-up time). The BUSY line is triggered high from the rising edge of end of the write to the control register if calibration is initiated in software), and BUSY will go low when the full self-calibration is complete after a time t

For the self-(gain + offset), self-offset and self-gain calibrations, the BUSY line will be triggered high by the rising edge of the CAL signal (or the end of the write to the control register if calibration is initiated in software) and will stay high for the full duration of the self-calibration. The length of time that the BUSY is high for will depend on the type of self-calibration that is initiated. Typical figures are given in Table IX. The timing diagrams for the other self-calibration options will be similar to that outlined in Figure 27.

System Calibration Description

System calibration allows the user to take out system errors external to the AD7851 as well as calibrate the errors of the AD7851 itself. The maximum calibration range for the system offset errors is ±5% of V ±2.5% of V offset voltage applied between the AIN(+) and AIN(–) pins for the calibration to adjust out this error is ±0.05 × V

AIN(+) can be 0.05 × V AIN(–)). For the system gain error the maximum allowable

system full-scale voltage, in unipolar mode, that can be applied between AIN(+) and AIN(–) for the calibration to adjust out this error is V

0.025 × V AIN(–)). If the system offset or system gain errors are outside the ranges mentioned, the system calibration algorithm will reduce the errors as much as the trim range allows.

Figures 28 through 30 illustrate why a specific type of system calibration might be used. Figure 29 shows a system offset calibration (assuming a positive offset) where the analog input range has been shifted upwards by the system offset after the system offset calibration is completed. A negative offset may also be accounted for by a system offset calibration.

REV. A

CAL (or the

as shown in Figure 27.

CAL

= 100ns MIN,

= 2.5

CLKIN

= 250026

CAL

MAX,

CLKIN

CAL (I/P)

BUSY (O/P)

CAL

Figure 27. Timing Diagram for Full Self-Calibration

and for the system gain errors is

REF

above AIN(–) or 0.05 × V

REF

(i.e., the AIN(+) can be V

REF

– 0.025 × V

REF

(i.e., the

below

REF

above

. This means that the maximum allowable system

REF

± 0.025 × V

REF

above AIN(–) or V

REF

MAX SYSTEM FULL SCALE

IS ±2.5% FROM V

+ SYS OFFSET

– 1LSB

REF

SYS OFFSET

AGND

MAX SYSTEM OFFSET

IS ±5% OF V

ANALOG INPUT RANGE

REF

SYSTEM OFFSET

CALIBRATION

– 1LSB

REF

SYS OFFSET

AGND

MAX SYSTEM OFFSET

IS ±5% OF V

Figure 28. System Offset Calibration

Figure 29 shows a system gain calibration (assuming a system full scale greater than the reference voltage) where the analog input range has been increased after the system gain calibration is completed. A system full-scale voltage less than the reference voltage may also be accounted for a by a system gain calibration.

MAX SYSTEM FULL SCALE

IS ±2.5% FROM V

– 1LSB

REF

ANALOG INPUT RANGE

AGND

REF

SYSTEM GAIN

CALIBRATION

MAX SYSTEM FULL SCALE

IS ±2.5% FROM V

SYS FULL S.SYS FULL S.

– 1LSB

REF

AGND

Figure 29. System Gain Calibration

Finally in Figure 30 both the system offset and gain are accounted for by the system offset followed by a system gain calibration. First the analog input range is shifted upwards by the positive system offset and then the analog input range is adjusted at the top end to account for the system full scale.

Figure 30. System (Gain + Offset) Calibration

–21–

REF

ANALOG INPUT RANGE

REF

ANALOG INPUT RANGE

AD7851

CONVST (I/P)

AIN (I/P)

SETUP

CAL (I/P)

BUSY (O/P)

CAL1

CAL2

SYSTEM FULL SCALE

OFFSET

= 100ns MIN, t14 = 50 MAX,

= 4 t

CLKIN

MAX, t

CAL1

= 222228 t

CLKIN

MAX,

CAL2

= 27798 t

CLKIN

System Gain and Offset Interaction

The inherent architecture of the AD7851 leads to an interaction between the system offset and gain errors when a system calibration is performed. Therefore it is recommended to perform the cycle of a system offset calibration followed by a system gain calibration twice. Separate system offset and system gain calibrations reduce the offset and gain errors to at least the 14-bit level. By performing a system offset calibration first and a system gain calibration second, priority is given to reducing the gain error to zero before reducing the offset error to zero. If the system errors are small, a system offset calibration would be performed, followed by a system gain calibration. If the systems errors are large (close to the specified limits of the calibration range), this cycle would be repeated twice to ensure that the offset and gain errors were reduced to at least the 14-bit level. The advantage of doing separate system offset and system gain calibrations is that the user has more control over when the analog inputs need to be at the required levels, and the

CONVST sig-

nal does not have to be used. Alternatively, a system (gain + offset) calibration can be per-

formed. It is recommended to perform three system (gain + offset) calibrations to reduce the offset and gain errors to the 14-bit level. For the system (gain + offset) calibration priority is given to reducing the offset error to zero before reducing the gain error to zero. Thus if the system errors are small then two system (gain + offset) calibrations will be sufficient. If the system errors are large (close to the specified limits of the calibration range), three system (gain + offset) calibrations may be required to reduced the offset and gain errors to at least the 14-bit level. There will never be any need to perform more than three system (offset + gain) calibrations.

In Bipolar Mode the midscale error is adjusted for an offset calibration and the positive full-scale error is adjusted for the gain calibration; in Unipolar Mode the zero-scale error is adjusted for an offset calibration and the positive full-scale error is adjusted for a gain calibration.

System Calibration Timing

The calibration timing diagram in Figure 31 is for a full system calibration where the falling edge of

CAL initiates an internal

reset before starting a calibration (note that if the part is in power-

down mode the

CAL pulse width must take account of the power-up

time). If a full system calibration is to be performed in software,

it is easier to perform separate gain and offset calibrations so that the CONVST bit in the control register does not have to be programmed in the middle of the system calibration sequence. The rising edge of

CAL starts calibration of the internal DAC and causes the BUSY line to go high. If the control register is set for a full system calibration, the

CONVST must be used also. The full-scale system voltage should be applied to the analog input pins from the start of calibration. The BUSY line will go low once the DAC and system gain calibration are complete.

Next the system offset voltage is applied to the AIN pin for a minimum setup time (t the

CONVST and remain until the BUSY signal goes low. The

rising edge of the

CONVST starts the system offset calibration

) of 100 ns before the rising edge of

SETUP

section of the full system calibration and also causes the BUSY signal to go high. The BUSY signal will go low after a time t

CAL2

when the calibration sequence is complete. The timing for a system (gain + offset) calibration is very similar

to that of Figure 31, the only difference being that the time t

will be replaced by a shorter time of the order of t

CAL1

CAL2

as the internal DAC will not be calibrated. The BUSY signal will signify when the gain calibration is finished and when the part is ready for the offset calibration.

Figure 31. Timing Diagram for Full System Calibration

The timing diagram for a system offset or system gain calibration is shown in Figure 32. Here again the the rising edge of the

CAL initiates the calibration sequence (or

CAL is pulsed and

the calibration can be initiated in software by writing to the control register). The rising edge of the

CAL causes the BUSY line to go high and it will stay high until the calibration sequence is finished. The analog input should be set at the correct level for a minimum setup time (t of

CAL and stay at the correct level until the BUSY signal goes

) of 100 ns before the rising edge

SETUP

low.

CAL (I/P)

BUSY (O/P)

CAL2

OR V

SYSTEM OFFSET

AIN (I/P)

SETUP

SYSTEM FULL SCALE

Figure 32. Timing Diagram for System Gain or System Offset Calibration

–22–

REV. A

AD7851

SERIAL INTERFACE SUMMARY

Table IX details the five interface modes and the serial clock edges from which the data is clocked out by the AD7851 (DOUT Edge) and that the data is latched in on (DIN Edge). The logic level of the POLARITY pin is shown and it is clear that this reverses the edges.

In Interface Modes 4 and 5 the first data bit and SCLK will clock out the subsequent bits.

In Interface Modes 1, 2, and 3 the SCLK and the POLARITY pin. Thus the the MSB of data. Subsequent bits will be clocked out by the serial clock, SCLK. The conditions for the the MSB of data is as follows:

With the POLARITY pin high the falling edge of out the MSB if the serial clock is low when the

With the POLARITY pin low the falling edge of out the MSB if the serial clock is high when the

Table IX. SCLK Active Edge for Different Interface Modes

Interface POLARITY DOUT DIN Mode Pin Edge Edge

1, 2, 3 0 SCLK ↑ SCLK ↓

1 SCLK ↓ SCLK ↑

4, 5 0 SCLK ↓ SCLK ↑

1 SCLK ↑ SCLK ↓

Resetting the Serial Interface

When writing to the part via the DIN line there is the possibility of writing data into the incorrect registers, such as the test register for instance, or writing the incorrect data and corrupting the serial interface. The SYNC pin high resets the internal shift register. The first data bit after the next new 16-bit transfer. It is also possible that the test register contents were altered when the interface was lost. Therefore, once the serial interface is reset, it may be necessary to write the 16bit word 0100 0000 0000 0010 to restore the test register to its default value. Now the part and serial interface are completely reset. It is always useful to retain the ability to program the SYNC line from a port of the µController/DSP to have the abil- ity to reset the serial interface.

Table X summarizes the interface modes provided by the AD7851. It also outlines the various µP/µC to which the par- ticular interface is suited.

The interface mode is determined by the serial mode selection pins SM1 and SM2. Interface mode 2 is the default mode. Note that Interface Mode 1 and 2 have the same combination of SM1

SYNC pin acts as a reset. Bringing the

SYNC falling edge will now be the first bit of a

SYNC always clocks out the

SYNC is gated with the

SYNC may clock out

SYNC clocking out

SYNC will clock

SYNC goes low.

SYNC will clock

SYNC goes low.

and SM2. Interface Mode 1 may only be set by programming the control register (see section on control register). External SCLK and required for Interfaces Modes 1, 2, and 3. In Interface Modes 4 and 5 the AD7851 generates the SCLK and

Some of the more popular µProcessors, µControllers, and the DSP machines that the AD7851 will interface to directly are mentioned here. This does not cover all µCs, µPs and DSPs. The interface mode of the AD7851 that is mentioned here for a specific µC, µP, or DSP is only a guide and in most cases an- other interface mode may work just as well.

A more detailed timing description on each of the interface modes follows.

SM1 SM2 mProcessor/ Interface Pin Pin mController Mode

0 0 8XC51 1 (2-Wire)

0 0 68HC11 2 (3-Wire, SPI/QSPI)

0 1 68HC16 3 (QSPI)

1 0 68HC16 4 (DSP is Slave)

1 1 ADSP-21xx 5 (DSP is Slave)

SYNC signals (SYNC may be hardwired low) are

SYNC.

Table X. Interface Mode Description

8XL51 (DIN is an Input/ PIC17C42 Output pin)

68L11 (Default Mode)

PIC16C64 (External Serial ADSP-21xx Clock, SCLK, and DSP56000 External Frame Sync, DSP56001 DSP56002 DSP56L002 TMS320C30

DSP56000 (AD7851 DSP56001 generates a DSP56002 continuous Serial DSP56L002 Clock, SCLK, and the TMS320C20 Frame Sync, TMS320C25 TMS320C30 TMS320C5X TMS320LC5X

SYNC, are required)

(AD7851 generates a noncontinuous (16 clocks) Serial Clock, SCLK, and the Frame Sync, SYNC)

SYNC)

REV. A

–23–

AD7851

DETAILED TIMING SECTION MODE 1 (2-Wire 8051 Interface)

The read and writing takes place on the DIN line and the conversion is initiated by pulsing the every write cycle the 2/

3 MODE bit must be set to 1). The con-

CONVST pin (note that in

version may be started by setting the CONVST bit in the control register to 1 instead of using the

CONVST line.

Below in Figure 33 and in Figure 34 are the timing diagrams for Interface Mode 1 in Table XI where we are in the 2-wire interface mode. Here the DIN pin is used for both input and output as shown. The

SYNC input is level triggered active low and can

be pulsed (Figure 33) or can be constantly low (Figure 34). In Figure 33 the part samples the input data on the rising edge

of SCLK. After the 16th rising edge of SCLK the DIN is configured as an output. When the 3-stated. Taking

SYNC low disables the 3-state on the DIN pin

SYNC is taken high the DIN is

and the first SCLK falling edge clocks out the first data bit. Once the 16 clocks have been provided the DIN pin will automatically revert back to an input after a time t

t3 = –0.4 t

= 45 MAX, t7 = 30ns MIN, t8 = 20 MIN

116 161

DB15 DB0DB0 DB15

SYNC (I/P)

SCLK (I/P)

DIN (I/O)

POLARITY PIN LOGIC HIGH

SCLK

DATA WRITE

. Note that a

MIN (NONCONTINUOUS SCLK) –/+0.4 t

DIN BECOMES AN OUTPUT

continuous SCLK shown by the dotted waveform in Figure 33 can be used provided that the

SYNC is low for only 16 clock pulses in each of the read and write cycles. The POLARITY pin may be used to change the SCLK edge which the data is sampled on and clocked out on.

In Figure 34 the sults in a different timing arrangement. With

SYNC line is tied low permanently and this re-

SYNC tied low

permanently the DIN pin will never be 3-stated. The 16th rising edge of SCLK configures the DIN pin as an input or an output as shown in the diagram. Here no more than 16 SCLK pulses must occur for each of the read and write operations.

If reading from and writing to the calibration registers in this interface mode, all the selected calibration registers must be read from or written to. The read and write operations cannot be aborted. When reading from the calibration registers, the DIN pin will remain as an output for the full duration of all the calibration register read operations. When writing to the calibration registers, the DIN pin will remain as an input for the full duration of all the calibration register write operations.

MIN/MAX (CONTINUOUS SCLK),

SCLK

3-STATE

DATA READ

DIN BECOMES AN INPUT

Figure 33. Timing Diagram for Read/Write Operation with DIN as an Input/Output (i.e., Interface Mode 1, SM1 = SM2 = 0)

t6 = 45 MAX, t7 = 30ns MIN, t8 = 20 MIN,

= 90 MAX, t

116 161

DB15 DB0DB0 DB15

DATA WRITE

SCLK (I/P)

DIN (I/O)

POLARITY PIN LOGIC HIGH

Figure 34. Timing Diagram for Read/Write Operation with DIN as an Input/Output and

= 50ns MAX

DATA READ

DIN BECOMES AN INPUT

SYNC

Input Tied Low

(i.e., Interface Mode 1, SM1 = SM2 = 0)

–24–

REV. A

AD7851

MODE 2 (3-Wire SPI/QSPI Interface Mode) This is the DEFAULT INTERFACE MODE.

In Figure 35 below we have the timing diagram for Interface Mode 2 which is the SPI/QSPI interface mode. Here the

SYNC

input is active low and may be pulsed or tied permanently low. If

SYNC is permanently low 16 clock pulses must be applied to the SCLK pin for the part to operate correctly, and with a pulsed

SYNC input a continuous SCLK may be applied pro-

vided

SYNC is low for only 16 SCLK cycles. In Figure 35 the

SYNC going low disables the three-state on the DOUT pin.

The first falling edge of the SCLK after the

SYNC going low clocks out the first leading zero on the DOUT pin. The DOUT pin is 3-stated again a time t the DIN pin the data input has to be set up a time t

after the SYNC goes high. With

before the

SCLK rising edge as the part samples the input data on the SCLK rising edge in this case. The POLARITY pin may be used to change the SCLK edge which the data is sampled on and clocked out on. If resetting the interface is required, the SYNC must be taken high and then low.

SYNC (I/P)

SCLK (I/P)

DOUT (O/P)

DIN (I/P)

POLARITY PIN LOGIC HIGH

3-STATE

t3 = –0.4 t

= 45 MAX, t7 = 30ns MIN, t8 = 20 MIN, t

30/0.4 t

162345

MIN (NONCONTINUOUS SCLK) –/+0.4 t

CLKIN

= ns MIN/MAX (CONTINUOUS SCLK)

SCLK

DB12

MODE 3 (QSPI Interface Mode)

Figure 36 shows the timing diagram for Interface Mode 3. In this mode the DSP is the master and the part is the slave. Here the

SYNC input is edge triggered from high to low, and the 16 clock pulses are counted from this edge. Since the clock pulses are counted internally then the

SYNC signal does not have to go high after the 16th SCLK rising edge as shown by the dotted SYNC line in Figure 36. Thus a frame sync that gives a high pulse, of one SCLK cycle minimum duration, at the beginning of the read/write operation may be used. The rising edge of SYNC enables the 3-state on the DOUT pin. The falling edge of

SYNC disables the 3-state on the DOUT pin, and data is

clocked out on the falling edge of SCLK. Once

SYNC goes high, the 3-state on the DOUT pin is enabled. The data input is sampled on the rising edge of SCLK and thus has to be valid a time t

before this rising edge. The POLARITY pin may be

used to change the SCLK edge which the data is sampled on and clocked out on. If resetting the interface is required, the SYNC must be taken high and then low.

MIN/MAX (CONTINUOUS SCLK),

= 30 MIN (NONCONTINUOUS SCLK) ,

DB12DB13DB14DB15 DB11

SCLK

DB0DB10

DB10DB11DB13DB14DB15

DB0

3-STATE

Figure 35. SPI/QSPI Mode 2 Timing Diagram for Read/Write Operation with DIN Input, DOUT Output and (SM1 = SM2 = 0)

t3 = –0.4 t

= 45 MAX, t7 = 30ns MIN, t8 = 20 MIN, t

162345

SYNC (I/P)

SCLK (I/P)

DOUT (O/P)

DIN (I/P)

POLARITY PIN LOGIC HIGH

3-STATE

Figure 36. QSPI Mode 3 Timing Diagram for Read/Write Operation with

MIN (NONCONTINUOUS SCLK) –/+0.4 t

CLKIN

= 30 MIN

DB12DB13DB14DB15 DB11

DB12

MIN/MAX (CONTINUOUS SCLK),

SCLK

DB10DB11DB13DB14DB15

SYNC

Input Edge Triggered (SM1 = 0, SM2 = 1)

DB0

3-STATE

DB0DB10

SYNC

Input

REV. A

–25–

AD7851

CONVST

(I/P)

SCLK

(O/P)

CONVERSION ENDS

3.25µs LATER

SERIAL READ

AND WRITE

OPERATIONS

OUTPUT SERIAL SHIFT

READ OPERATION

SHOULD END 500ns

PRIOR TO NEXT RISING

400ns MIN

BUSY

(O/P)

SYNC

(O/P)

CONVERSION IS INITIATED

AND TRACK/HOLD GOES

INTO HOLD

EDGE OF CONVST

= 100ns MIN

CONVERT

= 3.25µs

MODE 4 and 5 (Self-Clocking Modes)

The timing diagrams in Figure 38 and Figure 39 are for Interface Modes 4 and 5. Interface Mode 4 has a noncontinuous SCLK output and Interface Mode 5 has a continuous SCLK output (SCLK is switched off internally during calibration for both Modes 4 and 5). These modes of operation are especially different to all the other modes since the SCLK and outputs. The

SYNC is generated by the part as is the SCLK.

SYNC are

The master clock at the CLKIN pin is routed directly to the SCLK pin for Interface Mode 5 (Continuous SCLK) and the CLKIN signal is gated with the

SYNC to give the SCLK

(noncontinuous) for Interface Mode 4. The most important point about these two modes of operation

mode is that the result of the current conversion is clocked out during the same conversion and a write to the part during this conversion is for the next conversion. The arrangement is shown in Figure

37. Figure 38 and Figure 39 show more detailed timing for the arrangement of Figure 37.

THE CONVERSION RESULT DUE TO

WRITE N+1 IS READ HERE

WRITE N+1

READ N

CONVERSION N CONVERSION N+1 CONVERSION N+2

3.25µs

WRITE N+2

READ N+1

3.25µs 3.25µs

WRITE N+3

READ N+2

Figure 37.

In Figure 38 the first point to note is that the BUSY, SYNC, and SCLK are all outputs from the AD7851 with the

CONVST

being the only input signal. Conversion is initiated with the CONVST signal going low. This CONVST falling edge also triggers the BUSY to go high. The triggers the

3.5 t

SYNC to go low after a short delay (2.5 t

typically) after which the SCLK will clock out the

CLKIN

CONVST signal rising edge

CLKIN

data on the DOUT pin during conversion. The data on the DIN pin is also clocked in to the AD7851 by the same SCLK for the next conversion. The read/write operations must be complete after sixteen clock cycles (which takes 3.25 µs approximately from

the rising edge of

time the conversion will be complete, the

CONVST assuming a 6 MHz CLKIN). At this

SYNC will go high,

and the BUSY will go low. The next falling edge of the CONVST must occur at least 330 ns after the falling edge of BUSY to allow the track/hold amplifier adequate acquisition time as shown in Figure 38. This gives a throughput time of

3.68 µs. The maximum throughput rate in this case is 272 kHz.

Figure 38. Mode 4, 5 Timing Diagram (SM1 = 1, SM2 = 1 and 0)

In these interface modes the part is now the master and the DSP is the slave. Figure 39 is an expansion of Figure 38. The AD7851 will ensure

SYNC goes low after the rising edge C of the continuous SCLK (Interface Mode 5) in Figure 39. Only in the case of a noncontinuous SCLK (Interface Mode 4) will the time t falling edge of

apply. The first data bit is clocked out from the

SYNC. The SCLK rising edge clocks out all subsequent bits on the DOUT pin. The input data present on the DIN pin is clocked in on the rising edge of the SCLK. The POLARITY pin may be used to change the SCLK edge which the data is sampled on and clocked out on. The

SYNC will go high after the 16th SCLK rising edge and before the rising edge D of the continuous SCLK in Figure 39. This ensures the part will not clock in an extra bit from the DIN pin or clock out an

Figure 39. Timing Diagram for Read/Write with (i.e., Operating Mode Numbers 4 and 5, SM1 = 1, SM2 = 1 and 0)

DOUT (O/P)

SYNC (O/P)

SCLK (O/P)

DIN (I/P)

POLARITY PIN LOGIC HIGH

3-STATE

t4 = 0.6 t

SCLK

= 30ns MIN, t8 = 20ns MIN , t

162345

(NONCONTINUOUS SCLK), t6 = 45ns MAX,

SYNC

= 50ns MAX

11A

DB12

DB10DB11DB13DB14DB15

Output and SCLK Output (Continuous and Noncontinuous)

–26–

11A

DB0DB10DB12DB13DB14DB15 DB11

DB0

3-STATE

REV. A

AD7851

extra bit on the DOUT pin. If the user has control of the

CONVST pin but does not want to exercise it for every conversion, the control register may be used to start a conversion. Setting the CONVST bit in the control register to 1 starts a conversion. If the user does not have control of the

CONVST pin, a conversion should not initiated by writing to the control register. The reason for this is that the user may get “locked out” and not be able to perform any further write/read operations. When a conversion is started by writing to the control register, the

SYNC goes low and read/write operations take place while the conversion is in progress. However, once the conversion is complete, there is no way of writing to the part unless the signal triggers the erations to take place. operations. The

CONVST pin is exercised. The CONVST

SYNC signal low which allows read/write op-

SYNC must be low to perform read/write

SYNC is triggered low by the CONVST signal

rising edge or setting the CONVST bit in the control register to

1. Therefore if there is not full control of the

CONVST pin the

user may end up getting “locked out.”

START

DIN CONNECTED TO DGND

POWER-ON, APPLY CLKIN SIGNAL,

WAIT 150ms FOR AUTOMATIC CALIBRATION

CONFIGURING THE AD7851 AD7851 as a Read-Only ADC

The AD7851 contains fourteen on-chip registers which can be accessed via the serial interface. In the majority of applications it will not be necessary to access all of these registers. Figure 40 outlines a flowchart of the sequence which is used to configure the AD7851 as a Read-Only ADC. In this case there is no writing to the on-chip registers and only the conversion result data is read from the part. Interface Mode 1 cannot be used in this case as it is necessary to write to the control register to set Interface Mode 1. Here the CLKIN signal is applied directly after poweron, the CLKIN signal must be present to allow the part to perform a calibration. This automatic calibration will be completed approximately 150 ms after power-on.

SERIAL

INTERFACE

MODE

PULSE CONVST PIN

READ DATA

DURING

CONVERSION

WAIT FOR BUSY SIGNAL

TO GO LOW

APPLY SYNC (IF REQUIRED), SCLK AND READ

CONVERSION RESULT ON DOUT PIN

4, 5

2, 3

YES

Figure 40. Flowchart for Setting Up and Reading from the AD7851

WAIT APPROXIMATELY 200ns AFTER CONVST RISING EDGE

PULSE CONVST PIN

SYNC AUTOMATICALLY GOES LOW

AFTER CONVST RISING EDGE

SCLK AUTOMATICALLY ACTIVE, READ

CONVERSION RESULT ON DOUT PIN

REV. A

–27–

AD7851

Writing to the AD7851

For accessing the on-chip registers it is necessary to write to the part. To enable Serial Interface Mode 1, the user must also write to the part. Figure 41 through 43 outline flowcharts of how to configure the AD7851 for each of the different serial interface modes. The continuous loops on all diagrams indicate the sequence for more than one conversion. The options of using a hardware (pulsing the

CONVST pin) or software (setting the CONVST bit to 1) conversion start, and reading/writing during or after conversion are shown in Figures 41 and 42. If the CONVST pin is never used then it should be tied to DVDD per- manently. Where reference is made to the BUSY bit equal to a

START

POWER-ON, APPLY CLKIN SIGNAL,

WAIT 150ms FOR AUTOMATIC CALIBRATION

SERIAL

INTERFACE

MODE

2, 3

NOTE: WHEN USING THE SOFTWARE CONVERSION START AND TRANSFERRING DATA DURING CONVERSION THE USER MUST ENSURE THE CONTROL REGISTER WRITE OPERATION EXTENDS BEYOND THE FALLING EDGE OF BUSY. THE FALLING EDGE OF BUSY RESETS THE CONVST BIT TO 0 AND ONLY AFTER THIS TIME CAN IT BE REPROGRAMMED TO 1 TO START THE NEXT CONVERSION.

logic 0, to indicate the end of conversion, the user in this case would poll the BUSY bit in the status register.

Interface Modes 2 and 3 Configuration

Figure 41 shows the flowchart for configuring the part in Interface Modes 2 and 3. For these interface modes, the read and write operations take place simultaneously via the serial port. Writing all 0s ensures that no valid data is written to any of the registers. When using the software conversion start and transferring data during conversion, Note must be obeyed.

YES

WAIT APPROXIMATELY 200ns

AFTER CONVST RISING EDGE

WAIT FOR BUSY SIGNAL TO GO

LOW OR WAIT FOR BUSY BIT = 0

APPLY SYNC (IF REQUIRED),

SCLK, READ PREVIOUS CONVERSION

RESULT ON DOUT PIN,

AND WRITE ALL 0s ON DIN PIN

APPLY SYNC (IF REQUIRED), SCLK, READ

CURRENT CONVERSION RESULT ON DOUT PIN,

AND WRITE ALL 0s ON DIN PIN

INITIATE

CONVERSION

SOFTWARE

PULSE CONVST PIN

TRANSFER

DATA

DURING

CONVERSION

YES

TRANSFER

DATA DURING

CONVERSION

APPLY SYNC (IF REQUIRED), SCLK, WRITE TO CONTROL

CONVERSION RESULT ON DOUT PIN

WAIT FOR BUSY SIGNAL TO GO LOW

OR WAIT FOR BUSY BIT = 0

YES

APPLY SYNC (IF REQUIRED), SCLK, WRITE TO CONTROL

CONVERSION RESULT ON DOUT PIN (SEE NOTE)

Figure 41. Flowchart for Setting Up, Reading, and Writing in Interface Modes 2 and 3

–28–

REV. A

AD7851

POWER-ON, APPLY CLKIN SIGNAL,

WAIT 150ms FOR AUTOMATIC CALIBRATION

SYNC AUTOMATICALLY GOES

LOW AFTER CONVST RISING EDGE

PULSE CONVST PIN

SCLK AUTOMATICALLY ACTIVE, READ CURRENT

CONVERSION RESULT ON DOUT PIN, WRITE

TO CONTROL REGISTER ON DIN PIN

4, 5

START

SERIAL

INTERFACE

MODE

Interface Mode 1 Configuration

Figure 42 shows the flowchart for configuring the part in Interface Mode 1. This mode of operation can only be enabled by writing to the control register and setting the 2/

3 MODE bit. Reading and writing cannot take place simultaneously in this mode as the DIN pin is used for both reading and writing.

START

POWER-ON, APPLY CLKIN SIGNAL,

WAIT 150ms FOR AUTOMATIC CALIBRATION

SERIAL

INTERFACE

MODE

INITIATE

CONVERSION

SOFTWARE

APPLY SYNC (IF REQUIRED),

SCLK, WRITE TO CONTROL REGISTER

SETTING THE TWO-WIRE MODE

AND CONVST BIT TO 1

YES

Interface Modes 4 and 5 Configuration

Figure 43 shows the flowchart for configuring the AD7851 in Interface Modes 4 and 5, the self-clocking modes. In this case it is not recommended to use the software conversion start option. The read and write operations always occur simultaneously and during conversion.

APPLY SYNC (IF REQUIRED),

SCLK, WRITE TO CONTROL REGISTER

SETTING THE TWO-WIRE MODE

PULSE CONVST PIN

READ

YES

WAIT APPROXIMATLY 200ns

AFTER CONVST RISING EDGE

OR AFTER END OF CONTROL

Figure 42. Flowchart for Setting Up, Reading, and Writing

APPLY SYNC (IF REQUIRED),

SCLK, READ PREVIOUS CONVERSION

RESULT ON DIN PIN

WAIT FOR BUSY SIGNAL TO GO

LOW OR WAIT FOR BUSY BIT = 0

APPLY SYNC (IF REQUIRED), SCLK, READ

CURRENT CONVERSION RESULT ON DIN PIN

DATA

DURING

CONVERSION

in Interface Mode 1

Figure 43. Flowchart for Setting Up, Reading, and Writing in Interface Modes 4 and 5

REV. A

–29–

AD7851

(8XC51/L51) /PIC17C42

P3.0/DT

P3.1/CK

AD7851

CONVST

CLKIN SCLK DIN

SYNC

SM1 SM2

POLARITY

OPTIONAL

7MHz/6MHz

BUSY

(INT0/P3.2)/INT

DVDD FOR 8XC51/L51 DGND FOR PIC17C42

MASTER

SLAVE

OPTIONAL

68HC11/L11/16

SCK

AD7851

CONVST

CLKIN

SCLK DOUT BUSY

SM1

SM2 POLARITY

OPTIONAL

7MHz/6MHz

SYNC

MISO

DIN AT DGND FOR

NO WRITING TO PART

MASTER

SLAVE

DIN

OPTIONAL

IRQ

MOSI

DVDDFOR HC11, SPI

DGND FOR HC16, QSPI

SPI

HC16, QSPI

MICROPROCESSOR INTERFACING

In many applications, the user may not require the facility of writing to the on-chip registers. The user may just want to hardwire the relevant pins to the appropriate levels and read the conversion result. In this case the DIN pin can be tied low so that the on-chip registers are never used. Now the part will operate as a nonprogrammable analog to digital converter where the

CONVST is applied, a conversion is performed and the result may be read using the SCLK to clock out the data from the output register on to the DOUT pin. Note that the DIN pin cannot be tied low when using the two-wire interface mode of operation.

The SCLK can also be connected to the CLKIN pin if the user does not want to have to provide separate serial and master clocks in Interface Modes 1, 2, and 3. With this arrangement the

SYNC signal must be low for 16 SCLK cycles in Interface Modes 1 and 2 for the read and write operations. For Interface Mode 3 the for the read and write operations. Note that in Interface Modes 4 and 5 the CLKIN and SCLK cannot be tied together as the SCLK is an output and the CLKIN is an input.

Figure 44. Simplified Interface Diagram with DIN Grounded and SCLK Tied to CLKIN

AD7851 to 8XC51/PIC17C42 Interface

Figure 45 shows the AD7851 interface to the 8XC51/PIC17C42. The 8XC51/PIC17C42 only run at 5 V. The 8XC51 is in Mode 0 operation. This is a two-wire interface consisting of the SCLK and the DIN which acts as a bidirectional line. The tied low. The BUSY line can be used to give an interrupt driven system but this would not normally be the case with the 8XC51/ PIC17C42. For the 8XC51 12 MHz version, the serial clock will run at a maximum of 1 MHz so that the serial interface to the AD7851 will only be running at 1 MHz. The CLKIN signal must be provided separately to the AD7851 from a port line on the 8XC51 or from a source other than the 8XC51. Here the SCLK cannot be tied to the CLKIN as the 8XC51 only provides a noncontinuous serial clock. The provided from an external timer or conversion can be started in software if required. The sequence of events would typically be writing to the control register via the DIN line setting a conversion start and the 2-wire interface mode (this would be performed in two 8-bit writes), wait for the conversion to be finished (3.25 µs with 6 MHz CLKIN), read the conversion re- sult data on the DIN line (this would be performed in two 8-bit reads), and then repeat the sequence. The maximum serial frequency will be determined by the data access and hold times of the 8XC51/PIC16C42 and the AD7851.

SYNC can be low for more than 16 SCLK cycles

CONVST

CLKIN

AD7851

SCLK

SYNC

DIN

DOUT

CONVST signal can be

CONVERSION START

7 MHz/6MHz MASTER CLOCK

SYNC SIGNAL TO GATE THE SCLK

SERIAL DATA OUTPUT

SYNC is

Figure 45. 8XC51/PIC16C42 Interface

AD7851 to 68HC11/16/L11 / PIC16C42 Interface

Figure 46 shows the AD7851 SPI/QSPI interface to the 68HC11/16/L11/PIC16C42. The

SYNC line is not used and is tied to DGND. The µController is configured as the master, by setting the MSTR bit in the SPCR to 1, and thus provides the serial clock on the SCK pin. For all the µControllers, the CPOL bit is set to 1 and for the 68HC11/16/L11, the CPHA bit is set to 1. The CLKIN and

CONVST signals can be supplied from the µController or from separate sources. The BUSY signal can be used as an interrupt to tell the µController when the conver- sion is finished, then the reading and writing can take place. If required the reading and writing can take place during conversion and there will be no need for the BUSY signal in this case. For no writing to the part then the DIN pin can be tied permanently low. For the 68HC16 and the QSPI interface the SM2 pin should be tied high and the

SS line tied to the SYNC pin. The microsequencer on the 68HC16 QSPI port can be used for performing a number of read and write operations independent of the CPU and storing the conversion results in memory without taxing the CPU. The typical sequence of events would be writing to the control register via the DIN line setting a conversion start and at the same time reading data from the previous conversion on the DOUT line, wait for the conversion to be finished (3.25 µs with 6 MHz CLKIN), and then repeat the sequence. The maximum serial frequency will be determined by the data access and hold times of the µControllers and the AD7851.

Figure 46. 68HC11 and 68HC16 Interface

–30–

REV. A

AD7851

CONVST

CLKIN SCLK DOUT

BUSY

SM1 SM2 POLARITY

OPTIONAL

7MHz/6MHz

SYNC

DIN AT DGND FOR

NO WRITING TO PART

SLAVE

MASTER

OPTIONAL

DIN

OPTIONAL

FSX INT0

TMS320C20/

25/5x/LC5x

CLKR

FSR

CLKX

AD7851 to ADSP-21xx Interface

Figure 47 shows the AD7851 interface to the ADSP-21xx. The ADSP-21xx is the slave and the AD7851 is the master. The AD7851 is in Interface Mode 5. For the ADSP-21xx, the bits in the serial port control register should be set up as TFSR = RFSR = 1 (need a frame sync for every transfer), SLEN = 15 (16-bit word length), TFSW = RFSW = 1 (alternate framing mode for transmit and receive operations), INVRFS = INVTFS = 1 (active low RFS and TFS), IRFS = ITFS = 0 (External RFS and TFS), and ISCLK = 0 (external serial clock). The CLKIN and

CONVST signals could be supplied from the ADSP-21xx or from an external source. The AD7851 supplies the SCLK and the

SYNC signals to the ADSP-21xx and the reading and writing takes place during conversion. The BUSY signal only indicates when the conversion is finished and may not be required. The data access and hold times of the ADSP21xx and the AD7851 allows for a CLKIN of 7 MHz/6 MHz with a 5 V supply.

ADSP-21xx

SLAVE

SCK

RFS

TFS

IRQ

OPTIONAL

7MHz/6MHz

OPTIONAL OPTIONAL

CONVST

CLKIN SCLK

DOUT

SYNC

BUSY DIN

AD7851

MASTER

DSP

56000/1/2/L002

MASTER

7MHz/6MHz

SCK SRD

SC2

IRQ

STD

NO WRITING TO PART

OPTIONAL OPTIONAL

DIN AT DGND FOR

OPTIONAL

AD7851

CONVST

CLKIN SCLK DOUT

SYNC

BUSY DIN

SLAVE

SM1 SM2 POLARITY

Figure 48. DSP56000/1/2 Interface

AD7851 to TMS320C20/25/5x/LC5x Interface

Figure 49 shows the AD7851 to the TMS320Cxx interface. The AD7851 is the master and operates in Interface Mode 5. For the TMS320Cxx the CLKX, CLKR, FSX, and FSR pins should all be configured as inputs. The CLKX and the CLKR should be connected together as should the FSX and FSR. Since the AD7851 is the master and the reading and writing occurs during the conversion, the BUSY only indicates when the conversion is finished and thus may not be required. Again the data access and hold times of the TMS320Cxx and the AD7851 allows for a CLKIN of 7 MHz/6 MHz.

DIN AT DGND FOR

NO WRITING TO PART

SM1 SM2 POLARITY

Figure 47. ADSP-21xx Interface

AD7851 to DSP56000/1/2/L002 Interface

Figure 48 shows the AD7851 to DSP56000/1/2/L002 interface. Here the DSP5600x is the master and the AD7851 is the slave. The AD7851 is in Interface Mode 3. The setting of the bits in the registers of the DSP5600x would be for synchronous operation (SYN = 1), internal frame sync (SCD2 = 1), Internal clock (SCKD = 1), 16-bit word length (WL1 = 1, WL0 = 0), frames sync only active at beginning of the transfer (FSL1 = 0, FSL0 =

1). A gated clock can be used (GCK = 1) or if the SCLK is to be tied to the CLKIN of the AD7851, then there must be a continuous clock (GCK = 0). Again the data access and hold times of the DSP5600x and the AD7851 should allow for an SCLK of 7 MHz/6 MHz.

REV. A

Figure 49. TMS320C20/25/5x Interface

–31–

AD7851

APPLICATION HINTS Grounding and Layout

The analog and digital supplies to the AD7851 are independent and separately pinned out to minimize coupling between the analog and digital sections of the device. The part has very good immunity to noise on the power supplies as can be seen by the PSRR versus Frequency graph. However, care should still be taken with regard to grounding and layout.

The printed circuit board that houses the AD7851 should be designed such that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be separated easily. A minimum etch technique is generally best for ground planes as it gives the best shielding. Digital and analog ground planes should only be joined in one place. If the AD7851 is the only device requiring an AGND to DGND connection, then the ground planes should be connected at the AGND and DGND pins of the AD7851. If the AD7851 is in a system where multiple devices require AGND to DGND connections, the connection should still be made at one point only, a star ground point which should be established as close as possible to the AD7851.

Avoid running digital lines under the device as these will couple noise onto the die. The analog ground plane should be allowed to run under the AD7851 to avoid noise coupling. The power supply lines to the AD7851 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals like clocks should be shielded with digital ground to avoid radiating noise to other sections of the board and clock signals should never be run near the analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This will reduce the effects of feedthrough through the board. A microstrip technique is by far the best but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes while signals are placed on the solder side.

Good decoupling is also important. All analog supplies should be decoupled with 10 µF tantalum in parallel with 0.1µF ca- pacitors to AGND. All digital supplies should have a 0.1 µF disc ceramic capacitor to AGND. To achieve the best from these decoupling components, they must be placed as close as possible to the device, ideally right up against the device. In systems where a common supply voltage is used to drive both the AV

and DVDD of the AD7851, it is recommended that the system’s AV

supply is used. In this case there should be a 10 Ω resistor

between the AV

pin and DVDD pin. This supply should have

the recommended analog supply decoupling capacitors between the AV digital supply decoupling capacitor between the DV

pin of the AD7851 and AGND and the recommended

pin of the

AD7851 and DGND.

Evaluating the AD7851 Performance

The recommended layout for the AD7851 is outlined in the evaluation board for the AD7851. The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from the PC via the EVAL-CONTROL BOARD. The EVAL-CONTROL BOARD can be used in conjunction with the AD7851 Evaluation board, as well as many other Analog Devices evaluation boards ending in the CB designator, to demonstrate/evaluate the ac and dc performance of the AD7851.

The software allows the user to perform ac (fast Fourier transform) and dc (histogram of codes) tests on the AD7851. It also gives full access to all the AD7851 on-chip registers allowing for various calibration and power-down options to be programmed.

AD785x Family

All parts are 12 bits, 200 kSPS, 3.0 V to 5.5 V.

AD7853 – Single Channel Serial AD7854 – Single Channel Parallel AD7858 – Eight Channel Serial AD7859 – Eight Channel Parallel

–32–

REV. A

AD7851

PAGE INDEX Topic Page

FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1

PRODUCT HIGHLIGHTS . . . . . . . . . . . . . . . . . . . . . . . . . 1

SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 4

TYPICAL TIMING DIAGRAMS . . . . . . . . . . . . . . . . . . . . 5

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 6

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PINOUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

PIN FUNCTION DESCRIPTION . . . . . . . . . . . . . . . . . . . 8

AD7851 ON-CHIP REGISTERS . . . . . . . . . . . . . . . . . . . . . 9

Addressing the On-Chip Registers . . . . . . . . . . . . . . . . . . . 9

Writing/Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

CONTROL REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

CALIBRATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . 12

Addressing the Calibration Registers . . . . . . . . . . . . . . . . 12

Writing to/Reading from the Calibration Registers . . . . . . 12

Adjusting the Offset Calibration Register . . . . . . . . . . . . . 13

Adjusting the Gain Calibration Registers . . . . . . . . . . . . . 13

CIRCUIT INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . 14

CONVERTER DETAILS . . . . . . . . . . . . . . . . . . . . . . . . . . 14

TYPICAL CONNECTION DIAGRAM . . . . . . . . . . . . . . . 14

ANALOG INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Acquisition Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

DC/AC Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Input Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Transfer Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

REFERENCE SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . 17

AD7851 PERFORMANCE CURVES . . . . . . . . . . . . . . . . 17

POWER-DOWN OPTIONS . . . . . . . . . . . . . . . . . . . . . . . . 18

POWER-UP TIMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Using an External Reference . . . . . . . . . . . . . . . . . . . . . . 19

Using the Internal (On-Chip) Reference . . . . . . . . . . . . . 19

POWER VS. THROUGHPUT RATE . . . . . . . . . . . . . . . . 19

CALIBRATION SECTION . . . . . . . . . . . . . . . . . . . . . . . . 20

Calibration Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Automatic Calibration on Power-On . . . . . . . . . . . . . . . . 20

Self-Calibration Description . . . . . . . . . . . . . . . . . . . . . . . 20

Self-Calibration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 21

System Calibration Description . . . . . . . . . . . . . . . . . . . . 21

System Gain and Offset Interaction . . . . . . . . . . . . . . . . . 22

System Calibration Timing . . . . . . . . . . . . . . . . . . . . . . . 22

SERIAL INTERFACE SUMMARY . . . . . . . . . . . . . . . . . . 23

Resetting the Serial Interface . . . . . . . . . . . . . . . . . . . . . . 23

DETAILED TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Mode 1 (2-Wire 8051 Interface) . . . . . . . . . . . . . . . . . . . 24

Mode 2 (3-Wire SPI/QSPI Interface Mode) . . . . . . . . . . . 25

Mode 3 (QSPI Interface Mode) . . . . . . . . . . . . . . . . . . . . 25

Mode 4 and 5 (Self-Clocking Modes) . . . . . . . . . . . . . . . 26

CONFIGURING THE AD7851 . . . . . . . . . . . . . . . . . . . . . 27

AD7851 as a Read-Only ADC . . . . . . . . . . . . . . . . . . . . . 27

Writing to the AD7851 . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Interface Modes 2 and 3 Configuration . . . . . . . . . . . . . . 28

Interface Mode 1 Configuration . . . . . . . . . . . . . . . . . . . . 29

Interface Modes 4 and 5 Configuration . . . . . . . . . . . . . . 29

MICROPROCESSOR INTERFACING . . . . . . . . . . . . . . . 30

AD7851 – 8XC51/PIC17C42 Interface . . . . . . . . . . . . . . . . 30

AD7851 – 68HC11/16/L11/PIC16C42 Interface . . . . . . . . 30

AD7851 – ADSP-21xx Interface . . . . . . . . . . . . . . . . . . . . . 31

AD7851 – DSP56000/1/2/L002 Interface . . . . . . . . . . . . . . 31

AD7851 – TMS320C20/25/5x/LC5x Interface . . . . . . . . . . 31

APPLICATIONS HINTS . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Grounding and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Evaluating the AD7851 Performance . . . . . . . . . . . . . . . . 32

INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 34

TABLE INDEX

# Title Page

I Write Register Addressing . . . . . . . . . . . . . . . . . . . . . . . 9

II Read Register Addressing . . . . . . . . . . . . . . . . . . . . . . . 9

III Calibration Selection . . . . . . . . . . . . . . . . . . . . . . . . . . 10

IV Calibrating Register Addressing . . . . . . . . . . . . . . . . . . 12

V Analog Input Connections . . . . . . . . . . . . . . . . . . . . . . 16

VI Power Management Options . . . . . . . . . . . . . . . . . . . . 18

VII Power Consumption vs. Throughput . . . . . . . . . . . . . . 20

VIII Calibration Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

IX SCLK Active Edges . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

X Interface Mode Description . . . . . . . . . . . . . . . . . . . . . 23

REV. A

–33–

AD7851

0.210 (5.33)

MAX

0.200 (5.05)

0.125 (3.18)

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

24-Pin Plastic DIP

(N-24)

1.275 (32.30)

1.125 (28.60)

112

PIN 1

0.022 (0.558)

0.014 (0.356)

0.100 (2.54) BSC

0.070 (1.77)

0.045 (1.15)

0.280 (7.11)

0.240 (6.10)

0.060 (1.52)

0.015 (0.38)

0.150 (3.81) MIN

SEATING PLANE

0.325 (8.25)

0.300 (7.62)

24-Pin Small Outline Package

(R-24)

0.6141 (15.60)

0.5985 (15.20)

0.195 (4.95)

0.115 (2.93)

0.015 (0.381)

0.008 (0.204)

0.0118 (0.30)

0.0040 (0.10)

0.311 (7.9)

0.301 (7.64)

0.078 (1.98)

0.068 (1.73)

PIN 1

0.0500 (1.27)

BSC

0.0192 (0.49)

0.0138 (0.35)

0.2992 (7.60)

0.1043 (2.65)

0.0926 (2.35)

SEATING PLANE

0.2914 (7.40)

0.4193 (10.65)

0.3937 (10.00)

0.0125 (0.32)

0.0091 (0.23)

24-Pin Shrink Small Outline Package

(RS-24)

0.328 (8.33)

0.318 (8.08)

PIN 1

0.212 (5.38)

0.07 (1.78)

0.066 (1.67)

0.205 (5.207)

0.0291 (0.74)

0.0098 (0.25)

8° 0°

x 45°

0.0500 (1.27)

0.0157 (0.40)

0.008 (0.203)

0.002 (0.050)

0.0256 (0.65)

BSC

0.015 (0.38)

0.010 (0.25)

SEATING

PLANE

–34–

0.009 (0.229)

0.005 (0.127)

8° 0°

0.037 (0.94)

0.022 (0.559)

REV. A

–35–

C2166–18–8/96

–36–

PRINTED IN U.S.A.

Analog Devices AD7851CB, AD7851KR, AD7851KN, AD7851ARS, AD7851AR Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TYPICAL TIMING DIAGRAMS

ABSOLUTE MAXIMUM RATINGS

ORDERING GUIDE

TERMINOLOGY

PIN FUNCTION DESCRIPTION

CONTROL REGISTER

STATUS REGISTER

CALIBRATION REGISTERS

CIRCUIT INFORMATION

CONVERTER DETAILS

ANALOG INPUT

REFERENCE SECTION

POWER-DOWN OPTIONS

POWER VS. THROUGHPUT RATE

SYSTEM GAIN CALIBRATION

SERIAL INTERFACE SUMMARY

Figure 37.

MICROPROCESSOR INTERFACING