Analog Devices AD7851 b Datasheet

14-Bit 333 kSPS

a

FEATURES
Single 5 V Supply
333 kSPS Throughput Rate/ⴞ2 LSB DNL—A Grade
285 kSPS Throughput Rate/ⴞ1 LSB DNL—K Grade
A and K Grades Guaranteed to 125ⴗC/238 kSPS

Throughput Rate
Pseudo-Differential Input with Two Input Ranges
System and Self-Calibration with Autocalibration on

Power-Up
Read/Write Capability of Calibration Data
Low Power: 60 mW Typ
Power-Down Mode: 5 ␮W Typ Power Consumption
Flexible Serial Interface: 8051/SPI
24-Lead PDIP, SOIC, and SSOP Packages

APPLICATIONS
Digital Signal Processing
Speech Recognition and Synthesis
Spectrum Analysis
DSP Servo Control
Instrumentation and Control Systems
High Speed Modems
Automotive

®

/QSPI™/␮P Compatible

AIN (+)

AIN (–)

REFIN/

REF

C

C

OUT

REF1

REF2

CAL

Serial A/D Converter

AD7851

FUNCTIONAL BLOCK DIAGRAM

AV

T/H

REFERENCE

BUF

CHARGE

REDISTRIBUTION

CALIBRATION

MEMORY

AND CONTROLLER

SERIAL INTERFACE/CONTROL REGISTER

SM1 SM2 DIN DOUT SCLK POLARITY

DD

DAC

4.096V

SYNC

AGND

COMP

AGND

AD7851

SAR + ADC

CONTROL

*

DV

DD

DGND

AMODE

CLKIN

CONVST

BUSY

SLEEP

GENERAL DESCRIPTION

The AD7851 is a high speed, 14-bit ADC that operates from a
single 5 V power supply. The ADC powers up with a set of default
conditions at which time it can be operated as a read-only ADC.
The ADC contains self-calibration and system calibration options
to ensure accurate operation over time and temperature and has a
number of power-down options for low power applications.

The AD7851 is capable of a 333 kHz throughput rate. The
input track-and-hold acquires a signal in 0.33 µs and features
a pseudo-differential sampling scheme. The AD7851 has the
added advantage of two input voltage ranges (0 V to V

/2 to +V

–V

REF

range is to V

/2 centered about V

REF

and the part is capable of converting full

DD

/2). Input signal

REF

REF

and

power signals to 20 MHz.

CMOS construction ensures low power dissipation (60 mW typ)
with power-down mode (5 µW typ). The part is available in a
24-lead, 0.3 inch-wide PDIP, a 24-lead SOIC, and a 24-lead
SSOP package.

*Protected by U.S. Patent No. 5,852,415; 5,668,551; 5,600,322; 5,600,275;
and 5,589,785

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

PRODUCT HIGHLIGHTS

1. Single 5 V supply.

2. Operates with reference voltages from 4 V to V

3. Analog input ranges from 0 V to V

DD

.

DD

.

4. System and self-calibration including power-down mode.

5. Versatile serial I/O port.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

AD7851

TABLE OF CONTENTS

FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1

PRODUCT HIGHLIGHTS . . . . . . . . . . . . . . . . . . . . . . . . . 1

SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 5

TYPICAL TIMING DIAGRAMS . . . . . . . . . . . . . . . . . . . . 6

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 7

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

PINOUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 9

AD7851 ON-CHIP REGISTERS . . . . . . . . . . . . . . . . . . . . 10

Addressing the On-Chip Registers . . . . . . . . . . . . . . . . . . 10

Writing/Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

CONTROL REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

CALIBRATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . 13

Addressing the Calibration Registers . . . . . . . . . . . . . . . . 13

Writing to/Reading from the Calibration Registers . . . . . . 13

Adjusting the Offset Calibration Register . . . . . . . . . . . . . 14

Adjusting the Gain Calibration Registers . . . . . . . . . . . . . 14

CIRCUIT INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . 15

CONVERTER DETAILS . . . . . . . . . . . . . . . . . . . . . . . . . . 15

TYPICAL CONNECTION DIAGRAM . . . . . . . . . . . . . . 15

ANALOG INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Acquisition Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

DC/AC Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Input Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Transfer Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

REFERENCE SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . 18

AD7851 PERFORMANCE CURVES . . . . . . . . . . . . . . . . 18

POWER-DOWN OPTIONS . . . . . . . . . . . . . . . . . . . . . . . . 19

POWER-UP TIMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Using an External Reference . . . . . . . . . . . . . . . . . . . . . . 20

Using the Internal (On-Chip) Reference . . . . . . . . . . . . . 20

POWER VS. THROUGHPUT RATE . . . . . . . . . . . . . . . . 20

CALIBRATION SECTION . . . . . . . . . . . . . . . . . . . . . . . . 21

Calibration Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Automatic Calibration on Power-On . . . . . . . . . . . . . . . . 21

Self-Calibration Description . . . . . . . . . . . . . . . . . . . . . . . 21

Self-Calibration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 22

System Calibration Description . . . . . . . . . . . . . . . . . . . . 22

System Gain and Offset Interaction . . . . . . . . . . . . . . . . . 23

System Calibration Timing . . . . . . . . . . . . . . . . . . . . . . . 23

SERIAL INTERFACE SUMMARY . . . . . . . . . . . . . . . . . . 24

Resetting the Serial Interface . . . . . . . . . . . . . . . . . . . . . . 24

DETAILED TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Mode 1 (2-Wire 8051 Interface) . . . . . . . . . . . . . . . . . . . 25

Mode 2 (3-Wire SPI/QSPI Interface Mode) . . . . . . . . . . . 26

Mode 3 (QSPI Interface Mode) . . . . . . . . . . . . . . . . . . . . 26

Mode 4 and 5 (Self-Clocking Modes) . . . . . . . . . . . . . . . 27

CONFIGURING THE AD7851 . . . . . . . . . . . . . . . . . . . . . 28

AD7851 as a Read-Only ADC . . . . . . . . . . . . . . . . . . . . . 28

Writing to the AD7851 . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Interface Modes 2 and 3 Configuration . . . . . . . . . . . . . . 29

Interface Mode 1 Configuration . . . . . . . . . . . . . . . . . . . . 30

Interface Modes 4 and 5 Configuration . . . . . . . . . . . . . . 30

MICROPROCESSOR INTERFACING . . . . . . . . . . . . . . . 31

AD7851 to 8XC51/PIC17C42 Interface . . . . . . . . . . . . . . . 31

AD7851 to 68HC11/16/L11/PIC16C42 Interface . . . . . . . . 31

AD7851 to ADSP-21xx Interface . . . . . . . . . . . . . . . . . . . . 32

AD7851 to DSP56000/1/2/L002 Interface . . . . . . . . . . . . . 32

AD7851 to TMS320C20/25/5x/LC5x Interface . . . . . . . . . 32

APPLICATIONS HINTS . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Grounding and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Evaluating the AD7851 Performance . . . . . . . . . . . . . . . . 33

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 34

REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

–2–

REV. B

AD7851

SPECIFICATIONS

1, 2

A Grade: f
(to 125ⴗC), f
unless otherwise noted.)

Parameter Version A1Version K1Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

Signal-to-Noise + Distortion Ratio

Total Harmonic Distortion (THD) –86 –86 dB max V

Peak Harmonic or Spurious Noise –87 –87 dB max V
Intermodulation Distortion (IMD)

Second-Order Terms –86 –90 dB typ fa = 9.983 kHz, fb = 10.05 kHz, f
Third-Order Terms –86 –90 dB typ fa = 9.983 kHz, fb = 10.05 kHz, f

Full Power Bandwidth 20 20 MHz typ @ 3 dB.

DC ACCURACY

Resolution 14 14 Bits
Integral Nonlinearity ±2 ±1 LSB max
Differential Nonlinearity ±2 ±1 LSB max Guaranteed No Missed Codes to 14 Bits
Unipolar Offset Error ±10 ± 10 LSB max Review: Adjusting the Offset Calibration
Positive Full-Scale Error ± 10 ± 10 LSB max Register in the Calibration Registers section.
Negative Full-Scale Error ±10 ± 10 LSB typ
Bipolar Zero Error ±1 ±1 LSB typ

ANALOG INPUT

Input Voltage Ranges 0 V to V

Leakage Current ±1 ±1 µA max
Input Capacitance 20 20 pF typ

= 7 MHz (–40ⴗC to +85ⴗC), f

CLKIN

= 238 kHz; (AVDD = DVDD = 5.0 V ⴞ 5%, REFIN/REF

SAMPLE

3

(SNR) 77 78 dB min Typically SNR Is 79.5 dB.

= 333 kHz; K Grade: f

SAMPLE

±V

REF

/2 ±V

REF

= 6 MHz (0ⴗC to 85ⴗC), f

CLKIN

= 4.096 V External Reference; SLEEP = Logic High; TA = T

OUT

V

= 285 kHz; A and K Grade: f

SAMPLE

= 10 kHz, Sine Wave, f

IN

= 10 kHz, Sine Wave, f

IN

typically –96 dB.

= 10 kHz, f

0 V to V

IN

V AIN(+) – AIN(–) = 0 V to V

REF

SAMPLE

biased up but AIN(+) cannot go below AIN(–).

/2 V AIN(+) – AIN(–) = –V

REF

should be biased up and AIN(+) can go below
AIN(–) but cannot go below 0 V.

MIN

SAMPLE

SAMPLE

= 333 kHz.

SAMPLE

SAMPLE

, AIN(–) can be

REF

/2 to +V

REF

= 5 MHz

CLKIN

to T

MAX

= 333 kHz.
= 333 kHz,

= 333 kHz.
= 333 kHz.

/2, AIN(–)

REF

,

REFERENCE INPUT/OUTPUT

REF

Input Voltage Range 4/V

IN

DD

4/V

DD

V min/max Functional from 1.2 V.

Input Impedance 150 150 kΩ typ Resistor Connected to Internal Reference Node.
REF
REF

Output Voltage 3.696/4.496 3.696/4.496 V min/max

OUT

Temperature Coefficient 50 50 ppm/°C typ

OUT

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance, C

INL

IN

IN

INH

4

VDD – 1.0 VDD – 1.0 V min

0.4 0.4 V max
±10 ± 10 µA max V
10 10 pF max

= 0 V or VDD.

IN

LOGIC OUTPUTS

Output High Voltage, V
Output Low Voltage, V
Floating State Leakage Current ± 10 ±10 µA max
Floating State Output Capacitance

OH

OL

4

VDD – 0.4 VDD – 0.4 V min I

0.4 0.4 V max I

10 10 pF max

SOURCE

= 0.8 mA.

SINK

= 200 µA.

Output Coding Straight (Natural) Binary Unipolar Input Range.

Twos Complement Bipolar Input Range.

CONVERSION RATE

Conversion Time 2.78 3.25 µs max 19.5 CLKIN Cycles.
Conversion + Track-and-Hold

Acquisition Time 3.0 3.5 µs max 21 CLKIN Cycles Throughput Rate.

REV. B

–3–

AD7851

Parameter Version A1Version K1Unit Test Conditions/Comments

POWER PERFORMANCE

AV

DD, DVDD

I

DD

Normal Mode

Sleep Mode

4

5

With External Clock On 20 20 µA typ Full Power-Down. Power management bits

With External Clock Off 10 10 µA max Typically 1 µA. Full Power-Down. Power

Normal Mode Power Dissipation 89.25 89.25 mW max V
Sleep Mode Power Dissipation

With External Clock On 105 105 µW typ V
With External Clock Off 52.5 52.5 µW max VDD = 5.25 V; Typically 5.25 µW; SLEEP = 0 V.

4.75/5.25 4.75/5.25 V min/max

17 17 mA max AV

= DVDD = 4.75 V to 5.25 V. Typically

DD

12 mA.

in control register set as PMGT1 = 1, PMGT0 = 0.

600 600 µA typ Partial Power-Down. Power management bits in

control register set as PMGT1 = 1, PMGT0 = 1.

management bits in control register set as
PMGT1 = 1, PMGT0 = 0.

300 300 µA typ Partial Power-Down. Power management bits in

control register set as PMGT1 = 1, PMGT0 = 1.

= 5.25 V: Typically 63 mW; SLEEP = VDD.

DD

= 5.25 V; SLEEP = 0 V.

DD

SYSTEM CALIBRATION

Offset Calibration Span
Gain Calibration Span

NOTES

1

Temperature ranges as follows: A Version, –40°C to +125°C; K Version, 0°C to 125°C.

2

Specifications apply after calibration.

3

SNR calculation includes distortion and noise components.

4

All digital inputs at DGND except for CONVST, SLEEP, CAL, and SYNC at DVDD. No load on the digital outputs. Analog inputs at AGND.

5

CLKIN at DGND when external clock off. All digital inputs at DGND except for CONVST, SLEEP, CAL, and SYNC at DVDD. No load on the digital outputs.
Analog inputs at AGND.

6

The offset and gain calibration spans are defined as the range of offset and gain errors that the AD7851 can calibrate. Note also that these are voltage spans and are
not absolute voltages (i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–) ± 0.05 × V
allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted out will be V
explained in more detail in the Calibration section of the data sheet.

Specifications subject to change without notice.

6

6

+0.05 × V
+1.025 × V

/–0.05 × V

REF

/–0.975 × V

REF

REF

V max/min Allowable Offset Voltage Span for Calibration.
V max/min Allowable Full-Scale Voltage Span for Calibratio

REF

± 0.025 × V

REF

REF

). This is

REF

, and the

n.

–4–

REV. B

AD7851

1

(AV

TIMING SPECIFICATIONS

= DVDD = 5.0 V ⴞ 5%; f

DD

Descriptions that refer to SCLK↑ (rising) or SCLK↓ (falling) edges are with the POLARITY pin HIGH. For the POLARITY pin
LOW, then the opposite edge of SCLK will apply.

Limit at T

MIN

, T

MAX

Parameter (A, K Versions) Unit Description

2

f

CLKIN

3

f

SCLK

4

t

1

t

2

t

CONVERT

t

3

t

4

5

t

5

5

t

5A

5

t

6

t

7

t

8

6

t

9

6

t

10

t

11

t

11A

7

t

12

t

13

8

t

14

t

15

t

16

9

t

CAL

9

t

CAL1

9

t

CAL2

t

DELAY

NOTES

1

Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. See
Table X and timing diagrams for different interface modes and calibration.

2

Mark/space ratio for the master clock input is 40/60 to 60/40.

3

For Interface Modes 1, 2, 3, the SCLK maximum frequency will be 10 MHz. For Interface Modes 4 and 5, the SCLK will be an output and the frequency will be f

4

The CONVST pulse width will only apply for normal operation. When the part is in power-down mode, a different CONVST pulse width will apply (see Power­Down section).

5

Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.

6

For self-clocking mode (Interface Modes 4, 5), the nominal SCLK high and low times will be 0.5 t

7

The time t12 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that t12 as quoted in the timing characteristics is the true bus
relinquish time of the part and is independent of the bus loading.

8

The time t14 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics is the true
delay of the part in turning off the output drivers and configuring the DIN line as an input. Once this time has elapsed , the user can drive the DIN line knowing
that a bus conflict will not occur.

9

The typical time specified for the calibration times is for a master clock of 6 MHz.

Specifications subject to change without notice.

500 kHz min Master Clock Frequency
7 MHz max
10 MHz max Interface Modes 1, 2, 3 (External Serial Clock)
f

CLK IN

MHz max Interface Modes 4, 5 (Internal Serial Clock)

100 ns min CONVST Pulse Width
50 ns max CONVST↓ to BUSY↑ Propagation Delay

3.25 µs max Conversion Time = 20 t
–0.4 t
±0.4 t

0.6 t

SCLK

SCLK

SCLK

ns min SYNC↓ to SCLK↓ Setup Time (Noncontinuous SCLK Input)
ns min/max SYNC↓ to SCLK↓ Setup Time (Continuous SCLK Input)

ns min SYNC↓ to SCLK↓ Setup Time, Interface Mode 4 Only
30 ns max Delay from SYNC↓ until DOUT Three-State Disabled
30 ns max Delay from SYNC↓ until DIN Three-State Disabled
45 ns max Data Access Time after SCLK↓
30 ns min Data Setup Time prior to SCLK↑
20 ns min Data Valid to SCLK Hold Time

0.4 t

0.4 t

SCLK

SCLK

ns min SCLK High Pulse Width (Interface Modes 4 and 5)

ns min SCLK Low Pulse Width (Interface Modes 4 and 5)
30 ns min SCLK↑ to SYNC↑ Hold Time (Noncontinuous SCLK)
30/0.4 t

SCLK

ns min/max (Continuous SCLK) Does Not Apply to Interface Mode 3
50 ns max SCLK↑ to SYNC↑ Hold Time
50 ns max Delay from SYNC↑ until DOUT Three-State Enabled
90 ns max Delay from SCLK↑ to DIN Being Configured as Output
50 ns max Delay from SCLK↑ to DIN Being Configured as Input

2.5 t

2.5 t

CLKIN

CLKIN

ns max CAL↑ to BUSY↑ Delay

ns max CONVST↓ to BUSY↑ Delay in Calibration Sequence

41.7 ms typ Full Self-Calibration Time, Master Clock Dependent

37.04 ms typ Internal DAC Plus System Full-Scale Calibration Time, Master Clock

4.63 ms typ System Offset Calibration Time, Master Clock Dependent

65 ns max Delay from CLK to SCLK

= 6 MHz, TA = T

CLKIN

(250026 t

CLKIN

)

Dependent (222228 t

(27798 t

CLKIN

)

= 0.5 t

SCLK

to T

MIN

CLKIN

CLKIN

, unless otherwise noted.)

MAX

)

.

CLKIN

CLKIN

.

REV. B

–5–

AD7851

TYPICAL TIMING DIAGRAMS

Figures 2 and 3 show typical read and write timing diagrams.
Figure 2 shows the reading and writing after conversion in
Interface Modes 2 and 3. To attain the maximum sample rate of
285 kHz in Interface Modes 2 and 3, reading and writing must
be performed during conversion. Figure 3 shows the timing dia­gram for Interface Modes 4 and 5 with sample rate of 285 kHz.
At least a 330 ns acquisition time must be allowed (the time
from the falling edge of BUSY to the next rising edge of
CONVST) before the next conversion begins to ensure that the
part is settled to the 14-bit level. If the user does not want to
provide the CONVST signal, the conversion can be initiated in
software by writing to the control register.

t

= 3.25µs MAX, t1 = 100ns MIN,

CONVERT

= 30ns MAX, t7 = 30ns MIN

t

5

15

t

6

DB15

t

7

DB15 DB0

CONVST (I/P)

BUSY (O/P)

SYNC (I/P)

SCLK (I/P)

DOUT (O/P)

DIN (I/P)

POLARITY PIN LOGIC HIGH

t

1

t

2

THREE-STATE

t

CONVERT

t

3

t

5

1.6mA

I

OL

TO

OUTPUT

PIN

50pF

C

L

200µA

I

OH

Figure 1. Load Circuit for Digital Output Timing
Specifications

t

9

6

t

10

t

6

t

8

DB11

t

11

16

t

12

THREE-STATE

DB0DB11

2.1V

Figure 2. Timing Diagram (Typical Read and Write Operation for Interface Modes 2, 3)

t

= 3.25µs MAX, t1 = 100ns MIN,

CONVERT

= 30ns MAX, t7 = 30ns MIN

t

5

t

CONVERT

t

9

t

6

DB11

t

11

6

t

10

16

t

12

DB0DB11

THREE-STATE

CONVST (I/P)

BUSY (O/P)

SYNC (O/P)

SCLK (O/P)

DOUT (O/P)

DIN (I/P)

POLARITY PIN LOGIC HIGH

t

1

t

2

t

5

THREE-STATE

t

7

DB15 DB0

t

4

15

DB15

t

8

Figure 3. Timing Diagram (Typical Read and Write Operation for Interface Modes 4, 5)

–6–

REV. B

AD7851

ABSOLUTE MAXIMUM RATINGS

1

(TA = 25°C, unless otherwise noted.)

AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DV

DD

AV

to DVDD . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

DD

Analog Input Voltage to AGND . . . . . –0.3 V to AV

Digital Input Voltage to DGND . . . . –0.3 V to DV

Digital Output Voltage to DGND . . . –0.3 V to DV
REFIN/REF
Input Current to Any Pin Except Supplies

to AGND . . . . . . . . . . –0.3 V to AVDD + 0.3 V

OUT

2

. . . . . . . . . ± 10 mA

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

DD

Operating Temperature Range

Commercial (A, K Versions) . . . . . . . . . . . –40°C to +125°C

Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

PDIP Package, Power Dissipation . . . . . . . . . . . . . . . . 450 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 105°C/W

θ

JA

Thermal Impedance . . . . . . . . . . . . . . . . . . . . .34.7°C/W

θ

JC

Lead Temperature, (Soldering, 10 secs) . . . . . . . . . . 260°C

SOIC, SSOP Package, Power Dissipation . . . . . . . . . 450 mW

Thermal Impedance . . 75°C/W (SOIC), 122.28°C/W (SSOP)

θ

JA

Thermal Impedance . . . 25°C/W (SOIC), 31.25°C/W (SSOP)

θ

JC

ORDERING GUIDE

Linearity

Temperature Error Throughput Throughput Package

Model Range (LSB)

2

Lead Temperature, Soldering

Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >1.5 kV

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

Transient currents of up to 100 mA will not cause SCR latch-up.

PINOUT FOR DIP, SOIC, AND SSOP

CONVST

REF

IN

1

BUSY

SLEEP

/REF

AGND

C

C

AIN(+)

AIN(–)

AGND

AV

REF

REF

OUT

DD

NC

1

2

3

4

5

6

7

1

8

2

9

10

11

12

AD7851

TOP VIEW

(Not to Scale)

NC = NO CONNECT

24

23

22

21

20

19

18

17

16

15

14

13

SYNC

SCLK

CLKIN

DIN

DOUT

DGND

DV

DD

CAL

SM2

SM1

POLARITY

AMODE

Rate (kSPS) at 125ⴗC (kSPS) Description Options

3

AD7851AN –40°C to +85°C ±2 333 238 PDIP N-24
AD7851KN 0°C to 85°C ± 1 285 238 PDIP N-24
AD7851AR –40°C to +85°C ± 2 333 238 SOIC R-24
AD7851AR-REEL –40°C to +85°C ± 2 333 238 SOIC R-24
AD7851ARZ
AD7851ARZ-REEL

3

3

–40°C to +85°C ± 2 333 238 SOIC R-24

–40°C to +85°C ± 2 333 238 SOIC R-24
AD7851KR 0°C to 85°C ± 1 285 238 SOIC R-24
AD7851KR-REEL 0°C to 85°C ± 1 285 238 SOIC R-24
AD7851KRZ
AD7851KRZ-REEL

3

3

0°C to 85°C ± 1 285 238 SOIC R-24

0°C to 85°C ± 1 285 238 SOIC R-24
AD7851ARS –40°C to +85°C ± 2 333 238 SSOP RS-24
AD7851ARS-REEL –40°C to +85°C ± 2 333 238 SSOP RS-24
EVAL-AD7851CB
EVAL-CONTROL BRD2

NOTES

1

Both A and K Grades are guaranteed up to 125°C, but at a lower throughput of 238 kHz (5 MHz).

2

Linearity error refers to the integral linearity error.

3

Z = Pb-free part.

4

This can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BOARD for evaluation/demonstration purposes.

5

This board is a complete unit allowing a PC to control and communicate with all Analog Devices, Inc. evaluation boards ending in the CB designators. To order a
complete evaluation kit, the particular ADC evaluation board needs to be ordered, e.g., EVAL-AD7851CB, the EVAL-CONTROL BRD2, and a 12 V ac trans­former. See the Evaluation Board application note for more information.

4

5

Evaluation Board
Controller Board

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD7851 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

REV. B

–7–

AD7851

TERMINOLOGY

Integral Nonlinearity

This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The end­points of the transfer function are zero scale, a point 1/2 LSB
below the first code transition, and full scale, a point 1/2 LSB
above the last code transition.

Differential Nonlinearity

This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.

Total Unadjusted Error

This is the deviation of the actual code from the ideal code tak­ing all errors into account (gain, offset, integral nonlinearity, and
other errors) at any point along the transfer function.

Unipolar Offset Error

This is the deviation of the first code transition (00 . . . 000 to
00 . . . 001) from the ideal AIN(+) voltage (AIN(–) + 1/2 LSB)
when operating in unipolar mode.

Positive Full-Scale Error

This applies to unipolar and bipolar modes and is the deviation of
the last code transition from the ideal AIN(+) voltage (AIN(–) +
full scale – 1.5 LSB) after the offset error has been adjusted out.

Negative Full-Scale Error

This applies to bipolar mode only and is the deviation of the
first code transition (10 . . . 000 to 10 . . . 001) from the ideal
AIN(+) voltage (AIN(–) – V

Bipolar Zero Error

/2 + 0.5 LSB).

REF

This is the deviation of the midscale transition (all 1s to all 0s)
from the ideal AIN(+) voltage (AIN(–) – 1/2 LSB).

Track-and-Hold Acquisition Time

The track-and-hold amplifier returns into track mode at the end
of conversion. Track-and-hold acquisition time is the time
required for the output of the track-and-hold amplifier to reach
its final value, within ±1/2 LSB, after the end of conversion.

Signal-to-(Noise + Distortion) Ratio

This is the measured ratio of signal-to-(noise + distortion) at
the output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (f

/2), excluding dc. The ratio is

S

dependent on the number of quantization levels in the digitiza­tion process; the more levels, the smaller the quantization noise.
The theoretical signal-to-(noise + distortion) ratio for an ideal
N-bit converter with a sine wave input is given by

Signal-to-(Noise + Distortion) = (6.02 N +1.76)dB

Thus, for a 14-bit converter, this is 86 dB.

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7851, it is defined as

2

THD

(d ) 20logB =

VVVVV

++++

()

223242526

V

1

where V1 is the rms amplitude of the fundamental and V2, V3,
V

, V5, and V6 are the rms amplitudes of the second through the

4

sixth harmonics.

Peak Harmonic or Spurious Noise

Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to f

/2 and excluding dc) to the rms value of the

S

fundamental. Normally, the value of this specification is deter­mined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor, it will be a
noise peak.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are
those for which neither m nor n are equal to zero. For example,
the second-order terms include (fa + fb) and (fa – fb), while the
third-order terms include (2fa + fb), (2fa – fb), (fa + 2fb), and
(fa – 2fb).

Testing is performed using the CCIF standard where two
input frequencies near the top end of the input bandwidth are
used. In this case, the second-order terms are usually distanced
in frequency from the original sine waves while the third-order
terms are usually at a frequency close to the input frequencies.
As a result, the second- and third-order terms are specified
separately. The calculation of the intermodulation distortion is
as per the THD specification where it is the ratio of the rms
sum of the individual distortion products to the rms amplitude
of the sum of the fundamentals expressed in dBs.

Power Supply Rejection Ratio (PSRR)

PSRR is defined as the ratio of the power in ADC output at fre­quency f to the power of the full-scale sine wave applied to the
supply voltage (V

). The units are in LSB, % of FS per % of

DD

supply voltage, or expressed logarithmically, in dB (PSRR (dB)
= 10 log (Pf/Pfs)).

Full Power Bandwidth (FPBW)

FPBW is that frequency at which the amplitude of the recon­structed fundamental (using FFTs and neglecting harmonics
and SNR) is reduced by 3 dB for a full-scale input.

–8–

REV. B

AD7851

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Description

1 CONVST Convert Start. Logic input. A low-to-high transition on this input puts the track-and-hold into its hold

mode and starts conversion. When this input is not used, it should be tied to DV

2 BUSY Busy Output. The busy output is triggered high by the falling edge of CONVST or rising edge of CAL and

remains high until conversion is completed. BUSY is also used to indicate when the AD7851 has completed
its on-chip calibration sequence.

3 SLEEP Sleep Input/Low Power Mode. A Logic 0 initiates a sleep and all circuitry is powered down, including the

internal voltage reference, provided there is no conversion or calibration being performed. Calibration data
is retained. A Logic 1 results in normal operation. See Power-Down section for more details.

4 REF

/Reference Input/Output. This pin is connected to the internal reference through a series resistor and is the

IN

REF

OUT

reference source for the analog-to-digital converter. The nominal reference voltage is 4.096 V and this appears
at the pin. This pin can be overdriven by an external reference or can be taken as high as AV

5AV

DD

pin is tied to AV
be tied to AV

Analog Positive Supply Voltage, 5.0 V ± 5%.

, or when an externally applied reference approaches VDD, then the C

DD

.

DD

6, 12 AGND Analog Ground. Ground reference for track and hold, reference, and DAC.

7C

REF1

Reference Capacitor (0.1 µF ceramic disc in parallel with a 470 nF tantalum). This external capacitor is
used as a charge source for the internal DAC. The capacitor should be tied between the pin and AGND.

8C

REF2

Reference Capacitor (0.01 µF ceramic disc). This external capacitor is used in conjunction with the on-chip
reference. The capacitor should be tied between the pin and AGND.

9 AIN(+) Analog Input. Positive input of the pseudo-differential analog input. Cannot go below AGND or above

AV

at any time and cannot go below AIN(–) when the unipolar input range is selected.

DD

10 AIN(–) Analog Input. Negative input of the pseudo-differential analog input. Cannot go below AGND or above

at any time.

AV

DD

11 NC No Connect Pin.

13 AMODE Analog Mode Pin. This pin allows two different analog input ranges to be selected. A Logic 0 selects range

0 to V

(i.e., AIN(+) – AIN(–) = 0 to V

REF

cannot go below AGND. A Logic 1 selects range –V
+V

/2). In this case, AIN(+) cannot go below AGND so that AIN(–) needs to be biased to +V

REF

allow AIN(+) to go from 0 V to +V

REF

). In this case, AIN(+) cannot go below AIN(–) and AIN(–)

REF

/2 to +V

REF

/2 (i.e., AIN(+) – AIN(–) = –V

REF

V.

14 POLARITY Serial Clock Polarity. This pin determines the active edge of the serial clock (SCLK). Toggling this pin will

reverse the active edge of the serial clock (SCLK). A Logic 1 means that the serial clock (SCLK) idles high
and a Logic 0 means that the serial clock (SCLK) idles low. It is best to refer to the timing diagrams and
Table IX for the SCLK active edges.

15 SM1 Serial Mode Select Pin. This pin is used in conjunction with the SM2 pin to give different modes of opera-

tion as described in Table X.

16 SM2 Serial Mode Select Pin. This pin is used in conjunction with the SM1 pin to give different modes of opera-

tion as described in Table X.

17 CAL Calibration Input. This pin has an internal pull-up current source of 0.15 µA. A Logic 0 on this pin resets all

calibration control logic and initiates a calibration on its rising edge. There is the option of connecting a 10 nF
capacitor from this pin to DGND to allow for an automatic self-calibration on power-up. This input overrides
all other internal operations. If the autocalibration is not required, then this pin should be tied to a logic high.

18 DV

DD

Digital Supply Voltage, 5.0 V ± 5%.

19 DGND Digital Ground. Ground reference point for digital circuitry.

20 DOUT Serial Data Output. The data output is supplied to this pin as a 16-bit serial word.

21 DIN Serial Data Input. The data to be written is applied to this pin in serial form (16-bit word). This pin can act as

an input pin or as a input and output pin depending on the serial interface mode the part is in (see Table X).

22 CLKIN Master Clock Signal for the Device (6 MHz or 7 MHz). Sets the conversion and calibration times.

23 SCLK Serial Port Clock. Logic input/output. The SCLK pin is configured as an input or output, dependent on the

type of serial data transmission (self-clocking or external-clocking) that has been selected by the SM1 and
SM2 pins. The SCLK idles high or low depending on the state of the POLARITY pin.

24 SYNC This pin can be an input level triggered active low (similar to a chip select in one case and to a frame sync

in the other) or an output (similar to a frame sync) pin depending on SM1, SM2 (see Table X).

DD

.

. When this

DD

pin should also

REF1

/2 to

REF

/2 to

REF

REV. B

–9–

AD7851

AD7851 ON-CHIP REGISTERS

The AD7851 powers up with a set of default conditions, and the user need not ever write to the device. In this case, the AD7851 will
operate as a read-only ADC. The AD7851 still retains the flexibility for performing a full power-down and a full self-calibration.
Note that the DIN pin should be tied to DGND for operating the AD7851 as a read-only ADC.

Extra features and flexibility, such as performing different power-down options, different types of calibrations, including system cali­bration, and software conversion starts can be selected by writing to the part.

The AD7851 contains a control register, ADC output data register, status register, test register, and 10 calibration registers.
The control register is write-only, the ADC output data register and the status register are read-only, and the test and calibration
registers are both read/write registers. The test register is used for testing the part and should not be written to.

Addressing the On-Chip Registers

Writing

A write operation to the AD7851 consists of 16 bits. The two MSBs, ADDR0 and ADDR1, are decoded to determine which regis­ter is addressed, and the subsequent 14 bits of data are written to the addressed register. It is not until all 16 bits are written that
the data is latched into the addressed register. Table I shows the decoding of the address bits, while Figure 4 shows the overall
write register hierarchy.

Table I. Write Register Addressing

ADDR1 ADDR0 Comment

00This combination does not address any register so the subsequent 14 data bits are ignored.
01This combination addresses the TEST REGISTER. The subsequent 14 data bits are written to the test register.
10This combination addresses the CALIBRATION REGISTERS. The subsequent 14 data bits are written

to the selected calibration register.

11This combination addresses the CONTROL REGISTER. The subsequent 14 data bits are written to the

control register.

Reading

To read from the various registers the user must first write to Bits 6 and 7 in the Control Register, RDSLT0 and RDSLT1. These
bits are decoded to determine which register is addressed during a read operation. Table II shows the decoding of the read address
bits while Figure 5 shows the overall read register hierarchy. The power-up status of these bits is 00 so that the default read will be
from the ADC output data register.

Once the read selection bits are set in the control register, all subsequent read operations that follow will be from the selected register
until the read selection bits are changed in the control register.

Table II. Read Register Addressing

RDSLT1 RDSLT0 Comment

00All successive read operations will be from ADC OUTPUT DATA REGISTER. This is the power-up default

setting. There will always be two leading zeros when reading from the ADC output data register.
01All successive read operations will be from TEST REGISTER.
10All successive read operations will be from CALIBRATION REGISTERS.
11All successive read operations will be from STATUS REGISTER.

RDSLT1, RDSLT0

DECODE

CALIBRATION

REGISTERS

GAIN (1)

OFFSET (1)

STATUS

REGISTER

OFFSET (1) GAIN (1)

CALSLT1, CALSLT0

DECODE

ADDR1, ADDR0

DECODE

01 10 11

TEST

REGISTER

GAIN (1)

OFFSET (1)

DAC (8)

00 01 10 11

CALIBRATION

REGISTERS

GAIN (1)

OFFSET (1)

OFFSET (1) GAIN (1)

CONTROL

REGISTER

00

ADC OUTPUT

DATA REGISTER

CALSLT1, CALSLT0

DECODE

01 10 11

TEST

REGISTER

GAIN (1)

OFFSET (1)

DAC (8)

00 01 10 11

Figure 4. Write Register Hierarchy/Address Decoding

–10–

Figure 5. Read Register Hierarchy/Address Decoding

REV. B

AD7851

CONTROL REGISTER

The arrangement of the control register is shown below. The control register is a write-only register and contains 14 bits of data. The
control register is selected by putting two 1s in ADDR1 and ADDR0. The function of the bits in the control register are described
below. The power-up status of all bits is 0.

MSB

ZERO ZERO ZERO ZERO PMGT1 PMGT0 RDSLT1

RDSLT0

Bit No. Mnemonic Comment

13 ZERO These four bits must be set to 0 when writing to the control register.
12 ZERO
11 ZERO
10 ZERO

9PMGT1 Power Management Bits. These two bits are used with the SLEEP pin for putting the part into various
8PMGT0 power-down modes (see Power-Down section for more details).

7 RDSLT1 Theses two bits determine which register is addressed for the read operations. See Table II.
6 RDSLT0

52/3 MODE Interface Mode Select Bit. With this bit set to 0, Interface Mode 2 is enabled. With this bit set to 1,

4 CONVST Conversion Start Bit. A Logic 1 in this bit position starts a single conversion, and this bit is automati-

3 CALMD Calibration Mode Bit. A 0 here selects self-calibration and a 1 selects a system calibration (see Table III).

2 CALSLT1 Calibration Selection Bits and Start Calibration Bit. These bits have two functions:
1 CALSLT0 With the STCAL bit set to 1, the CALSLT1 and CALSLT0 bits determine the type of calibration per­0 STCAL formed by the part (see Table III). The STCAL bit is automatically reset to 0 at the end of calibration.

2/3 MODE

Interface Mode 1 is enabled where DIN is used as an output as well as an input. This bit is set to 0 by
default after every read cycle; thus when using Interface Mode 1, this bit needs to be set to 1 in every
write cycle.

cally reset to 0 at the end of conversion. This bit may also be used in conjunction with system calibration
(see Calibration section).

With the STCAL bit set to 0, the CALSLT1 and CALSLT0 bits are decoded to address the calibration
register for read/write of calibration coefficients (see section on Calibration Registers for more details).

CONVST CALMD CALSLT1 CALSLT0 STCAL

LSB

Control Register Bit Function Descriptions

Table III. Calibration Selection

CALMD CALSLT1 CALSLT0 Calibration Type

00 0 A full internal calibration is initiated where the internal DAC is calibrated followed by the

internal gain error, and finally the internal offset error is calibrated out. This is the default setting.

00 1 Here the internal gain error is calibrated out followed by the internal offset error calibrated

out.

01 0This calibrates out the internal offset error only.

01 1This calibrates out the internal gain error only.

10 0 A full system calibration is initiated here where first the internal DAC is calibrated, fol-

lowed by the system gain error, and finally the system offset error is calibrated out.

10 1Here the system gain error is calibrated out followed by the system offset error.

11 0This calibrates out the system offset error only.

11 1This calibrates out the system gain error only.

REV. B

–11–