Analog Devices AD7724 b Datasheet

a

Dual CMOS ⌺-⌬ Modulators

AD7724

FEATURES
13 MHz Master Clock Frequency
0 V to +2.5 V or ⴞ1.25 V Input Range
Single Bit Output Stream
90 dB Dynamic Range
Power Supplies

AVDD, DVDD: 5 V ⴞ 5%

DVDD1: 3 V ⴞ 5%
Logic Outputs 3 V/5 V Compatible
On-Chip 2.5 V Voltage Reference
48-Lead LQFP

GENERAL DESCRIPTION

This device consists of two seventh order sigma-delta modula­tors. Each modulator converts its analog input signal into a high
speed 1-bit data stream. The part operates from a 5 V power
supply and accepts a differential input range of 0 V to +2.5 V or
±1.25 V centered about a common-mode bias. The analog inputs
are continuously sampled by the analog modulators, eliminating
the need for external sample-and-hold circuitry. The input
information is contained in the output stream as a density of
ones. The original information can be digitally reconstructed
with an appropriate digital filter.

The part provides an accurate on-chip 2.5 V reference for each
modulator. A reference input/output function is provided to
allow either the internal reference or an external system refer­ence to be used as the reference source for the modulator.

The device is offered in a 48-lead LQFP package and designed
to operate from –40°C to +85°C.

AVIN(+)

AVIN(–)

BVIN(+)

BVIN(–)

MZERO

GC

BIP

STBY

RESET

FUNCTIONAL BLOCK DIAGRAM

REF1 REF2A REF2B

2.5V

REFERENCE

AD7724

⌺-

⌬

MODULATOR A

⌺-

⌬

MODULATOR B

CLOCK

CIRCUITRY

CONTROL

LOGIC

DVDD DVDD1 DGND AVDD AGND

ADATA

SCLK

BDATA

OFF

XTAL

XTAL1

XTAL2/MCLK

DVAL

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2002

1

AD7724–SPECIFICATIONS

f

= 13 MHz ac-coupled sine wave, REF2A = REF2B = 2.5 V; TA = T

MCLK

(AVDD = 5 V ⴞ 5%; DVDD = 5 V ⴞ 5%, DVDD1 = 3 V ⴞ 5%; AGND = DGND = 0 V,

to T

MIN

, unless otherwise noted.)

MAX

Parameter A Version Unit Test Conditions/Comments

STATIC PERFORMANCE When Tested with Ideal FIR Filter as in Figure 1

Integral Nonlinearity ±0.003 % FSR typ
Offset Error ±0.24 % FSR typ
Gain Error

2

±0.6 % FSR typ

Offset Error Drift ±37.69 µV/°C typ
Gain Error Drift REF2 Is an Ideal Reference, REF1 = AGND

Unipolar Mode ±37.69 µV/°C typ
Bipolar Mode ±18.85 µV/°C typ

ANALOG INPUTS

Signal Input Span (VIN(+) – VIN(–))

Bipolar Mode ±V
Unipolar Mode 0 to V

/2 V max BIP = V

REF2

REF2

V max BIP = V

IH

IL

Maximum Input Voltage AVDD V
Minimum Input Voltage 0 V
Input Sampling Capacitance 2 pF typ
Input Sampling Rate 2 f

MCLK

Differential Input Impedance 109/(8 f

MCLK

MHz

)kΩ typ

REFERENCE INPUTS

REF1 Output Voltage 2.32 to 2.68 V min/max
REF1 Output Voltage Drift 60 ppm/°C typ
REF1 Output Impedance 4 kΩ typ
Reference Buffer Offset Voltage ±12 mV max Offset Between REF1 and REF2
Using Internal Reference

REF2 Output Voltage 2.32 to 2.68 V min/max
REF2 Output Voltage Drift 60 ppm/°C typ

Using External Reference REF1 = AGND

REF2 Input Impedance 10

9

/(16 f

MCLK

)kΩ typ

External Reference Voltage Range 2.32 to 2.68 V min/max Applied to REF1 or REF2

DYNAMIC SPECIFICATIONS

3

Bipolar Mode BIP = V

When Tested with Ideal FIR Filter as in Figure 1

, VCM = 2.5 V, VIN(+) = VIN(–) = 1.25 V p-p

IH

or VIN(–) = 1.25 V, VIN(+) = 0 V to 2.5 V

Signal-to-(Noise + Distortion) 90 dB typ Input BW = 0 kHz–94.25 kHz

86 dB min
Total Harmonic Distortion –90 dB max Input BW = 0 kHz–94.25 kHz
Spurious Free Dynamic Range –90 dB max Input BW = 0 kHz–94.25 kHz

Unipolar Mode BIP = V

, VIN(–) = 0 V, VIN(+) = 0 V to 2.5 V

IL

Signal-to-(Noise + Distortion) 88 dB typ Input BW = 0 kHz–94.25 kHz
Total Harmonic Distortion –90 dB typ Input BW = 0 kHz–101.556 kHz
Spurious Free Dynamic Range –90 dB typ Input BW = 0 kHz–101.556 kHz
Intermodulation Distortion –93 dB typ

AC CMRR 96 dB typ VIN(+) = VIN(–) = 2.5 V p-p, V

= 1.25 V to

CM

3.75 V, 20 kHz

CLOCK

Square Wave

4

MCLK Duty Ratio 45 to 55 % max For Specified Operation
V
V

, MCLK High Voltage 4 V min MCLK Uses CMOS Logic

MCLKH

, MCLK Low Voltage 0.4 V max

MCLKL

Sine Wave

XTAL1 Voltage Swing 0.4 V p-p min XTAL_OFF Tied Low

4 V p-p max

LOGIC INPUTS

VIH, Input High Voltage 2.4 V min

, Input Low Voltage 0.8 V max

V

IL

I

, Input Current 10 µA max

INH

CIN, Input Capacitance 10 pF max

–2–

REV. B

Parameter A Version Unit Test Conditions/Comments

LOGIC OUTPUTS

, Output High Voltage DVDD1 – 0.2 V min |I

V

OH

VOL, Output Low Voltage 0.4 V max |I

| ≤ 200 µA

OUT

| ≤ 1.6 mA

OUT

POWER SUPPLIES

AVDD/DVDD 4.75/5.25 V min/V max
DVDD1 2.85/5.25 V min/V max

(Total for AVDD, DVDD) Digital Inputs Equal to 0 V or DVDD

I

DD

Active Mode 60 mA max
Standby Mode 20 µA max

NOTES

1

Operating temperature range is as follows: A Version: –40°C to +85°C.

2

Gain Error excludes reference error. The modulator gain is calibrated wrt the voltage on the REF2 pin.

3

Measurement Bandwidth = 0.5 × f

4

When a square wave clock is used, the dynamic specifications will degrade by 1 dB typically.

Specifications subject to change without notice.

; Input Level = –0.05 dB.

MCLK

AD7724

BIT STREAM

94.25kHz

FILTER 1

BANDWIDTH = 94.25kHz
TRANSITION = 304.687kHz
ATTENUATION = 120dB
COEFFICIENTS = 384

304.687kHz

120dB

DECIMATE

BY 32

94.25kHz

FILTER 2

BANDWIDTH = 94.25kHz
TRANSITION = 108.874kHz
ATTENUATION = 90dB
COEFFICIENTS = 151

108.874kHz

90dB

DECIMATE

BY 2

16-BIT

OUTPUT

Figure 1. Digital Filter (Consists of Two FIR Filters). This Filter is Implemented on the AD7722.

REV. B –3–

AD7724

(AVDD = 5 V ⴞ 5%; DVDD = 5 V ⴞ 5%; DVDD1 = 3 V ⴞ 5%; AGND = DGND = 0 V, REF2A =

1, 2

TIMING CHARACTERISTICS

Limit at T

Parameter (A Version) Unit Conditions/Comments

f

MCLK

100 kHz min Master Clock Frequency
15 MHz max 13 MHz for Specified Performance

t

DELAY

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

NOTES

1

Sample tested at 25°C to ensure compliance.

2

Guaranteed by design.

14 ns max MCLK to SCLK Delay
67 ns min Master Clock Period

0.45 × t

0.45 × t
15 ns min Data Hold Time After SCLK Rising Edge
10 ns min RESET Pulsewidth
10 ns min RESET Low Time Before MCLK Rising
20 × t
3 ns max Data Access Time After SCLK Falling Edge
t3–t

MIN

MCLK

MCLK

MCLK

8

REF2B = 2.5 V, unless otherwise noted.)

, T

MAX

ns min Master Clock Input High Time
ns min Master Clock Input Low Time

ns max DVAL High Delay After RESET Low

ns max Data Valid Time Before SCLK Rising Edge

I

OL

1.6mA

SCLK (O)

DATA (O)

NOTE:
O SIGNIFIES AN OUTPUT

MCLK (I)

RESET (I)

DVAL (O)

TO

OUTPUT

PIN

50pF

C

L

I

OH

200␮A

1.6V

Figure 2. Load Circuit for Access Time and Bus Relinquish Time

t

1

t

t

3

t

8

2

t

t

4

9

Figure 3. Data Timing

t

6

t

5

t

7

NOTE:
I SIGNIFIES AN INPUT
O SIGNIFIES AN OUTPUT

Figure 4. RESET Timing

–4–

REV. B

AD7724

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

*

(TA = 25°C unless otherwise noted)

DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . –1 V to +1 V

AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

Digital Inputs to DGND . . . . . . . . –0.3 V to DVDD + 0.3 V

Digital Outputs to DGND . . . . . . . –0.3 V to DVDD + 0.3 V

VIN(+), VIN(–) to AGND . . . . . . . –0.3 V to AVDD + 0.3 V

REF1 to AGND . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V

REF2 to AGND . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V

REFIN to AGND . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V

Operating Temperature Range . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 75°C/W

θ

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

ORDERING GUIDE

AVDD

AGND

AVIN(–)

NC

AVIN(+)

AGND

AVDD

NC

STBY

MZERO

RESET

NC

NC = NO CONNECT

PIN CONFIGURATION

NCNCAGND

REF2A

AGND

REF1

AD7724

TOP VIEW

(Not to Scale)

DVDD

DGND

DGND

AVDDNCREF2B

ADATA

BDATA

48 47 46 45 44 39 38 3743 42 41 40

1

PIN 1

2

IDENTIFIER

3

4

5

6

7

8

9

10

11

12

13 14 15 16 17 18 19 20 21 22 23 24

NC

XTAL1

XTAL1/MCLK

AGNDNCNC

SCLK

DVDD1

DVAL

NC

36

AVDD

35

AGND

34

BVIN(–)

33

NC

32

BVIN(+)

31

AGND

30

AVDD

29

NC

28

GC

27

BIP

26

XTAL_OFF

25

NC

Temperature Package Package

Model Range Description Option

AD7724AST –40°C to +85°C 48-Lead Plastic Thin Quad Flatpack (LQFP) ST-48

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7724 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

REV. B

–5–