643 Oversampling Ratio
Up to 220 kSPS Output Word Rate
Low-Pass, Linear Phase Digital Filter
Inherently Monotonic
On-Chip 2.5 V Voltage Reference
Single Supply +5 V
High Speed Parallel or Serial Interface
GENERAL DESCRIPTION
The AD7722 is a complete low power, 16-bit, sigma-delta
ADC. The part operates from a +5 V supply and accepts a
differential input voltage range of 0 V to +2.5 V or ± 1.25 V
centered around a common-mode bias. The AD7722 provides
16-bit performance for input bandwidths up to 90.625 kHz.
The part provides data at an output word rate of 195.3 kHz.
The analog input is continuously sampled by an analog modulator eliminating the need for external sample-and-hold circuitry.
The modulator output is processed by two Finite Impulse
Response (FIR) digital filters in series. The on-chip filtering
reduces the external antialias requirements to first order, in
most cases. The group delay for the filter is 215.5 µs, while the
settling time for a step input is 431 µs. The sample rate, filter
corner frequency, and output word rate are set by an external
clock that is nominally 12.5 MHz.
Use of a single bit DAC in the modulator guarantees excellent
linearity and dc accuracy. Endpoint accuracy is ensured by onchip calibration. This calibration procedure minimizes the zeroscale and full-scale errors.
CMOS, Sigma-Delta ADC
AD7722
FUNCTIONAL BLOCK DIAGRAM
Conversion data is provided at the output register through a
flexible serial port or a parallel port. This offers 3-wire, high
speed interfacing to digital signal processors. The serial interface
operates in an internal clocking (master) mode, whereby an
internal serial data clock and framing pulse are device outputs.
Additionally, two AD7722s can be configured with the serial
data outputs connected together. Each converter alternately
transmits its conversion data on a shared serial data line.
The part provides an accurate on-chip 2.5 V reference. A
reference input/output function is provided to allow either the
internal reference or an external system reference to be used as
the reference source for the part.
The AD7722 is available in a 44-pin PQFP package and is
specified over the industrial temperature range from –40°C to
+85°C.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7722 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. 0
–3–
AD7722
(AVDD= +5 V 6 5%, DVDD = +5 V 6 5%, AGND = DGND = 0 V, CL = 50 pF, TA = T
f
TIMING SPECIFICATIONS
= 12.5 MHz, SFMT = Logic Low or High, CFMT = Logic Low or High)
CLKIN
CLKIN Frequencyf
CLKIN Period (t
CLK
= 1/f
)t
CLK
CLKIN Low Pulse Widtht
CLKIN High Pulse Widtht
CLKIN Rise Timet
CLKIN Fall Timet
FSI Low Timet
FSI Setup Timet
FSI Hold Timet
CLKIN to SCO Delayt
SCO Period
1
SCO Transition to FSO High Delayt
SCO Transition to FSO Low Delayt
SCO Transition to SDO Valid Delayt
SCO Transition from FSI
2
SDO Enable Delay Timet
SDO Disable Delay Timet
DRDY High Timet
Conversion Time
1
DRDY to CS Setup Timet
CS to RD Setup Timet
RD Pulse Widtht
Data Access Time after
Bus Relinquish Time after
RD Falling Edge
RD Rising Edget
3
CS to RD Hold Timet
RD to DRDY High Timet
SYNC/RESET Input Pulse Widtht
DVAL Low Delay from SYNC/RESETt
SYNC/RESET Low Time Before CLKIN Risingt
DRDY High Delay after SYNC/RESET Lowt
DRDY Low Delay after SYNC/RESET Low1t
DVAL High Delay after SYNC/RESET Low1t
CAL Setup Timet
CAL Pulse Widtht
Calibration Delay from CAL Hight
Unipolar Input Calibration Time, (UNI = “0”)1t
Bipolar Input Calibration Time, (UNI = “1”)1t
Conversion Results Valid, (UNI = “0”)
Conversion Results Valid, (UNI = “1”)
NOTES
1
Guaranteed by design.
2
Frame Sync is initiated on falling edge of CLKIN.
3
With RD synchronous to CLKIN t22, can be reduced up to 1 t
ZERO FOR LAST 16 SCO CYCLESVALID DATA FOR 16 SCO CYCLESVALID
Figure 2a. Generalized Serial Mode Timing (FSI = Logic Low or High, TSI = DOE)
64 CKLIN CYCLES
CLKIN
SCO
(CFMT = 0)
FSO
(SFMT = 1)
SCO
LOW FOR 16 SCO CYCLES
VALID DATA FOR 16 SCO CYCLES
32 SCO CYCLES
HIGH FOR LAST 16 SCO CYCLES
ZERO FOR LAST 16 SCO CYCLES
Figure 2b. Generalized Serial Mode Timing (FSI = Logic Low or High, TSI = DOE)
t
4
t
t
8
t
9
t
10
t
7
3
t
2
CLKIN
FSI
SCO
2.3V
t
5
0.8V
t
1
t
6
t
9
VALID
Figure 3. Serial Mode Timing for Clock Input, Frame Sync Input and Serial Clock Output
CLKIN
t
1
FSI
t
10
SCO
SFMT = LOGIC
LOW(0)
SFMT = LOGIC
HIGH(1)
FSO
SDO
SCO
FSO
SDO
LOW FOR
D15–D0
t
11
t
14
t
12
t
13
D15D14D13D1D0
t
12
D15D14D13D1D0
t
13
t
11
Figure 4. Serial Mode Timing for Frame Sync Input, Frame Sync Output, Serial Clock Output
and Serial Data Output (CFMT = Logic Low, TSI = DOE)
REV. 0
–5–
AD7722
DOE
t
16
SDO
t
15
Figure 5. Serial Mode Timing for Data Output Enable and Serial Data Output (TSI = Logic Low)
DRDY
t
17
t
19
t
18
t
25
DB0 – DB15
CLKIN
SYNC, RESET
DVAL
DRDY
CLKIN
CAL
DVAL
DRDY
CS
RD
t
20
t
21
t
22
VALID DATA
t
24
t
23
Figure 6. Parallel Mode Read Timing
t
30
t
t
28
t
t
27
26
t
29
31
Figure 7. SYNC and RESET Timing, Serial and Parallel Mode
t
36
t
34
t
35
t
37
t
38
Figure 8. Calibration Timing, Serial and Parallel Mode
–6–
REV. 0
PIN FUNCTION DESCRIPTION
MnemonicPin No.Description
AD7722
AV
DD1
14Clock logic power supply voltage for the analog modulator, +5 V ± 5%.
AGND110Clock logic ground reference for the analog modulator.
AV
DD
20, 23Analog Power Supply Voltage, +5 V ± 5%.
AGND9, 13, 15,Ground reference for analog circuitry.
19, 21, 25, 26
DV
DD
39Digital Power Supply Voltage, +5 V ± 5%.
DGND6, 28Ground reference for digital circuitry.
REF122Reference Input/Output. REF1 connects through 3 kΩ to the output of the internal 2.5 V
reference and to the input of a buffer amplifier that drives the Σ−∆ modulator. This pin can
also be overdriven with an external reference 2.5 V.
REF224Reference Input/Output. REF2 connects to the output of an internal buffer amplifier used to
to drive the Σ−∆ modulator. When REF2 is used as an input, REF1 must be connected
to AGND.
V
(+)18Positive terminal of the differential analog input.
IN
V
(–)16Negative terminal of the differential analog input.
IN
UNI7Analog input range select input. UNI selects the analog input range for either bipolar
or unipolar operation. A logic low input selects unipolar operation. A logic high input
selects bipolar operation.
CLKIN11Clock Input. Master clock signal for the device. The CLKIN pin interfaces the AD7722
internal oscillator circuit to an external crystal or to an external clock. A parallel resonant,
fundamental-frequency, microprocessor-grade crystal and a 1 MΩ resistor should be
connected between the CLKIN and XTAL pin with two capacitors connected from each
pin to ground. Alternatively, the CLKIN pin can be driven with an external CMOScompatible clock. The AD7722 is specified with a clock input frequency of 12.5 MHz.
XTAL12Oscillator Output. The XTAL pin connects the internal oscillator output to an external
crystal. If an external clock is used, XTAL should be left unconnected.
P/
S8Parallel/Serial interface select input. A logic high configures output data interface for parallel
mode operation. Serial mode operation is selected with the P/S set to a logic low.
CAL27Calibration Logic Input. A logic high input for a duration of one CLKIN cycle initiates a
calibration sequence for the device Gain and Offset Error.
RESET17Reset Logic Input. RESET is used to clear the offset and gain calibration registers. RESET is an
asynchronous input. RESET allows the user to set AD7722 to an uncalibrated state if the device
had been previously calibrated. A rising edge also resets the AD7722 Σ−∆ modulator by shorting
the integrator capacitors in the modulator. In addition RESET functions identically to the
SYNC pin described below.
CS29Chip select is a level sensitive logic input. CS enables the output data register for parallel mode
read operation. The CS logic level is sensed on the rising edge of CLKIN. The output data bus
is enabled when the rising edge of CLKIN senses a logic low level on CS if RD is also low. When
CS is sensed high, the output data bits DB15–DB0 will be high impedance. In serial mode tie
CS to a logic low.
SYNC30Synchronization Logic Input. SYNC is an asynchronous input. When using more than one
AD7722 operated from a common master clock, SYNC allows each ADC’s Σ−∆ modulator
to simultaneously sample its analog input and update its output data register. A rising edge resets
the AD7722 digital filter sequencer counter to zero. After a SYNC, conversion data is not valid
until after the digital filter settles (reference Figure 7). DVAL goes low in the serial mode. When
the rising edge of CLKIN senses a logic low on SYNC (or RESET) the reset state is released; in
parallel mode,
8192 CLKIN cycles (128 × 64/f
convolution cycle of the digital filter (64 CLKIN periods), when valid data is ready to be read
from the output data register.
DRDY goes high. After the reset state is released, DVAL returns high after
); in parallel mode, DRDY returns low after one additional
CLKIN
REV. 0
–7–
AD7722
PIN CONFIGURATION
44-Pin PQFP (S-44)
DD
DV
SCO/DB7
FSI/DB6
40 39 384142434436 35 3437
AD7722
TOP VIEW
(Not to Scale)
VIN(–)
AGND
RESET
FSO/DB9
SDO/DB8
VIN(+)
AGND
DGND/DB10
DGND/DB11
DGND/DB12
DD
REF1
AV
AGND
33
DGND/DB13
32
DGND/DB14
31
DGND/DB15
30
SYNC
CS
29
28
DGND
27
CAL
26
AGND
25
AGND
24
REF2
23
AV
DD
DGND/DB2
DGND/DB1
DGND/DB0
CFMT/DRDY
DVAL/RD
DGND
UNI
P/S
AGND
AGND1
CLKIN
TSI/DB3
SFMT/DB5
DOE/DB4
1
PIN 1
IDENTIFIER
2
3
4
5
6
7
8
9
10
11
121314 15 16 17 18 192021 22
DD1
XTAL
AGND
AV
PARALLEL MODE PIN FUNCTION DESCRIPTION
MnemonicPin No.Description
DVAL/
RD5Read Input is a level sensitive logic input. The RD logic level is sensed on the rising edge of CLKIN.
This digital input can be used in conjunction with
bus is enabled when the rising edge of CLKIN senses a logic low level on
CS to read data from the device. The output data
RD if CS is also low. When
RD is sensed high, the output data bits DB15–DB0 will be high impedance.
CFMT/
DRDY2Data Ready Logic Output. A falling edge indicates a new output word is available to be read from out-
put data register. DRDY will return high upon completion of a read operation. If a read operation
does not occur between output updates, DRDY will pulse high for two CLKIN cycles before the next
output update. DRDY also indicates when conversion results are available after a SYNC or RESET
sequence and when completing a self-calibration.
DGND/DB1531Data Output Bit (MSB)
DGND/DB1432Data Output Bit
DGND/DB1333Data Output Bit
DGND/DB1234Data Output Bit
DGND/DB1135Data Output Bit
DGND/DB1036Data Output Bit
FSO/DB937Data Output Bit
SDO/DB838Data Output Bit
SCO/DB740Data Output Bit
FSI/DB641Data Output Bit
SFMT/DB542Data Output Bit
DOE/DB443Data Output Bit
TSI/DB344Data Output Bit
DGND/DB21Data Output Bit
DGND/DB12Data Output Bit
DGND/DB03Data Output Bit (LSB)
–8–
REV. 0
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