ANALOG DEVICES AD7568 Service Manual

R B

R F

DAC A

DAC A
LATCH

INPUT

LATCH A

INPUT

LATCH B

INPUT

LATCH C

INPUT

LATCH D

INPUT

LATCH E

INPUT

LATCH F

INPUT

LATCH G

DAC B
LATCH

DAC C
LATCH

DAC D
LATCH

DAC E
LATCH

DAC F

LATCH

DAC G

LATCH

DAC B

DAC C

DAC D

DAC E

DAC F

DAC G

V B

REF

V D

REF

R G

FB

V G

REF

V F

REF

V E

REF

FB

FB

R E

R D

R C

FB

FB

R A

FBREF

V AV C

REF

V

DD

DGND

LDAC

CLR

AD7568

12

12

12

12

12

12

12

12

12

12

12

12

12

12

V H

REF

A0

CONTROL LOGIC

+

INPUT SHIFT

REGISTER

CLKIN

SDIN

SDOUT

INPUT

LATCH H

DAC H
LATCH

DAC H

R H

FB

12

12

FSIN

I A
I A

I B
I B

I C

I D

I C

I D

I E

I F

I E

I F

I G

I H

I G

I H

AGND

12

OUT1
OUT2

OUT1

OUT2

OUT1

OUT2

FB

OUT1

OUT2

OUT1

OUT2

OUT1
OUT2

OUT1
OUT2

OUT1
OUT2

LC2MOS

NC = NO CONNECT

NC
V

REF

C

V

REF

B

R

FB

B

I

OUT1

B

I

OUT1

C

NC

V

REF

F

V

REF

G

R

FB

G

R

FB

F

I

OUT2

F

I

OUT2

E

I

OUT1

E

V

DD

DGND

AGND

R

FB

E

I

OUT1

H

I

OUT2

H

LDAC

FSIN

SDIN

SDOUT

CLR

V

REF

E

R

FB

D

I

OUT1

D

A0

I

OUT2

A

I

OUT1

A

CLKIN

V

REF

D

V

REF

A

R

FB

A

I

OUT2

B

I

OUT2

G

V

REF

H

R

FB

H

I

OUT1

G

4412645

21 24

23

22182019

39
38

35
34
33

37
36

3

7
8

11
12
13

9

10

404142

25 28

27

26

43

31
30
29

32
15
16
17

14

TOP VIEW

(Not to Scale)

AD7568 PLCC

I

OUT2

D

I

OUT2

C

R

FB

C

I

OUT1

F

REV. C

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2012 Analog Devices, Inc. All rights reserved.

a

FEATURES
Eight 12-Bit DACs in One Package
4-Quadrant Multiplication
Separate References
Single +5 V Supply
Low Power: 1 mW
Versatile Serial Interface
Simultaneous Update Capability
Reset Function
44-Pin PQFP and PLCC

APPLICATIONS
Process Control
Automatic Test Equipment
General Purpose Instrumentation

GENERAL DESCRIPTION

The AD7568 contains eight 12-bit DACs in one monolithic de­vice. The DACs are standard current output with separate V
I

, I

OUT1

and RFB terminals.

OUT2

The AD7568 is a serial input device. Data is loaded using
FSIN, CLKIN and SDIN. One address pin, A0, sets up a de­vice address, and this feature may be used to simplify device
loading in a multi-DAC environment.

All DACs can be simultaneously updated using the asynchro­nous

LDAC input and they can be cleared by asserting the

asynchronous

CLR input.

The AD7568 is housed in a space-saving 44-pin plastic quad
flatpack and 44-lead PLCC.

REF

,

Octal 12-Bit DAC

AD7568

FUNCTIONAL BLOCK DIAGRAM

Plastic Quad Flatpack Plastic Leaded Chip Carrier

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

V F

REF

R F

FB

I F

OUT1

I F

OUT2

V G

REF

R G

FB

I G

OUT1

I G

OUT2

V H

REF

R H

FB

NC

1
2
3
4
5
6
7
8

9
10
11

FB

OUT2

OUT1

R E

I E

I E

4443424140393837363534

PIN 1 IDENTIFIER

AD7568 PQFP

121314

OUT1

OUT2

I H

I H

SDOUT

NC = NO CONNECT

REF

VDDDGND

V E

AD7568

TOP VIEW

TOP VIEW

Not to Scale

(Not to Scale)

151617

CLR

FSIN

LDAC

AGND

181920

SDIN

REF

V D

CLKIN

FB

R D

A0

OUT1

I D

21

OUT2

I A

OUT2

I D

22

OUT1

I A

PIN CONFIGURATIONS

33

NC
V C

32

REF

R C

31

FB

I C

30

OUT1

29

I C

OUT2

V B

28

REF

R B

27

FB

I B

26

OUT1

I B

25

OUT2

24

V A

REF

R A

23

FB

AD7568–SPECIFICATIONS

REV. C

Parameter AD7568B

2

(VDD = +4.75 V to +5.25 V; I

1

unless otherwise noted)

Units Test Conditions/Comments

OUT1

= I

OUT2

= O V; V

= +5 V; TA = T

REF

MIN

to T

MAX

,

ACCURACY

Resolution 12 Bits 1 LSB = V

/212 = 1.22 mV when V

REF

REF

= 5 V
Relative Accuracy ±0.5 LSB max
Differential Nonlinearity ±0.9 LSB max All Grades Guaranteed Monotonic over Temperature
Gain Error

+25°C ±4 LSBs max
T

MIN

to T

MAX

±5 LSBs max

Gain Temperature Coefficient 2 ppm FSR/°C typ

5 ppm FSR/°C max

Output Leakage Current

I

OUT1

@ +25°C 10 nA max See Terminology Section
T

MIN

to T

MAX

200 nA max

REFERENCE INPUT

Input Resistance 5 kΩ min Typical Input Resistance = 7 kΩ

9kΩ max

Ladder Resistance Mismatch 2 % max Typically 0.6%

DIGITAL INPUTS

V

, Input High Voltage 2.4 V min

INH

V

, Input Low Voltage 0.8 V max

INL

I

, Input Current ±1 µA max

INH

CIN, Input Capacitance 10 pF max

POWER REQUIREMENTS

V

Range 4.75/5.25 V min/V max

DD

Power Supply Sensitivity

∆Gain/∆V

I

DD

DD

–75 dB typ
300 µA max V

3.5 mA max V

= 4.0 V min, V

INH

= 2.4 V min, V

INH

= 0.4 V max

INL

= 0.8 V max

INL

(These characteristics are included for Design Guidance and are not subject

AC PERFORMANCE CHARACTERISTICS

Parameter AD7568B

2

to test. DAC output op amp is AD843.)

Units Test Conditions/Comments

DYNAMIC PERFORMANCE

Output Voltage Settling Time 500 ns typ To 0.01% of Full-Scale Range. DAC Latch Alternately

Loaded with All 0s and All 1s.

Digital to Analog Glitch Impulse 40 nV–s typ Measured with V

= 0 V. DAC Register Alternately

REF

Loaded with All 0s and All 1s.

Multiplying Feedthrough Error –66 dB max V

= 20 V pk-pk, 10 kHz Sine Wave. DAC Latch

REF

Loaded with All 0s.

Output Capacitance 60 pF max All 1s Loaded to DAC.

30 pF max All 0s Loaded to DAC.

Channel-to-Channel Isolation –76 dB typ Feedthrough from Any One Reference to the Others

with 20 V pk-pk, 10 kHz Sine Wave Applied.

Digital Crosstalk 40 nV–s typ Effect of all 0s to all 1s Code Transition on

Nonselected DACs.

Digital Feedthrough 40 nV–s typ Feedthrough to Any DAC Output with

FSIN High

and Square Wave Applied to SDIN and SCLK.

Total Harmonic Distortion –83 dB typ V

= 6 V rms, 1 kHz Sine Wave.

REF

Output Noise Spectral Density

@ 1 kHz 20 nV/√

Hz All 1s Loaded to the DAC. V

REF

= 0 V. Output Op

Amp is AD OP07.

NOTES

1

Temperature range as follows: B Version: –40°C to +85°C.

2

All specifications also apply for V

Specifications subject to change without notice.

= +10 V, except relative accuracy which degrades to ±1 LSB.

REF

–2–

AD7568

REV. C

TIMING SPECIFICATIONS

(VDD = +5 V 6 5%; I

OUT1

= I

OUT2

= 0 V; TA = T

MIN

to T

, unless otherwise noted)

MAX

Limit at Limit at

Parameter TA = +258CT

t

1

t

2

t

3

t

4

t

5

t

6

t

7

2

t

8

t

9

NOTES

1

Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

2

t8 is measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V.

100 100 ns min CLKIN Cycle Time
40 40 ns min CLKIN High Time
40 40 ns min CLKIN Low Time
30 30 ns min FSIN Setup Time
30 30 ns min Data Setup Time
5 5 ns min Data Hold Time
90 90 ns min FSIN Hold Time
70 70 ns max SDOUT Valid After CLKIN Falling Edge
40 40 ns min LDAC, CLR Pulse Width

CLKIN (I)

t

FSIN (I)

SDIN (I)

SDOUT (O)

LDAC, CLR

NOTES

1. AO IS HARDWIRED HIGH OR LOW.

= –408C to +858C Units Description

A

t

1

t

t

4

t

6

DB15 DB0

2

t

5

t

t

3

7

8

DB15

t

9

DB0

Figure 1. Timing Diagram

TO OUTPUT

PIN

C

L

50pF

1.6mA I

200µA

OL

+2.1V

I

OH

Figure 2. Load Circuit for Digital Output
Timing Specifications

–3–

AD7568

– 4 –

REV. C

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted

Parameter Rating

VDD to DGND −0.3 V to +6 V
I

to DGND −0.3 V to VDD +0.3 V

OUT1

I

to DGND −0.3 V to VDD +0.3 V

OUT2

Digital Input Voltage to DGND −0.3 V to VDD +0.3 V
V

, V

to DGND ±15 V

RFB

REF

Input Current to Any Pin Except Supplies1 ±10 mA
Operating Temperature Range

Commercial Plastic (B Versions) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C
Power Dissipation (Any Package) to 75°C 250 mW
Derates above 75°C by 10 mW/°C

1

Transient currents of up to 100 mA will not cause SCR latch-up.

PIN DESCRIPTION

Mnemonic Description

VDD Positive Power Supply. This is 5 V ± 5%.
DGND Digital Ground.
AGND Analog Ground
V

to V

DAC Reference Inputs.

REFH

to R

DAC Feedback Resistor Pins.

FBH

to I

DAC Current Output Terminals.

OUTH

R
I

OUTA

REFA

FBA

AGND This pin connects to the back gates of the current steering switches. It should be connected to the signal ground of the system.
CLKIN

Clock Input. Data is clocked into the input shift register on the falling edges of CLKIN. Add a pull-down resistor on the clock
line to avoid timing issues.

FSIN Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When FSIN goes low, it

enables the input shift register, and data is transferred on the falling edges of CLKIN. If the address bit is valid, the 12-bit DAC
data is transferred to the appropriate input latch on the sixteenth falling edge after FSIN

SDIN

Serial Data Input. The device accepts a 16-bit word. The first bit (DB15) is the DAC MSB, with the remaining bits following.
Next comes the device address bit, A0. If this does not correspond to the logic level on Pin A0, the data is ignored. Finally

comes the three DAC select bits. These determine which DAC in the device is selected for loading.
SDOUT This shift register output allows multiple devices to be connected in a daisy-chain configuration.
A0

Device Address Pin. This input gives the device an address. If DB3 of the serial input stream does not correspond to this, the

data that follows is ignored and not loaded to any input latch. However, it will appear at SDOUT irrespective of this.
LDAC Asynchronous LDAC Input. When this input is taken low, all DAC latches are simultaneously updated with the contents of the

input latches.
CLR Asynchronous CLR Input. When this input is taken low, all DAC latch outputs go to zero.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

goes low.

AD7568

REV. C

TERMINOLOGY
Relative Accuracy

Relative Accuracy or endpoint linearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero error and full-scale error and is normally ex­pressed in Least Significant Bits or as a percentage or full-scale
reading.

Differential Nonlinearity

Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity.

Gain Error

Gain Error is a measure of the output error between an ideal
DAC and the actual device output. It is measured with all 1s in
the DAC after offset error has been adjusted out and is
expressed in Least Significant Bits. Gain error is adjustable to
zero with an external potentiometer.

Output Leakage Current

Output leakage current is current which flows in the DAC lad­der switches when these are turned off. For the I

OUT1

terminal,
it can be measured by loading all 0s to the DAC and measuring
the I

current. Minimum current will flow in the I

OUT1

OUT2

line
when the DAC is loaded with all 1s. This is a combination of
the switch leakage current and the ladder termination resistor
current. The I
I

.

OUT1

Output Capacitance

This is the capacitance from the I

leakage current is typically equal to that in

OUT2

pin to AGND.

OUT1

Output Voltage Settling Time

This is the amount of time it takes for the output to settle to a
specified level for a full-scale input change. For the AD7568, it
is specified with the AD843 as the output op amp.

Digital to Analog Glitch Impulse

This is the amount of charge injected into the analog output
when the inputs change state. It is normally specified as the area
of the glitch in either pA-secs or nV-secs, depending upon
whether the glitch is measured as a current or voltage signal. It
is measured with the reference input connected to AGND and
the digital inputs toggled between all 1s and all 0s.

AC Feedthrough Error

This is the error due to capacitive feedthrough from the DAC
reference input to the DAC I

terminal, when all 0s are

OUT

loaded in the DAC.

Channel-to-Channel Isolation

Channel-to-channel isolation refers to the proportion of input
signal from one DAC’s reference input which appears at the
output of any other DAC in the device and is expressed in dBs.

Digital Crosstalk

The glitch impulse transferred to the output of one converter
due to a change in digital input code to the other converter is
defined as the Digital Crosstalk and is specified in nV-secs.

Digital Feedthrough

When the device is not selected, high frequency logic activity on
the device digital inputs is capacitively coupled through the de­vice to show up as noise on the I

pin and subsequently on

OUT

the op amp output. This noise is digital feedthrough.

Table I. AD7568 Loading Sequence

DB15 DB0

DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 A0 DS2 DS1 DS0

Table II. DAC Selection

DS2 DS1 DS0 Function

0 0 0 DAC A Selected
0 0 1 DAC B Selected
0 1 0 DAC C Selected
0 1 1 DAC D Selected
1 0 0 DAC E Sclected
1 0 1 DAC F Selected
1 1 0 DAC G Sclected
1 1 1 DAC H Selected

–5–