ANALOG DEVICES AD7568 Service Manual

R B

R F

DAC A

DAC A
LATCH

INPUT

LATCH A

INPUT

LATCH B

INPUT

LATCH C

INPUT

LATCH D

INPUT

LATCH E

INPUT

LATCH F

INPUT

LATCH G

DAC B
LATCH

DAC C
LATCH

DAC D
LATCH

DAC E
LATCH

DAC F

LATCH

DAC G

LATCH

DAC B

DAC C

DAC D

DAC E

DAC F

DAC G

V B

REF

V D

REF

R G

FB

V G

REF

V F

REF

V E

REF

FB

FB

R E

R D

R C

FB

FB

R A

FBREF

V AV C

REF

V

DD

DGND

LDAC

CLR

AD7568

12

12

12

12

12

12

12

12

12

12

12

12

12

12

V H

REF

A0

CONTROL LOGIC

+

INPUT SHIFT

REGISTER

CLKIN

SDIN

SDOUT

INPUT

LATCH H

DAC H
LATCH

DAC H

R H

FB

12

12

FSIN

I A
I A

I B
I B

I C

I D

I C

I D

I E

I F

I E

I F

I G

I H

I G

I H

AGND

12

OUT1
OUT2

OUT1

OUT2

OUT1

OUT2

FB

OUT1

OUT2

OUT1

OUT2

OUT1
OUT2

OUT1
OUT2

OUT1
OUT2

LC2MOS

NC = NO CONNECT

NC
V

REF

C

V

REF

B

R

FB

B

I

OUT1

B

I

OUT1

C

NC

V

REF

F

V

REF

G

R

FB

G

R

FB

F

I

OUT2

F

I

OUT2

E

I

OUT1

E

V

DD

DGND

AGND

R

FB

E

I

OUT1

H

I

OUT2

H

LDAC

FSIN

SDIN

SDOUT

CLR

V

REF

E

R

FB

D

I

OUT1

D

A0

I

OUT2

A

I

OUT1

A

CLKIN

V

REF

D

V

REF

A

R

FB

A

I

OUT2

B

I

OUT2

G

V

REF

H

R

FB

H

I

OUT1

G

4412645

21 24

23

22182019

39
38

35
34
33

37
36

3

7
8

11
12
13

9

10

404142

25 28

27

26

43

31
30
29

32
15
16
17

14

TOP VIEW

(Not to Scale)

AD7568 PLCC

I

OUT2

D

I

OUT2

C

R

FB

C

I

OUT1

F

REV. C

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2012 Analog Devices, Inc. All rights reserved.

a

FEATURES
Eight 12-Bit DACs in One Package
4-Quadrant Multiplication
Separate References
Single +5 V Supply
Low Power: 1 mW
Versatile Serial Interface
Simultaneous Update Capability
Reset Function
44-Pin PQFP and PLCC

APPLICATIONS
Process Control
Automatic Test Equipment
General Purpose Instrumentation

GENERAL DESCRIPTION

The AD7568 contains eight 12-bit DACs in one monolithic de­vice. The DACs are standard current output with separate V
I

, I

OUT1

and RFB terminals.

OUT2

The AD7568 is a serial input device. Data is loaded using
FSIN, CLKIN and SDIN. One address pin, A0, sets up a de­vice address, and this feature may be used to simplify device
loading in a multi-DAC environment.

All DACs can be simultaneously updated using the asynchro­nous

LDAC input and they can be cleared by asserting the

asynchronous

CLR input.

The AD7568 is housed in a space-saving 44-pin plastic quad
flatpack and 44-lead PLCC.

REF

,

Octal 12-Bit DAC

AD7568

FUNCTIONAL BLOCK DIAGRAM

Plastic Quad Flatpack Plastic Leaded Chip Carrier

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

V F

REF

R F

FB

I F

OUT1

I F

OUT2

V G

REF

R G

FB

I G

OUT1

I G

OUT2

V H

REF

R H

FB

NC

1
2
3
4
5
6
7
8

9
10
11

FB

OUT2

OUT1

R E

I E

I E

4443424140393837363534

PIN 1 IDENTIFIER

AD7568 PQFP

121314

OUT1

OUT2

I H

I H

SDOUT

NC = NO CONNECT

REF

VDDDGND

V E

AD7568

TOP VIEW

TOP VIEW

Not to Scale

(Not to Scale)

151617

CLR

FSIN

LDAC

AGND

181920

SDIN

REF

V D

CLKIN

FB

R D

A0

OUT1

I D

21

OUT2

I A

OUT2

I D

22

OUT1

I A

PIN CONFIGURATIONS

33

NC
V C

32

REF

R C

31

FB

I C

30

OUT1

29

I C

OUT2

V B

28

REF

R B

27

FB

I B

26

OUT1

I B

25

OUT2

24

V A

REF

R A

23

FB

AD7568–SPECIFICATIONS

REV. C

Parameter AD7568B

2

(VDD = +4.75 V to +5.25 V; I

1

unless otherwise noted)

Units Test Conditions/Comments

OUT1

= I

OUT2

= O V; V

= +5 V; TA = T

REF

MIN

to T

MAX

,

ACCURACY

Resolution 12 Bits 1 LSB = V

/212 = 1.22 mV when V

REF

REF

= 5 V
Relative Accuracy ±0.5 LSB max
Differential Nonlinearity ±0.9 LSB max All Grades Guaranteed Monotonic over Temperature
Gain Error

+25°C ±4 LSBs max
T

MIN

to T

MAX

±5 LSBs max

Gain Temperature Coefficient 2 ppm FSR/°C typ

5 ppm FSR/°C max

Output Leakage Current

I

OUT1

@ +25°C 10 nA max See Terminology Section
T

MIN

to T

MAX

200 nA max

REFERENCE INPUT

Input Resistance 5 kΩ min Typical Input Resistance = 7 kΩ

9kΩ max

Ladder Resistance Mismatch 2 % max Typically 0.6%

DIGITAL INPUTS

V

, Input High Voltage 2.4 V min

INH

V

, Input Low Voltage 0.8 V max

INL

I

, Input Current ±1 µA max

INH

CIN, Input Capacitance 10 pF max

POWER REQUIREMENTS

V

Range 4.75/5.25 V min/V max

DD

Power Supply Sensitivity

∆Gain/∆V

I

DD

DD

–75 dB typ
300 µA max V

3.5 mA max V

= 4.0 V min, V

INH

= 2.4 V min, V

INH

= 0.4 V max

INL

= 0.8 V max

INL

(These characteristics are included for Design Guidance and are not subject

AC PERFORMANCE CHARACTERISTICS

Parameter AD7568B

2

to test. DAC output op amp is AD843.)

Units Test Conditions/Comments

DYNAMIC PERFORMANCE

Output Voltage Settling Time 500 ns typ To 0.01% of Full-Scale Range. DAC Latch Alternately

Loaded with All 0s and All 1s.

Digital to Analog Glitch Impulse 40 nV–s typ Measured with V

= 0 V. DAC Register Alternately

REF

Loaded with All 0s and All 1s.

Multiplying Feedthrough Error –66 dB max V

= 20 V pk-pk, 10 kHz Sine Wave. DAC Latch

REF

Loaded with All 0s.

Output Capacitance 60 pF max All 1s Loaded to DAC.

30 pF max All 0s Loaded to DAC.

Channel-to-Channel Isolation –76 dB typ Feedthrough from Any One Reference to the Others

with 20 V pk-pk, 10 kHz Sine Wave Applied.

Digital Crosstalk 40 nV–s typ Effect of all 0s to all 1s Code Transition on

Nonselected DACs.

Digital Feedthrough 40 nV–s typ Feedthrough to Any DAC Output with

FSIN High

and Square Wave Applied to SDIN and SCLK.

Total Harmonic Distortion –83 dB typ V

= 6 V rms, 1 kHz Sine Wave.

REF

Output Noise Spectral Density

@ 1 kHz 20 nV/√

Hz All 1s Loaded to the DAC. V

REF

= 0 V. Output Op

Amp is AD OP07.

NOTES

1

Temperature range as follows: B Version: –40°C to +85°C.

2

All specifications also apply for V

Specifications subject to change without notice.

= +10 V, except relative accuracy which degrades to ±1 LSB.

REF

–2–

AD7568

REV. C

TIMING SPECIFICATIONS

(VDD = +5 V 6 5%; I

OUT1

= I

OUT2

= 0 V; TA = T

MIN

to T

, unless otherwise noted)

MAX

Limit at Limit at

Parameter TA = +258CT

t

1

t

2

t

3

t

4

t

5

t

6

t

7

2

t

8

t

9

NOTES

1

Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

2

t8 is measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V.

100 100 ns min CLKIN Cycle Time
40 40 ns min CLKIN High Time
40 40 ns min CLKIN Low Time
30 30 ns min FSIN Setup Time
30 30 ns min Data Setup Time
5 5 ns min Data Hold Time
90 90 ns min FSIN Hold Time
70 70 ns max SDOUT Valid After CLKIN Falling Edge
40 40 ns min LDAC, CLR Pulse Width

CLKIN (I)

t

FSIN (I)

SDIN (I)

SDOUT (O)

LDAC, CLR

NOTES

1. AO IS HARDWIRED HIGH OR LOW.

= –408C to +858C Units Description

A

t

1

t

t

4

t

6

DB15 DB0

2

t

5

t

t

3

7

8

DB15

t

9

DB0

Figure 1. Timing Diagram

TO OUTPUT

PIN

C

L

50pF

1.6mA I

200µA

OL

+2.1V

I

OH

Figure 2. Load Circuit for Digital Output
Timing Specifications

–3–

AD7568

– 4 –

REV. C

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted

Parameter Rating

VDD to DGND −0.3 V to +6 V
I

to DGND −0.3 V to VDD +0.3 V

OUT1

I

to DGND −0.3 V to VDD +0.3 V

OUT2

Digital Input Voltage to DGND −0.3 V to VDD +0.3 V
V

, V

to DGND ±15 V

RFB

REF

Input Current to Any Pin Except Supplies1 ±10 mA
Operating Temperature Range

Commercial Plastic (B Versions) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C
Power Dissipation (Any Package) to 75°C 250 mW
Derates above 75°C by 10 mW/°C

1

Transient currents of up to 100 mA will not cause SCR latch-up.

PIN DESCRIPTION

Mnemonic Description

VDD Positive Power Supply. This is 5 V ± 5%.
DGND Digital Ground.
AGND Analog Ground
V

to V

DAC Reference Inputs.

REFH

to R

DAC Feedback Resistor Pins.

FBH

to I

DAC Current Output Terminals.

OUTH

R
I

OUTA

REFA

FBA

AGND This pin connects to the back gates of the current steering switches. It should be connected to the signal ground of the system.
CLKIN

Clock Input. Data is clocked into the input shift register on the falling edges of CLKIN. Add a pull-down resistor on the clock
line to avoid timing issues.

FSIN Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When FSIN goes low, it

enables the input shift register, and data is transferred on the falling edges of CLKIN. If the address bit is valid, the 12-bit DAC
data is transferred to the appropriate input latch on the sixteenth falling edge after FSIN

SDIN

Serial Data Input. The device accepts a 16-bit word. The first bit (DB15) is the DAC MSB, with the remaining bits following.
Next comes the device address bit, A0. If this does not correspond to the logic level on Pin A0, the data is ignored. Finally

comes the three DAC select bits. These determine which DAC in the device is selected for loading.
SDOUT This shift register output allows multiple devices to be connected in a daisy-chain configuration.
A0

Device Address Pin. This input gives the device an address. If DB3 of the serial input stream does not correspond to this, the

data that follows is ignored and not loaded to any input latch. However, it will appear at SDOUT irrespective of this.
LDAC Asynchronous LDAC Input. When this input is taken low, all DAC latches are simultaneously updated with the contents of the

input latches.
CLR Asynchronous CLR Input. When this input is taken low, all DAC latch outputs go to zero.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

goes low.

AD7568

REV. C

TERMINOLOGY
Relative Accuracy

Relative Accuracy or endpoint linearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero error and full-scale error and is normally ex­pressed in Least Significant Bits or as a percentage or full-scale
reading.

Differential Nonlinearity

Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity.

Gain Error

Gain Error is a measure of the output error between an ideal
DAC and the actual device output. It is measured with all 1s in
the DAC after offset error has been adjusted out and is
expressed in Least Significant Bits. Gain error is adjustable to
zero with an external potentiometer.

Output Leakage Current

Output leakage current is current which flows in the DAC lad­der switches when these are turned off. For the I

OUT1

terminal,
it can be measured by loading all 0s to the DAC and measuring
the I

current. Minimum current will flow in the I

OUT1

OUT2

line
when the DAC is loaded with all 1s. This is a combination of
the switch leakage current and the ladder termination resistor
current. The I
I

.

OUT1

Output Capacitance

This is the capacitance from the I

leakage current is typically equal to that in

OUT2

pin to AGND.

OUT1

Output Voltage Settling Time

This is the amount of time it takes for the output to settle to a
specified level for a full-scale input change. For the AD7568, it
is specified with the AD843 as the output op amp.

Digital to Analog Glitch Impulse

This is the amount of charge injected into the analog output
when the inputs change state. It is normally specified as the area
of the glitch in either pA-secs or nV-secs, depending upon
whether the glitch is measured as a current or voltage signal. It
is measured with the reference input connected to AGND and
the digital inputs toggled between all 1s and all 0s.

AC Feedthrough Error

This is the error due to capacitive feedthrough from the DAC
reference input to the DAC I

terminal, when all 0s are

OUT

loaded in the DAC.

Channel-to-Channel Isolation

Channel-to-channel isolation refers to the proportion of input
signal from one DAC’s reference input which appears at the
output of any other DAC in the device and is expressed in dBs.

Digital Crosstalk

The glitch impulse transferred to the output of one converter
due to a change in digital input code to the other converter is
defined as the Digital Crosstalk and is specified in nV-secs.

Digital Feedthrough

When the device is not selected, high frequency logic activity on
the device digital inputs is capacitively coupled through the de­vice to show up as noise on the I

pin and subsequently on

OUT

the op amp output. This noise is digital feedthrough.

Table I. AD7568 Loading Sequence

DB15 DB0

DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 A0 DS2 DS1 DS0

Table II. DAC Selection

DS2 DS1 DS0 Function

0 0 0 DAC A Selected
0 0 1 DAC B Selected
0 1 0 DAC C Selected
0 1 1 DAC D Selected
1 0 0 DAC E Sclected
1 0 1 DAC F Selected
1 1 0 DAC G Sclected
1 1 1 DAC H Selected

–5–

AD7568

1.0

0.0

10.0

0.3

0.1

4.0

0.2

2.0

0.6

0.4

0.5

0.7

0.8

0.9

8.0

6.0

V = +5V
T = +25°C

DD
A

V – Volts

REF

DNL – LSBs

–50

–100

–85

–95

–90

–70

–80

–75

–65

–60

–55

10

2

10

3

10

4

10

5

FREQUENCY – Hz

THD – dBs

V = +5V
T = +25°C
V = 6V rms
OP AMP = AD713

DD

A

IN

REV. C

–Typical Performance Curves

5.5

5.0

4.5

4.0

3.5

3.0

2.5

DD

I – mA

2.0

1.5

1.0

0.5

0.0

0.0

1.0
DIGITAL INPUT – Volts

V = +5V

DD

T = +25°C

A

4.03.02.0

5.0

Figure 3. Supply Current vs. Logic
Input Voltage

1.0

0.9

0.8

0.7

0.6

0.5

0.4

INL – LSBs

0.3

0.2

0.1

0.0

2.0

4.0
V – Volts

REF

V = +5V

DD

T = +25°C

A

8.06.0

10.0

Figure 6. Integral Nonlinearity Error
vs. V

REF

2

V = +5V

DD

V = +2.4V

IH

1

DD

I – mA

V = +4V

IH

0

TEMPERATURE – °C

35

Figure 4. Supply Current vs.
Temperature

1.0

V = +10V

2048

REF

V = +5V

DD

T = +25°C

A

0.8

0.6

0.4

INL SPREAD – LSBs

0.2

0.0
0

DIGITAL CODE

Figure 7. Typical DAC to DAC
Linearity Matching

85–15–40

6010

Figure 5. Differential Nonlinearity
Error vs. V

4095

REF

Figure 8. Total Harmonic Distortion
vs. Frequency



5V

100

DIGITAL INPUTS

90

AD713 OUTPUT

10

0%



50mV

Figure 9. Digital-to-Analog Glitch
Impulse



200ns

V = +5V

DD

T = +25°C

A

V = +10V

REF

OP AMP = AD713



200ns

0

V C = 20V pk-pk SINE WAVE

REF

–10

ALL OTHER REFERENCE INPUTS GROUNDED
DAC C LOADED WITH ALL 1s

–20

ALL OTHER DACs LOADED WITH ALL 0s

–30
–40
–50

OUT

–60

OUT

–70

V B/V C – dBs

–80
–90

–100

3

10

4

10

FREQUENCY – Hz

10

5

Figure 10. Channel-to-Channel
Isolation (1 DAC to 1 DAC)

–6–

0

V B GROUNDED

–10
–20
–30
–40
–50

OUT

–60

OUT

–70

V B/V C – dBs

–80
–90

6

10

–100

REF

ALL OTHER REFERENCE INPUTS =
20V pk-pk SINE WAVE
DAC B LOADED WITH ALL 0s
ALL OTHER DACs LOADED WITH ALL 1s

3

10

4

10

FREQUENCY – Hz

5

10

6

10

Figure 11. Channel-to-Channel
Isolation (1 DAC to All Other DACs)

AD7568

16-BIT INPUT SHIFT REGISTER

CLKIN

SDIN SDOUT

FSIN

REV. C

0

DAC LOADED WITH ALL 1s

–10
–20

V = +5V

DD

T = +25°C

A

–30

V = 20V pk-pk

IN

–40

OP AMP = AD713

–50
–60
–70
–80
–90

–100

3

10

DAC LOADED WITH ALL 0s

4

10

5

10

6

10

7

10

Figure 12. Multiplying Frequency Response vs.
Digital Code

GENERAL DESCRIPTION
D/A Section

The AD7568 contains eight 12-bit current-output D/A convert­ers. A simplified circuit diagram for one of the D/A converters is
shown in Figure 13.

A segmented scheme is used whereby the 2 MSBs of the 12-bit
data word are decoded to drive the three switches A, B and C.
The remaining 10 bits of the data word drive the switches S0 to
S9 in a standard R–2R ladder configuration.

Each of the switches A to C steers 1/4 of the total reference cur­rent with the remaining current passing through the R–2R
section.

Each DAC in the device has separate V
R

pins. This makes the device extremely versatile and allows

FB

REF

, I

OUT1

, I

OUT2

and

DACs in the same device to be configured differently.
When an output amplifier is connected in the standard configu-

ration of Figure 15, the output voltage is given by:

V

= –D•V

OUT

REF

where D is the fractional representation of the digital word
loaded to the DAC. Thus, in the AD7568, D can be set from
0 to 4095/4096.

V

REF

R

R

R

Interface Section

The AD7568 is a serial input device. Three lines control the se­rial interface,

FSIN, CLKIN and SDIN. The timing diagram is

shown in Figure 1.
When the

FSIN input goes low, data appearing on the SDIN
line is clocked into the input shift register on each falling edge of
CLKIN. When sixteen bits have been received, the register
loading is automatically disabled until the next falling edge of
FSIN detected. Also, the received data is clocked out on the
next rising edge of CLKIN and appears on the SDOUT pin.
This feature allows several devices to be connected together in a
daisy chain fashion.

When the sixteen bits have been received in the input shift regis­ter, DB3 (A0) is checked to see if it corresponds to the state of
pin A0. If it does, then the word is accepted. Otherwise, it is dis­regarded. This allows the user to address one of two AD7568s
in a very simple fashion. DB0 to DB2 of the 16-bit word deter­mine which of the eight DAC input latches is to be loaded.
When the

LDAC line goes low, all eight DAC latches in the de­vice are simultaneously loaded with the contents of their respec­tive input latches, and the outputs change accordingly.

Bringing the

CLR line low resets the DAC latches to all 0s. The
input latches are not affected, so that the user can revert to the
previous analog output if desired.

Figure 14. Input Logic

2R 2R 2R 2R 2R 2R 2R

CBA

S9

SHOWN FOR ALL 1s ON DAC

Figure 13. Simplified D/A Circuit Diagram

S8 S9

R/2

R
I

I

FB

OUT1
OUT2

–7–

AD7568

DAC A

A1

I A

OUT1

I A

OUT2

AD7568

V

BIAS

V

OUT

R A

FB

V A

REF

V

IN

NOTES

1. ONLY ONE DAC IS SHOWN FOR CLARITY.

2. DIGITAL INPUT CONNECTIONS ARE OMITTED.

3. C1 PHASE COMPENSATION (5–15pF) MAY BE
REQUIRED WHEN USING HIGH SPEED AMPLIFIER, A1.

REV. C

UNIPOLAR BINARY OPERATION
(2-Quadrant Multiplication)

Figure 15 shows the standard unipolar binary connection dia­gram for one of the DACs in the AD7568. When V

is an ac

IN

signal, the circuit performs 2-quadrant multiplication. Resistors
R1 and R2 allow the user to adjust the DAC gain error. Offset
can be removed by adjusting the output amplifier offset voltage.

A1 should be chosen to suit the application. For example, the
AD OP07 or OP177 are ideal for very low bandwidth applica­tions while the AD843 and AD845 offer very fast settling time
in wide bandwidth applications. Appropriate multiple versions
of these amplifiers can be used with the AD7568 to reduce
board space requirements.

The code table for Figure 15 is shown in Table III.

R2 10Ω

R A

R1 20Ω

V

IN

V A

REF

NOTES

1. ONLY ONE DAC IS SHOWN FOR CLARITY.

2. DIGITAL INPUT CONNECTIONS ARE OMITTED.

3. C1 PHASE COMPENSATION (5–15pF) MAY BE
REQUIRED WHEN USING HIGH SPEED AMPLIFIER, A1.

FB

DAC A

AD7568

I A

OUT1

I A

OUT2

SIGNAL

GND

C1

A1

A1: OP-177

ADOP-07
AD711
AD843
AD845

V

OUT

Figure 15. Unipolar Binary Operation

R4

R2 10Ω

R A

R1 20Ω

V

IN

V A

REF

FB

I A

OUT1

DAC A

I A

AD7568

NOTES

1. ONLY ONE DAC IS SHOWN FOR CLARITY.

2. DIGITAL INPUT CONNECTIONS ARE OMITTED.

3. C1 PHASE COMPENSATION (5–15pF) MAY BE
REQUIRED WHEN USING HIGH SPEED AMPLIFIER, A1.

OUT2

SIGNAL

GND

20kΩ

C1

A1

R3

10kΩ

20kΩ

A2

R5

V

OUT

Figure 16. Bipolar Operation (4-Quadrant Multiplication)

Table IV. Bipolar (Offset Binary) Code Table

Digital Input Analog Output

MSB . . . . . LSB (V

1111 1111 1111 +V
1000 0000 0001 +V
1000 0000 0000 +V
0111 1111 1111 –V
0000 0000 0001 –V
0000 0000 0000 –V

NOTE
Nominal LSB size for the circuit of Figure 16 is given by:
V

(1/2048).

REF

As Shown in Figure 16)

OUT

(2047/2048)

REF

(1/2048)

REF

(0/2048) = 0

REF

(1/2048)

REF

(2047/2048)

REF

(2048/2048) = –V

REF

REF

Table III. Unipolar Binary Code Table

Digital Input Analog Output
MSB………LSB (V

1111 1111 1111 –V
1000 0000 0001 –V
1000 0000 0000 –V
0111 1111 1111 –V
0000 0000 0001 –V
0000 0000 0000 –V

NOTE
Nominal LSB size for the circuit of Figure 15 is given by:
V

(1/4096).

REF

As Shown in Figure 15)

OUT

(4095/4096)

REF

(2049/4096)

REF

(2048/4096)

REF

(2047/4096)

REF

(1/4096)

REF

(0/4096) = 0

REF

BIPOLAR OPERATION
(4-Quadrant Multiplication)

Figure 16 shows the standard connection diagram for bipolar
operation of any one of the DACs in the AD7568. The coding is
offset binary as shown in Table IV. When V

is an ac signal,

IN

the circuit performs 4-quadrant multiplication. To maintain the
gain error specifications, resistors R3, R4 and R5 should be ra­tio matched to 0.01%.

SINGLE SUPPLY CIRCUITS

The AD7568 operates from a single +5 V supply, and this
makes it ideal for single supply systems. When operating in such
a system, it is not possible to use the standard circuits of Figures
15 and 16 since these invert the analog input, V

. There are

IN

two alternatives. One of these continues to operate the DAC as
a current-mode device, while the other uses the voltage switch­ing mode.

Figure 17. Single Supply Current-Mode Operation

–8–

Current Mode Circuit

DAC A

A1

I A

OUT1

I A

OUT2

AD7568

V

OUT

R A

FB

V A

REF

V

IN

NOTES

1) ONLY ONE DAC IS SHOWN FOR CLARITY.

2) DIGITAL INPUT CONNECTIONS ARE OMITTED.

3) C1 PHASE COMPENSATION (5–15pF) MAY BE
REQUIRED WHEN USING HIGH SPEED AMPLIFIER, A1.

R1 R2

REV. C

In the current mode circuit of Figure 17, I
I

, is biased positive by an amount V

OUT1

, and hence

OUT2

. For the circuit to

BIAS

operate correctly, the DAC ladder termination resistor must be
connected internally to I

. This is the case with the AD7568.

OUT2

The output voltage is given by:

R

V

OUT

FB

= D

{}

V

()

BIAS−VIN

R

DAC

+V

BIAS

As D varies from 0 to 4095/4096, the output voltage varies from
V

OUT

= V

BIAS

to V

OUT

= 2 V

BIAS

– VIN. V

should be a low

BIAS

impedance source capable of sinking and sourcing all possible
variations in current at the I

terminal without any

OUT2

problems.

Voltage Mode Circuit

Figure 18 shows DAC A of the AD7568 operating in the
voltage-switching mode. The reference voltage, V
the I
age is available at the V

OUT1

pin, I

is connected to AGND and the output volt-

OUT2

terminal. In this configuration, a

REF

is applied to

IN

positive reference voltage results in a positive output voltage
making single supply operation possible. The output from the
DAC is a voltage at a constant impedance (the DAC ladder re­sistance). Thus, an op amp is necessary to buffer the output
voltage. The reference voltage input no longer sees a constant
input impedance, but one which varies with code. So, the volt­age input should be driven from a low impedance source.

It is important to note that V

is limited to low voltages be-

IN

cause the switches in the DAC no longer have the same source­drain voltage. As a result, their on-resistance differs and this
degrades the integral linearity of the DAC. Also, V

must not

IN

go negative by more than 0.3 volts or an internal diode will turn
on, causing possible damage to the device. This means that the
full-range multiplying capability of the DAC is lost.

AD7568

Figure 18. Single Supply Voltage Switching
Mode Operation

APPLICATIONS
Programmable State Variable Filter

The AD7568 with its multiplying capability and fast settling
time is ideal for many types of signal conditioning applications.
The circuit of Figure 19 shows its use in a state variable filter
design. This type of filter has three outputs: low pass, high pass
and bandpass. The particular version shown in Figure 19 uses
one half of an AD7568 to control the critical parameters f
and A

. Instead of several fixed resistors, the circuit uses the

0

DAC equivalent resistances as circuit elements. Thus, R1 in
Figure 19 is controlled by the 12-bit digital word loaded to
DAC A of the AD7568. This is also the case with R2, R3 and
R4. The fixed resistor R5 is the feedback resistor, R

DAC Equivalent Resistance, R

EQ

= (R

LADDER

3 4096)/N

where:

R

is the DAC ladder resistance.

LADDER

N is the DAC Digital Code in Decimal (0 < N < 4096).

FB

B.

0

, Q

V

IN

V A

REF

C3 10pF

I A

DAC A

(R1)

OUT1

10kΩ

A1

I B

OUT1

DAC B

R8 30kΩ

R6

R BFBV B

(R2)

OUT1

C1 1000pF

A2

V D

REF

DAC D

(R4)

R7 30kΩ

HIGH

REF

PASS
OUTPUT

V C

REF

I C

DAC C

(R3)

A1

C1 1000pF

I D

OUT1

1/2 x AD7568

I A

OUT2

I B

OUT2

NOTES

1. A1, A2, A3, A4: 1/4 x AD713

2. DIGITAL INPUT CONNECTIONS ARE OMITTED.

3. C3 IS A COMPENSATION CAPACITOR TO ELIMINATE
Q AND GAIN VARIATIONS CAUSED BY AMPLIFIER GAIN
BANDWIDTH LIMITATIONS.

I C

OUT2

I D

OUT2

Figure 19. Programmable 2nd Order State Variable Filter

–9–

LOW

A3

PASS
OUTPUT

BAND
PASS
OUTPUT

AD7568

P3.5

P3.4

P3.3

TXD

RXD

SCLK

SDIN

CLR

LDAC

FSIN

80C51*

AD7568*

*ADDITIONAL PINS OMITTED FOR CLARITY

REV. C

In the circuit of Figure 19:

C1 = C2, R7 = R8, R3 = R4 (i.e., the same code is loaded to
each DAC).

Resonant frequency, f0 = 1/(2πR3C1).
Quality Factor, Q = (R6/R8)•(R2/R5).
Bandpass Gain, A0 = –R2/R1.

Using the values shown in Figure 19, the Q range is 0.3 to 5,
and the f

APPLICATION HINTS
Output Offset

range is 0 to 12 kHz.

0

CMOS D/A converters in circuits such as Figures 15, 16 and 17
exhibit a code dependent output resistance which in turn can
cause a code dependent error voltage at the output of the ampli­fier. The maximum amplitude of this error, which adds to the
D/A converter nonlinearity, depends on V

, where VOS is the

OS

amplifier input offset voltage. For the AD7568 to maintain
specified accuracy with V
V

be no greater than 500 µV, or (50 3 10–6)•(V

OS

at 10 V, it is recommended that

REF

), over the

REF

temperature range of operation. Suitable amplifiers include the
AD OP07, AD OP27, OP177, AD711, AD845 or multiple ver­sions of these.

Temperature Coefficients

The gain temperature coefficient of the AD7568 has a maxi­mum value of 5 ppm/°C and a typical value of 2 ppm/°C. This
corresponds to gain shifts of 2 LSBs and 0.8 LSBs respectively
over a 100°C temperature range. When trim resistors R1 and
R2 are used to adjust full-scale in Figures 15 and 16, their tem­perature coefficients should be taken into account. For further
information see “Gain Error and Gain Temperature Coefficient
of CMOS Multiplying DACs,” Application Note, Publication
Number E630c–5–3/86, available from Analog Devices.

High Frequency Considerations

The output capacitances of the AD7568 DACs work in con­junction with the amplifier feedback resistance to add a pole to
the open loop response. This can cause ringing or oscillation.
Stability can be restored by adding a phase compensation ca­pacitor in parallel with the feedback resistor. This is shown as
C1 in Figures 15, 16 and 17.

MICROPROCESSOR INTERFACING
AD7568–80C51 Interface

A serial interface between the AD7568 and the 80C51 micro­controller is shown in Figure 20. TXD of the 80C51 drives
SCLK of the AD7568 while RXD drives the serial data line of
the part. The

FSIN signal is derived from the port line P3.3.

The 80C51 provides the LSB of its SBUF register as the first bit
in the serial data stream. Therefore, the user will have to ensure
that the data in the SBUF register is arranged correctly so that

the data word transmitted to the AD7568 corresponds to the
loading sequence shown in Table I. When data is to be trans­mitted to the part, P3.3 is taken low. Data on RXD is valid on
the falling edge of TXD. The 80C51 transmits its serial data in
8-bit bytes with only eight falling clock edges occurring in the
transmit cycle. To load data to the AD7568, P3.3 is left low af­ter the first eight bits are transferred, and a second byte of data
is then transferred serially to the AD7568. When the second se­rial transfer is complete, the P3.3 line is taken high. Note that
the 80C51 outputs the serial data byte in a format which has the
LSB first. The AD7568 expects the MSB first. The 80C51
transmit routine should take this into account.

Figure 20. AD7568 to 80C51 Interface

LDAC and CLR on the AD7568 are also controlled by 80C51
port outputs. The user can bring

LDAC low after every two
bytes have been transmitted to update the DAC which has been
programmed. Alternatively, it is possible to wait until all the in­put registers have been loaded (sixteen byte transmits) and then
update the DAC outputs.

AD7568–68HC11 Interface

Figure 21 shows a serial interface between the AD7568 and the
68HC11 microcontroller. SCK of the 68HC11 drives SCLK of
the AD7568, while the MOSI output drives the serial data line
of the AD7568. The

FSIN signal is derived from a port line

(PC7 shown).
For correct operation of this interface, the 68HC11 should be

configured such that its CPOL bit is a 0 and its CPHA bit is a 1.
When data is to be transmitted to the part, PC7 is taken low.
When the 68HC11 is configured like this, data on MOSI is valid
on the falling edge of SCK. The 68HC11 transmits its serial
data in 8-bit bytes (MSB first), with only eight falling clock
edges occurring in the transmit cycle. To load data to the
AD7568, PC7 is left low after the first eight bits are transferred,
and a second byte of data is then transferred serially to the
AD7568. When the second serial transfer is complete, the PC7
line is taken high.

–10–

AD7568

XF

FSX

DX

CLKX CLKIN

SDIN

CLR

LDAC

FSIN

TMS320C25*

AD7568*

*ADDITIONAL PINS OMITTED FOR CLARITY

+5V

CLOCK

GENERATION

FO

TFS

DT

SCLK CLKIN

SDIN

CLR

LDAC

FSIN

ADSP-2101*

AD7568*

*ADDITIONAL PINS OMITTED FOR CLARITY

+5V

A0

CLKIN

SDIN

CLR

LDAC

FSIN

AD7568*

+5V

A0

REV. C

68HC11*

PC5

PC6

PC7

SCK

MOSI

*ADDITIONAL PINS OMITTED FOR CLARITY

AD7568*

CLR

LDAC

FSIN

CLKIN

SDIN

Figure 21. AD7568 to 68HC11 Interface

In Figure 21, LDAC and CLR are controlled by the PC6 and
PC5 port outputs. As with the 80C51, each DAC of the
AD7568 can be updated after each two-byte transfer, or else all
DACs can be simultaneously updated.

AD7568–ADSP-2101 Interface

Figure 22 shows a serial interface between the AD7568 and the
ADSP-2101 digital signal processor. The ADSP-2101 may be
set up to operate in the SPORT Transmit Normal Internal
Framing Mode. The following ADSP-2101 conditions are rec­ommended: Internal SCLK; Active High Framing Signal; 16-bit
word length. Transmission is initiated by writing a word to the
TX register after the SPORT has been enabled. The data is then
clocked out on every rising edge of SCLK after TFS goes low.
TFS stays low until the next data transfer.

Figure 23. AD7568 to TMS320C25 Interface

with the MSB, is then shifted out to the DX pin on the rising
edge of CLKX. When all bits have been transmitted, the user
can update the DAC outputs by bringing the XF output flag low.

Multiple DAC Systems

If there are only two AD7568s in a system, there is a simple way
of programming each. This is shown in Figure 24. If the user
wishes to program one of the DACs in the first AD7568, then
DB3 of the serial bit stream should be set to 0, to correspond to
the state of the A0 pin on that device. If the user wishes to pro­gram a DAC in the second AD7568, then DB3 should be set to
1, to correspond to A0 on that device.

ADSP-2101*

*ADDITIONAL PINS OMITTED FOR CLARITY

AD7568–TMS320C25 Interface

Figure 22. AD7568 to ADSP-2101 Interface

Figure 23 shows an interface circuit for the TMS320C25
digital signal processor. The data on the DX pin is clocked
out of the processor’s Transmit Shift Register by the CLKX
signal. Sixteen-bit transmit format should be chosen by setting
the FO bit in the ST1 register to 0. The transmit operation be­gins when data is written into the data transmit register of the
TMS320C25. This data will be transmitted when the FSX line
goes low while CLKX is high or going high. The data, starting

AD7568*

+5V

CLR

FO

TFS

DT

SCLK CLKIN

LDAC

FSIN

SDIN

Figure 24. Interfacing ADSP-2101 to Two AD7568s

–11–

AD7568

PC7

SCK

PC6

MISO

SCLK

SDIN

LDAC

FSIN

68HC11* AD7568*

(DAC 1)

*ADDITIONAL PINS OMITTED FOR CLARITY

A0

SCLK
LDAC

FSIN

AD7568*

(DAC 2)

A0

DECODE LOGIC

SDIN

MOSI

SDOUT

SDOUT

SCLK
LDAC

FSIN

AD7568*

(DAC N)

A0

SDIN

SDOUT

REV. C

For systems which contain larger numbers of AD7568s and
where the user also wishes to read back the DAC contents for
diagnostic purposes, the SDOUT pin may be used to daisy
chain several devices together and provide the necessary serial
readback. An example with the 68HC11 is shown in Figure 25.
The routine below shows how four AD7568s would be pro­grammed in such a system. Data is transmitted at the MOSI pin
of the 68HC11. It flows through the input shift registers of the
AD7568s and finally appears at the SDOUT pin of DAC N. So,
the readback routine can be invoked any time after the first four
words have been transmitted (the four input shift registers in the
chain will now be filled up and further activity on the CLKIN
pin will result in data being read back to the microcomputer
through the MISO pin). System connectivity can be verified in
this manner. For a four-device system (32 DACs) a two-line to
four-line decoder is necessary.

Note that to program the 32 DACs, 35 transmit operations are
needed. In the routine, three words must be retransmitted. The
first word for DACs #3, #2 and #1 must be transmitted twice in
order to synchronize their arrival at the SDIN pin with A0 going
low.

Table V. Routine for Loading 4 AD7568s Connected As in
Figure 25

Bring PC7 (FSIN) low to allow writing to the AD7568s.

Enable AD7568 #4 (Bring A0 low). Disable the others.

Transmit 1st 16-bit word: Data for DAC H, #4

. . . .

. . . .

Transmit 9th 16-bit word: Data for DAC H, #3
Transmit 9th 16-bit word again: Data for DAC H, #3
Transmit 10th 16-bit word: Data for DAC G, #3
Transmit 11th 16-bit word: Data for DAC F, #3

Enable AD7568 #3, Disable the others.

Transmit 12th 16-bit word: Data for DAC E, #3

. . . .

. . . .

Transmit 17th 16-bit word: Data for DAC H, #2
Transmit 17th 16-bit word again: Data for DAC H, #2
Transmit 18th 16-bit word: Data for DAC G, #2

Enable AD7568 #2, Disable the others.

Transmit 19th 16-bit word: Data for DAC F, #2

. . . .

. . . .

Transmit 25th word: Data for DAC H, #1

Enable AD7568 #1, Disable the others.

Transmit 25th word again: Data for DAC H, #1
Transmit 26th word: Data for DAC G, #1

. . . .

. . . .

Transmit 32nd word: Data for DAC A, #1

Bring PC7 (FSIN) high to disable writing to the AD7568s.

Figure 25. Multi-DAC System

–12–

AD7568

REV. C

– 13 –

OUTLINE DIMENSIONS

0.120 (3.05)

0.090 (2.29)

0.180 (4.57)

0.165 (4.19)

0.020 (0.51)
MIN

0.021 (0.53)

0.013 (0.33)

0.032 (0.81)

0.026 (0.66)

0.045 (1.14)

0.025 (0.64)

0.630 (16.00)

0.590 (14.99)

R

BOTTOM VIEW

(PINS UP)

0.048 (1.22)

0.042 (1.07)

0.048 (1.22)

0.042 (1.07)

6

7

17

18

PIN 1

IDENTIFIER

TOP VIEW

(PINS DOWN)

0.656 (16.6 6)

0.650 (16.5 1)

0.695 (17.65)

0.685 (17.40)

SQ

SQ

40

28

39

29

0.056 (1.42)

0.042 (1.07)

0.050
(1.27)
BSC

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

COMPLIANT TO JEDEC STANDARDS MO-047-AC

Figure 26. 44-Lead Plastic Leaded Chip Carrier [PLCC]

(P-44)

Dimensions shown in inches and (millimeters)

44

PIN 1

12

0.80 BSC

LEAD PITCH

14.15

13.90 SQ

13.65

TOP VIEW

(PINS DOWN)

34

33

23

22

0.45

0.30

LEAD WIDTH

10.20

10.00 SQ

9.80

041807-A

2.20

2.00

1.80

0.25 MIN

COPLANARITY

VIEW A

ROTATED 90° CCW

0.10

1.03

0.88

0.73

R

E

5

9

.

1

T

N

I

S

E

A

N

A

P

L

0.23

0.11

7°
0°

COMPLI A NT TO JEDEC S TANDARDS MO -112-AA-1

2.45

MAX

F
G

E

1

11

W

A

V

E

I

Figure 27. 44-Lead Metric Quad Flat Package [MQFP]

(S-44-2)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Linearity Error (LSBs) Package Description Package Option

AD7568BP −40°C to +85°C ±0.5 44-Lead Plastic Leaded Chip Carrier [PLCC] P-44
AD7568BP-REEL −40°C to +85°C ±0.5 44-Lead Plastic Leaded Chip Carrier [PLCC] P-44
AD7568BPZ −40°C to +85°C ±0.5 44-Lead Plastic Leaded Chip Carrier [PLCC] P-44
AD7568BPZ-REEL −40°C to +85°C ±0.5 44-Lead Plastic Leaded Chip Carrier [PLCC] P-44
AD7568BSZ −40°C to +85°C ±0.5 44-Lead Metric Quad Flat Package [MQFP] S-44-2
AD7568BSZ-REEL −40°C to +85°C ±0.5 44-Lead Metric Quad Flat Package [MQFP] S-44-2

1

Z = RoHS Compliant Part

AD7568

REV. C

– 14 –

REVISION HISTORY

2/12—Rev. B to Rev. C

Changes to

Updated Outline Dimensions ........................................................ 13

Changes to Ordering Guide ........................................................... 13

Added Revision History Section ................................................... 14

Description, Pin Description Table ................... 4

CLR

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D10541-0-2/12(C)