Analog Devices AD73360LAR Datasheet

Six-Input Channel

a

FEATURES
Six 16-Bit A/D Converters
Programmable Input Sample Rate
Simultaneous Sampling
76 dB SNR
64 kS/s Maximum Sample Rate
–95 dB Crosstalk
Low Group Delay (25 ␮s Typ per ADC Channel)
Programmable Input Gain
Flexible Serial Port Which Allows Multiple Devices to

Be Connected in Cascade
Single (2.7 V to 3.6 V) Supply Operation
80 mW Max Power Consumption at 2.7 V
On-Chip Reference
28-Lead SOIC Package

APPLICATIONS
General-Purpose Analog Input
Industrial Power Metering
Motor Control
Simultaneous Sampling Applications

GENERAL DESCRIPTION

The AD73360L is a six-input channel analog front-end proces­sor for general-purpose applications, including industrial power

Analog Front End

AD73360L

metering or multichannel analog inputs. It features six 16-bit
A/D conversion channels, each of which provides 76 dB signal­to-noise ratio over a dc-to-4 kHz signal bandwidth. Each
channel also features a programmable input gain amplifier (PGA)
with gain settings in eight stages from 0 dB to 38 dB.

The AD73360L is particularly suitable for industrial power
metering as each channel samples synchronously, ensuring that
there is no (phase) delay between the conversions. The AD73360L
also features low group delay conversions on all channels.

An on-chip reference voltage is included with a nominal value
of 1.2 V.

The sampling rate of the device is programmable, with four
separate settings offering 64 kHz, 32 kHz, 16 kHz, and 8 kHz
sampling rates (from a master clock of 16.384 MHz).

A serial port (SPORT) allows easy interfacing of single or cas­caded devices to industry-standard DSP engines. The SPORT
transfer rate is programmable to allow interfacing to both fast
and slow DSP engines.

The AD73360L is available in 28-lead SOIC package.

VINP1

VINN1

VINP2

VINN2

VINP3

VINN3

REFCAP

REFOUT

VINP4

VINN4

VINP5

VINN5

VINP6

VINN6

SIGNAL

CONDITIONING

SIGNAL

CONDITIONING

SIGNAL

CONDITIONING

SIGNAL

CONDITIONING

SIGNAL

CONDITIONING

SIGNAL

CONDITIONING

FUNCTIONAL BLOCK DIAGRAM

0/38dB

PGA

0/38dB

PGA

0/38dB

PGA

REFERENCE

0/38dB

PGA

0/38dB

PGA

0/38dB

PGA

ANALOG

⌺-⌬

MODULATOR

ANALOG

⌺-⌬

MODULATOR

ANALOG

⌺-⌬

MODULATOR

ANALOG

⌺-⌬

MODULATOR

ANALOG

⌺-⌬

MODULATOR

ANALOG

⌺-⌬

MODULATOR

DECIMATOR

DECIMATOR

DECIMATOR

AD73360L

DECIMATOR

DECIMATOR

DECIMATOR

SERIAL

I/O

PORT

SDI

SDIFS

SCLK

RESET

MCLK

SE

SDO

SDOFS

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

AD73360L–SPECIFICATIONS

(AVDD = 2.7 V to 3.6 V; DVDD = 2.7 V to 3.6 V; DGND = AGND = 0 V, f

1

f

= 8.192 MHz, fS = 8 kHz; TA = T

SCLK

MIN

to T

, unless otherwise noted.)

MAX

= 16.384 MHz,

MCLK

AD73360LA

Parameter Min Typ Max Unit Test Conditions/Comments

REFERENCE

REFCAP

Absolute Voltage, V

REFCAP

1.08 1.2 1.32 V

REFCAP TC 50 ppm/°C 0.1 µF Capacitor Required from REFCAP

to AGND2

REFOUT

Typical Output Impedance 130 Ω
Absolute Voltage, V

REFOUT

1.08 1.2 1.32 V Unloaded
Minimum Load Resistance 1 kΩ
Maximum Load Capacitance 100 pF

ADC SPECIFICATIONS

Maximum Input Range at VIN

2, 3

1.578 V p-p Measured Differentially
–2.85 dBm

Nominal Reference Level at VIN 1.0954 V p-p Measured Differentially

(0 dBm0) –6.02 dBm

Absolute Gain

PGA = 0 dB –1.3 +0.6 dB 1.0 kHz
PGA = 38 dB 0.6 dB 1.0 kHz

Signal to (Noise + Distortion)

PGA = 0 dB 76 dB 0 Hz to 4 kHz; f
PGA = 0 dB 71 76 dB 0 Hz to 2 kHz; f
PGA = 38 dB 58 dB 0 Hz to 4 kHz; f

= 8 kHz

S

= 8 kHz; f

S

= 64 kHz

S

= 60 Hz

IN

Total Harmonic Distortion

PGA = 0 dB –80 –71 dB 0 Hz to 2 kHz; f
PGA = 38 dB –64 dB 0 Hz to 2 kHz; f

= 8 kHz; f

S

= 64 kHz; f

S

= 60 Hz

IN

= 60 Hz

IN

Intermodulation Distortion –78 dB PGA = 0 dB
Idle Channel Noise –68 dB PGA = 0 dB, f

= 64 kHz; S

S

= 16 MHz

CLK

Crosstalk ADC-to-ADC –95 dB ADC1 at Idle

ADC2 to ADC6 Input Signal: 60 Hz
DC Offset –30 +30 mV PGA = 0 dB
Power Supply Rejection –55 dB Input Signal Level at AVDD and DVDD

Pins 1.0 kHz, 100 mV p-p Sine Wave
Group Delay

4, 5

25 µs 64 kHz Output Sample Rate
50 µs 32 kHz Output Sample Rate
95 µs 16 kHz Output Sample Rate

Input Resistance at VIN

2, 4

Phase Mismatch 0.15 Degrees f

190 µs 8 kHz Output Sample Rate
25 kΩ

6

DMCLK = 16.384 MHz

= 1 kHz

IN

0.01 Degrees fIN = 60 Hz

FREQUENCY RESPONSE

(ADC)7 Typical Output

Frequency (Normalized to f

)

S

00dB

0.03125 –0.1 dB

0.0625 –0.25 dB

0.125 –0.6 dB

0.1875 –1.4 dB

0.25 –2.8 dB

0.3125 –4.5 dB

0.375 –7.0 dB

0.4375 –9.5 dB
> 0.5 < –12.5 dB

LOGIC INPUTS

V

, Input High Voltage VDD – 0.8 V

INH

, Input Low Voltage 0 0.8 V

V

INL

I

, Input Current 10 µA

IH

DD

V

CIN, Input Capacitance 10 pF

–2–

REV. 0

AD73360L

AD73360LA

Parameter Min Typ Max Unit Test Conditions/Comments

LOGIC OUTPUT

VOH, Output High Voltage VDD – 0.4 V
V

, Output Low Voltage 0 0.4 V |IOUT| ≤ 100 µA

OL

DD

Three-State Leakage Current –10 +10 µA

POWER SUPPLIES

AVDD1, AVDD2 2.7 3.6 V
DVDD 2.7 3.6 V

8

I

DD

NOTES

1

Operating temperature range is as follows: –40°C to +85°C. Therefore, T

2

Test conditions: Input PGA set for 0 dB gain (unless otherwise noted).

3

At input to sigma-delta modulator of ADC.

4

Guaranteed by design.

5

Overall group delay will be affected by the sample rate and the external digital filtering.

6

The ADC’s input impedance is inversely proportional to DMCLK and is approximated by: (4 × 1011)/DMCLK.

7

Frequency response of ADC measured with input at audio reference level (the input level that produces an output level of –10 dBm0), with 38 dB preamplifier
bypassed and input gain of 0 dB.

8

Test Conditions: no load on digital inputs, analog inputs ac-coupled to ground.

Specifications subject to change without notice.

= –40°C and T

MIN

Table I. Current Summary (AVDD = DVDD = 3.3 V)

Total
Current MCLK

Conditions (Max) SE ON Comments

ADCs Only On 25 1 Yes REFOUT Disabled
REFCAP Only On 1.0 0 No REFOUT Disabled
REFCAP and REFOUT Only On 3.5 0 No
All Sections On 26.5 1 Yes REFOUT Enabled
All Sections Off 1.0 0 Yes MCLK Active Levels Equal to 0 V and DVDD
All Sections Off 0.05 0 No Digital Inputs Static and Equal to 0 V or DVDD

The above values are in mA and are typical values unless otherwise noted. MCLK = 16.384 MHz; SCLK = 16.384 MHz.

V |IOUT| ≤ 100 µA

See Table I

= +85°C.

MAX

TIMING CHARACTERISTICS

(AVDD = 2.7 V to 3.6 V; DVDD = 2.7 V to 3.6 V; AGND = DGND = 0 V; TA = T
wise noted.)

MlN

Limit at

Parameter TA = –40ⴗC to +85ⴗC Unit Description

Clock Signals See Figure 1.

t

1

t

2

t

3

61 ns min MCLK Period

24.4 ns min MCLK Width High

24.4 ns min MCLK Width Low

Serial Port See Figures 3 and 4.

t

4

t

5

t

6

t

7

t

8

t

9

t

10

t

11

t

12

t

13

REV. 0

t

1

0.4 × t

1

0.4 × t

1

20 ns min SDI/SDIFS Setup before SCLK Low
0 ns min SDI/SDIFS Hold after SCLK Low
10 ns max SDOFS Delay from SCLK High
10 ns max SDOFS Hold after SCLK High
10 ns max SDO Hold after SCLK High
10 ns max SDO Delay from SCLK High
30 ns max SCLK Delay from MCLK

ns min SCLK Period
ns min SCLK Width High
ns min SCLK Width Low

–3–

to T

MAX

, unless other-

AD73360L

t

t

2

Figure 1. MCLK Timing

TO OUTPUT

PIN

C

15pF

Figure 2. Load Circuit for Timing Specifications

1

t

3

100␮A

L

100␮A

I

OL

I

OH

2.1V

80

70

60

50

40

30

S/(N+D) – dB

20

10

0

–10

–85 5–75 –65 –55 –45 –35 –25 –15 –5

VIN – dBm0

3.17

Figure 5. S/(N+D) vs. VIN (ADC @ 3 V) Over Voiceband
Bandwidth (300 Hz–3.4 kHz)

MCLK

SCLK*

SE (I)

SCLK (O)

SDIFS (I)

SDI (I)

SDOFS (O)

SDO (O)

t

1

t

13

* SCLK IS INDIVIDUALLY PROGRAMMABLE

IN FREQUENCY (MCLK/4 SHOWN HERE).

t

2

t

5

t

4

Figure 3. SCLK Timing

THREE­STATE

t

THREE­STATE

THREE­STATE

9

t

3

t

6

t

7

t

8

t

10

t

t

12

11

D15 D2 D1 D0 D14

t

8

t

7

D0

D15D1D14D15

D15

Figure 4. Serial Port (SPORT)

–4–

REV. 0

AD73360L

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

(TA = 25°C unless otherwise noted)

AVDD, DVDD to GND . . . . . . . . . . . . . . . . –0.3 V to +4.6 V

AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

Digital I/O Voltage to DGND . . . . . –0.3 V to DVDD + 0.3 V

Analog I/O Voltage to AGND . . . . . . . . . . . . –0.3 V to AVDD

Operating Temperature Range

Industrial (A Version) . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150°C

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

AD73360LAR –40°C to +85°C Small Outline IC (SOIC) R-28

PIN CONFIGURATION

1

VINP2

2

VINN2

3

VINP1

4

VINN1

5

REOUT

AVDD2

AGND2

DGND

DVDD

RESET

SCLK

MCLK

SDO

6

AD73360L

7

TOP VIEW

(Not to Scale)

8

9

10

11

12

13

14

REFCAP

SOIC, θJA Thermal Impedance . . . . . . . . . . . . . . . . . . 75°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

R-28

28

VINN3

27

VINP3

VINN4

26

25

VINP4

24

VINN5

VINP5

23

VINN6

22

VINP6

21

AVDD1

20

AGND1

19

18

SE

17

SDI

16

SDIFS

15

SDOFS

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD73360L features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

REV. 0

–5–

AD73360L

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

1 VINP2 Analog Input to the Positive Terminal of Input Channel 2.
2 VINN2 Analog Input to the Negative Terminal of Input Channel 2.
3 VINP1 Analog Input to the Positive Terminal of Input Channel 1.
4 VINN1 Analog Input to the Negative Terminal of Input Channel 1.
5 REFOUT Buffered Output of the Internal Reference, which has a nominal value of 1.2 V.
6 REFCAP Reference Voltage for ADCs. A Bypass Capacitor to AGND2 of 0.1 µF is required for the on-chip

reference. The capacitor should be fixed to this pin. The internal reference can be overdriven by an

external reference connected to this pin if required.
7 AVDD2 Analog Power Supply Connection.
8 AGND2 Analog Ground/Substrate Connection.
9 DGND Digital Ground/Substrate Connection.
10 DVDD Digital Power Supply Connection.
11 RESET Active Low-Reset Signal. This input resets the entire chip, resetting the control registers and clearing

the digital circuitry.
12 SCLK Output Serial Clock, whose rate determines the serial transfer rate to/from the AD73360L. It is used

to clock data or control information to and from the serial port (SPORT). The frequency of SCLK is

equal to the frequency of the master clock (MCLK) divided by an integer number—this integer num-

ber being the product of the external master clock rate divider and the serial clock rate divider.
13 MCLK Master Clock Input. MCLK is driven from an external clock signal.
14 SDO Serial Data Output of the AD73360L. Both data and control information may be output on this

pin and are clocked on the positive edge of SCLK. SDO is in three-state when no information is being

transmitted and when SE is low.
15 SDOFS Framing Signal Output for SDO Serial Transfers. The frame sync is one bit wide and it is active one

SCLK period before the first bit (MSB) of each output word. SDOFS is referenced to the positive

edge of SCLK. SDOFS is in three-state when SE is low.
16 SDIFS Framing Signal Input for SDI Serial Transfers. The frame sync is one-bit wide and it is valid one

SCLK period before the first bit (MSB) of each input word. SDIFS is sampled on the negative edge of

SCLK and is ignored when SE is low.
17 SDI Serial Data Input of the AD73360L. Both data and control information may be input on this pin and

are clocked on the negative edge of SCLK. SDI is ignored when SE is low.
18 SE SPORT Enable. Asynchronous input enable pin for the SPORT. When SE is set low by the DSP, the

output pins of the SPORT are three-stated and the input pins are ignored. SCLK is also disabled inter-

nally in order to decrease power dissipation. When SE is brought high, the control and data registers of

the SPORT are at their original values (before SE was brought low); however, the timing counters and

other internal registers are at their reset values.
19 AGND1 Analog Ground Connection.
20 AVDD1 Analog Power Supply Connection.
21 VINP6 Analog Input to the Positive Terminal of Input Channel 6.
22 VINN6 Analog Input to the Negative Terminal of Input Channel 6.
23 VINP5 Analog Input to the Positive Terminal of Input Channel 5.
24 VINN5 Analog Input to the Negative Terminal of Input Channel 5.
25 VINP4 Analog Input to the Positive Terminal of Input Channel 4.
26 VINN4 Analog Input to the Negative Terminal of Input Channel 4.
27 VINP3 Analog Input to the Positive Terminal of Input Channel 3.
28 VINN3 Analog Input to the Negative Terminal of Input Channel 3.

–6–

REV. 0

AD73360L

TERMINOLOGY
Absolute Gain

Absolute gain is a measure of converter gain for a known signal.
Absolute gain is measured (differentially) with a 1 kHz sine
wave at 0 dBm0 for each ADC. The absolute gain specification
is used for gain tracking error specification.

Crosstalk

Crosstalk is due to coupling of signals from a given channel to
an adjacent channel. It is defined as the ratio of the amplitude of
the coupled signal to the amplitude of the input signal. Crosstalk
is expressed in dB.

Gain Tracking Error

Gain tracking error measures changes in converter output for
different signal levels relative to an absolute signal level. The
absolute signal level is 0 dBm0 (equal to absolute gain) at 1 kHz
for each ADC. Gain tracking error at 0 dBm0 (ADC) is 0 dB by
definition.

Group Delay

Group delay is defined as the derivative of radian phase with
respect to radian frequency, dø(f)/df. Group delay is a measure
of average delay of a system as a function of frequency. A linear
system with a constant group delay has a linear phase response.
The deviation of group delay from a constant indicates the
degree of nonlinear phase response of the system.

Idle Channel Noise

Idle channel noise is defined as the total signal energy measured
at the output of the device when the input is grounded (mea­sured in the frequency range 0 Hz–4 kHz).

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m nor n are equal to zero. For final testing, the second
order terms include (fa + fb) and (fa – fb), while the third order
terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).

Power Supply Rejection

Power supply rejection measures the susceptibility of a device to
noise on the power supply. Power supply rejection is measured
by modulating the power supply with a sine wave and measuring
the noise at the output (relative to 0 dB).

Sample Rate

The sample rate is the rate at which each ADC updates its output
register. It is set relative to the DMCLK and the programmable
sample rate setting.

SNR + THD

Signal-to-noise ratio plus harmonic distortion is defined to be
the ratio of the rms value of the measured input signal to the
rms sum of all other spectral components in a given frequency
range, including harmonics but excluding dc.

ABBREVIATIONS

ADC Analog-to-Digital Converter.

BW Bandwidth.

CRx A Control Register where x is a placeholder for

an alphabetic character (A–E). There are eight
read/write control registers on the AD73360L—
designated CRA through CRE.

CRx:n A bit position, where n is a placeholder for a

numeric character (0–7), within a control regis­ter; where x is a placeholder for an alphabetic
character (A–E). Position 7 represents the MSB
and Position 0 represents the LSB.

DMCLK Device (Internal) Master Clock. This is the

internal master clock resulting from the external
master clock (MCLK) being divided by the on­chip master clock divider.

FSLB Frame Sync Loop-Back—where the SDOFS of

the final device in a cascade is connected to the
RFS and TFS of the DSP and the SDIFS of first
device in the cascade. Data input and output
occur simultaneously. In the case of non-FSLB,
SDOFS and SDO are connected to the Rx Port
of the DSP while SDIFS and SDI are connected
to the Tx Port.

PGA Programmable Gain Amplifier.

SC Switched Capacitor.

SNR Signal-to-Noise Ratio.

SPORT Serial Port.

THD Total Harmonic Distortion.

VBW Voice Bandwidth.

REV. 0

–7–

AD73360L

FUNCTIONAL DESCRIPTION
General Description

The AD73360L is a six-input channel, 16-bit, analog front end.
It comprises six independent encoder channels each featuring
signal conditioning, programmable gain amplifier, sigma-delta
A/D converter and decimator sections. Each of these sections is
described in further detail below.

Encoder Channel

Each encoder channel consists of a signal conditioner, a switched
capacitor PGA, and a sigma-delta analog-to-digital converter
(ADC). An on-board digital filter, which forms part of the
sigma-delta ADC, also performs critical system-level filtering.
Due to the high-level of oversampling, the input antialias require­ments are reduced such that a simple single pole RC stage is
sufficient to give adequate attenuation in the band of interest.

Signal Conditioner

Each analog channel has an independent signal conditioning
block. This allows the analog input to be configured by the user
depending on whether differential or single-ended mode is used.

Programmable Gain Amplifier

Each encoder section’s analog front end comprises a switched
capacitor PGA that also forms part of the sigma-delta modula­tor. The SC sampling frequency is DMCLK/8. The PGA,
whose programmable gain settings are shown in Table II, may
be used to increase the signal level applied to the ADC from
low-output sources such as microphones, and can be used to
avoid placing external amplifiers in the circuit. The input signal
level to the sigma-delta modulator should not exceed the maxi­mum input voltage permitted.

The PGA gain is set by bits IGS0, IGS1, and IGS2 in control
Registers D, E, and F.

Table II. PGA Settings for the Encoder Channel

IxGS2 IxGS1 IxGS0 Gain (dB)

000 0
001 6
010 12
011 18
100 20
101 26
110 32
111 38

ADC

Each channel has its own ADC consisting of an analog sigma­delta modulator and a digital antialiasing decimation filter. The
sigma-delta modulator noise-shapes the signal and produces
1-bit samples at a DMCLK/8 rate. This bitstream, representing
the analog input signal, is input to the antialiasing decimation
filter. The decimation filter reduces the sample rate and increases
the resolution.

Analog Sigma-Delta Modulator

The AD73360L input channels employ a sigma-delta conver­sion technique, which provides a high resolution 16-bit output
with system filtering being implemented on-chip.

Sigma-delta converters employ a technique known as over­sampling, where the sampling rate is many times the highest
frequency of interest. In the case of the AD73360L, the initial
sampling rate of the sigma-delta modulator is DMCLK/8. The
main effect of oversampling is that the quantization noise is
spread over a very wide bandwidth, up to f

/2 = DMCLK/16

S

(Figure 6a). This means that the noise in the band of interest is
much reduced. Another complementary feature of sigma-delta
converters is the use of a technique called noise-shaping. This
technique has the effect of pushing the noise from the band of
interest to an out-of-band position (Figure 6b). The combina­tion of these techniques, followed by the application of a digital
filter, reduces the noise in band sufficiently to ensure good
dynamic performance from the part (Figure 6c).

BAND

OF

INTEREST

BAND

OF

INTEREST

a.

NOISE-SHAPING

f

/2

S

DMCLK/16

fS/2

DMCLK/16

b.

DIGITAL FILTER

BAND

OF

INTEREST

c.

/2

f

S

DMCLK/16

Figure 6. Sigma-Delta Noise Reduction

–8–

REV. 0

AD73360L

Figure 7 shows the various stages of filtering that are employed
in a typical AD73360L application. In Figure 7a we see the trans­fer function of the external analog antialias filter. Even though it
is a single RC pole, its cutoff frequency is sufficiently far away
from the initial sampling frequency (DMCLK/8) that it takes care
of any signals that could be aliased by the sampling frequency.
This also shows the major difference between the initial oversam­pling rate and the bandwidth of interest. In Figure 7b, the signal
and noise-shaping responses of the sigma-delta modulator are
shown. The signal response provides further rejection of any
high-frequency signals while the noise-shaping will push the
inherent quantization noise to an out-of-band position. The detail
of Figure 7c shows the response of the digital decimation filter
(sinc-cubed response) with nulls every multiple of DMCLK/
256, which is the decimation filter update rate. The final detail
in Figure 7d shows the application of a final antialias filter in the
DSP engine. This has the advantage of being implemented accord­ing to the user’s requirements and available MIPS. The filtering in
Figures 7a through 7c is implemented in the AD73360L.

= DMCLK/8

FB = 4kHz

F

SINIT

a. Analog Antialias Filter Transfer Function

SIGNAL TRANSFER FUNCTION

NOISE TRANSFER FUNCTION

FB = 4kHz

F

SINIT

= DMCLK/8

b. Analog Sigma-Delta Modulator Transfer Function

Decimation Filter

The digital filter used in the AD73360L carries out two impor­tant functions. Firstly, it removes the out-of-band quantization
noise, which is shaped by the analog modulator and secondly, it
decimates the high-frequency bitstream to a lower rate 15-bit word.

The antialiasing decimation filter is a sinc-cubed digital filter
that reduces the sampling rate from DMCLK/8 to DMCLK/
256, and increases the resolution from a single bit to 15 bits. Its
Z transform is given as: [(1–Z

–32

)/(1–Z–1)]3. This ensures a mini-

mal group delay of 25 µs.

Word growth in the decimator is determined by the sampling
rate. At 64 kHz sampling, where the oversampling ratio between
the sigma-delta modulator and decimator output equals 32,
there are five bits per stage of the three-stage Sinc

3

filter. Due to
symmetry within the sigma-delta modulator, the LSB will always
be a zero; therefore, the 16-bit ADC output word will have
2 LSBs equal to zero, one due to the sigma-delta symmetry and
the other being a padded zero to make up a 16-bit word. At
lower sampling rates, decimator word growth will be greater
than the 16-bit sample word, therefore truncation occurs in trans­ferring the decimator output as the ADC word. For example
at 8 kHz sampling, word growth reaches 24 bits due to the OSR
of 256 between sigma-delta modulator and decimator. This yields
eight bits per stage of the three stage Sinc

3

filter.

ADC Coding

The ADC coding scheme is in two’s complement format (see
Figure 8). The output words are formed by the decimation
filter, which grows the word length from the single-bit output of
the sigma-delta modulator to a 15-bit word, which is the final
output of the ADC block. In 16-bit Data Mode this value is left
shifted with the LSB being set to 0. For input values equal to or
greater than positive full scale, however, the output word is set
at 0x7FFF, which has the LSB set to 1. In mixed Control/Data
Mode, the resolution is fixed at 15 bits, with the MSB of the
16-bit transfer being used as a flag bit to indicate either control
or data in the frame.

V

+ (V

REF

ⴛ 0.32875)

REF

V

INN

REV. 0

F

F

= 4kHz

SINTER

= DMCLK/256

c. Digital Decimator Transfer Function

FB = 4kHz F

SFINAL

= 8kHz

SINTER

= DMCLK/256F

d. Final Filter LPF (HPF) Transfer Function

Figure 7. DC Frequency Responses

–9–

ANALOG

INPUT

ANALOG

INPUT

V

– (V

REF

V

+ (V

REF

V

– (V

REF

ⴛ 0.32875)

REF

ⴛ 0.6575)

REF

ⴛ 0.6575)

REF

V

REF

10...00

ADC CODE DIFFERENTIAL

V

10...00 00...00

ADC CODE SINGLE-ENDED

Figure 8. ADC Transfer Function

V

INP

00...00

INN

V

INP

01...11

01...11

AD73360L

Voltage Reference

The AD73360L reference, REFCAP, is a bandgap reference
that provides a low noise, temperature-compensated reference
to the ADC. A buffered version of the reference is also made
available on the REFOUT pin and can be used to bias other
external analog circuitry. The reference has a default nominal
value of 1.2 V.

The reference output (REFOUT) can be enabled for biasing
external circuitry by setting the RU bit (CRC:6) of CRC.

Serial Port (SPORT)

The AD73360Ls communicate with a host processor via the
bidirectional synchronous serial port (SPORT) which is compat­ible with most modern DSPs. The SPORT is used to transmit
and receive digital data and control information. Two AD73360Ls
can be cascaded together to provide additional input channels.

In both transmit and receive modes, data is transferred at the
serial clock (SCLK) rate with the MSB being transferred first.

Due to the fact that the SPORT of each AD73360L block uses
a common serial register for serial input and output, communi­cations between an AD73360L and a host processor (DSP
engine) must always be initiated by the AD73360Ls themselves.
In this configuration the AD73360Ls are described as being in
Master mode. This ensures that there is no collision between
input data and output samples.

SPORT Overview

The AD73360L SPORT is a flexible, full-duplex, synchronous
serial port whose protocol has been designed to allow up to
eight AD73360L devices to be connected in cascade, to a single
DSP via a six-wire interface. It has a very flexible architecture
that can be configured by programming two of the internal
control registers in each device. The AD73360L SPORT has
three distinct modes of operation: Control Mode, Data Mode
and Mixed Control/Data Mode.

MCLK

DMCLK

(INTERNAL)

SERIAL PORT

(SPORT)

3

88

B

SERIAL REGISTER

CONTROL
REGISTER

CONTROL

8

REGISTER

C

F

DIVIDER

8

CONTROL
REGISTER

D

CONTROL
REGISTER

G

SCLK

SCLK

SDOFS

SDO

2

CONTROL
REGISTER

CONTROL
REGISTER

8

E

H

SE

RESET

SDIFS

SDI

8

CONTROL
REGISTER

A

MCLK

DIVIDER

CONTROL
REGISTER

Figure 9. SPORT Block Diagram

Note: As each AD73360L has its own SPORT section, the
register settings in all SPORTs must be programmed. The regis­ters that control SPORT and sample rate operation (CRA and
CRB) must be programmed with the same values, otherwise
incorrect operation may occur.

In Program Mode (CRA:0 = 0), the device’s internal configura­tion can be programmed by writing to the eight internal control
registers. In this mode, control information can be written to or
read from the AD73360L. In Data Mode (CRA:0 = 1), any infor­mation that is sent to the device is ignored, while the encoder
section (ADC) data is read from the device. In this mode, only
ADC data is read from the device. Mixed mode (CRA:0 = 1 and
CRA:1 = 1) allows the user to send control information and
receive either control information or ADC data. This is achieved
by using the MSB of the 16-bit frame as a flag bit. Mixed mode
reduces the resolution to 15 bits with the MSB being used to
indicate whether the information in the 16-bit frame is control
information or ADC data.

The SPORT features a single 16-bit serial register that is used for
both input and output data transfers. As the input and output
data must share the same register, some precautions must be
observed. The primary precaution is that no information must be
written to the SPORT without reference to an output sample
event, which is when the serial register will be overwritten with
the latest ADC sample word. Once the SPORT starts to output
the latest ADC word, it is safe for the DSP to write new control
words to the AD73360L. In certain configurations, data can be
written to the device to coincide with the output sample being
shifted out of the serial register—see section on interfacing
devices. The serial clock rate (CRB:2–3) defines how many 16-bit
words can be written to a device before the next output sample
event will happen.

The SPORT block diagram, shown in Figure 9, details the blocks
associated with AD73360L including the eight control registers
(A–H), external MCLK to internal DMCLK divider and serial
clock divider. The divider rates are controlled by the setting of
Control Register B. The AD73360L features a master clock
divider that allows users the flexibility of dividing externally
available high-frequency DSP or CPU clocks to generate a lower
frequency master clock internally in the AD73360L which may be
more suitable for either serial transfer or sampling rate require­ments. The master clock divider has five divider options (÷1
default condition, ÷ 2, ÷ 3, ÷4, ÷ 5) that are set by loading the
master clock divider field in Register B with the appropriate
code (see Table XIII). Once the internal device master clock
(DMCLK) has been set using the master clock divider, the sample
rate and serial clock settings are derived from DMCLK.

The SPORT can work at four different serial clock (SCLK) rates:
chosen from DMCLK, DMCLK/2, DMCLK/4 or DMCLK/8,
where DMCLK is the internal or device master clock resulting
from the external or pin master clock being divided by the master
clock divider. Care should be taken when selecting Master Clock,
Serial Clock, and Sample Rate divider settings to ensure that
there is sufficient time to read all the data from the AD73360L
before the next sample interval.

–10–

REV. 0