Analog Devices AD73360 a Datasheet

Six-Input Channel

a

FEATURES
Six 16-Bit A/D Converters
Programmable Input Sample Rate
Simultaneous Sampling
77 dB SNR
64 kS/s Maximum Sample Rate

83 dB Crosstalk

–
Low Group Delay (25 ␮s Typ per ADC Channel)
Programmable Input Gain
Flexible Serial Port which Allows Multiple Devices to

Be Connected in Cascade
Single (+2.7 V to +5.5 V) Supply Operation
80 mW Max Power Consumption at +2.7 V
On-Chip Reference
28-Lead SOIC and 44-Lead TQFP Packages

APPLICATIONS
General Purpose Analog Input
Industrial Power Metering
Motor Control
Simultaneous Sampling Applications

GENERAL DESCRIPTION

The AD73360 is a six-input channel analog front-end processor
for general purpose applications including industrial power

Analog Front End

AD73360

metering or multichannel analog inputs. It features six 16-bit
A/D conversion channels each of which provide 77 dB signal-to­noise ratio over a dc to 4 kHz signal bandwidth. Each channel
also features a programmable input gain amplifier (PGA) with
gain settings in eight stages from 0 dB to 38 dB.

The AD73360 is particularly suitable for industrial power me­tering as each channel samples synchronously, ensuring that there
is no (phase) delay between the conversions. The AD73360 also
features low group delay conversions on all channels.

An on-chip reference voltage is included and is programmable
to accommodate either 3 V or 5 V operation.

The sampling rate of the device is programmable with four
separate settings offering 64 kHz, 32 kHz, 16 kHz and 8 kHz
sampling rates (from a master clock of 16.384 MHz).

A serial port (SPORT) allows easy interfacing of single or cas­caded devices to industry standard DSP engines. The SPORT
transfer rate is programmable to allow interfacing to both fast
and slow DSP engines.

The AD73360 is available in 28-lead SOIC and 44-lead TQFP
packages.

VINP1

VINN1

VINP2

VINN2

VINP3

VINN3

REFCAP

REFOUT

VINP4

VINN4

VINP5

VINN5

VINP6

VINN6

SIGNAL

CONDITIONING

SIGNAL

CONDITIONING

SIGNAL

CONDITIONING

SIGNAL

CONDITIONING

SIGNAL

CONDITIONING

SIGNAL

CONDITIONING

FUNCTIONAL BLOCK DIAGRAM

0/38dB

PGA

0/38dB

PGA

0/38dB

PGA

REFERENCE

0/38dB

PGA

0/38dB

PGA

0/38dB

PGA

ANALOG

⌺-⌬

MODULATOR

ANALOG

⌺-⌬

MODULATOR

ANALOG

⌺-⌬

MODULATOR

ANALOG

⌺-⌬

MODULATOR

ANALOG

⌺-⌬

MODULATOR

ANALOG

⌺-⌬

MODULATOR

DECIMATOR

DECIMATOR

DECIMATOR

AD73360

DECIMATOR

DECIMATOR

DECIMATOR

SERIAL

I/O

PORT

SDI

SDIFS

SCLK

RESET

MCLK

SE

SDO

SDOFS

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

AD73360–SPECIFICATIONS

(AVDD = 3 V ⴞ 10%; DVDD = 3 V ⴞ 10%; DGND = AGND = 0 V, f

1

f

= 8.192 MHz, fS = 8 kHz; TA = T

SCLK

MIN

to T

, unless otherwise noted.)

MAX

= 16.384 MHz,

MCLK

AD73360A

Parameter Min Typ Max Unit Test Conditions/Comments

REFERENCE

REFCAP

Absolute Voltage, V

REFCAP

1.125 1.25 1.375 V 5VEN = 0

REFCAP TC 50 ppm/°C 0.1 µF Capacitor Required from REFCAP

to AGND2

REFOUT

Typical Output Impedance 130 Ω
Absolute Voltage, V

REFOUT

1.125 1.25 1.375 V Unloaded
Minimum Load Resistance 1 kΩ
Maximum Load Capacitance 100 pF

ADC SPECIFICATIONS

Maximum Input Range at VIN

2, 3

1.644 V p-p 5VEN = 0, Measured Differentially
–2.85 dBm

Nominal Reference Level at VIN 1.1413 V p-p 5VEN = 0, Measured Differentially

(0 dBm0) –6.02 dBm

Absolute Gain

PGA = 0 dB –0.8 +0.8 dB 1.0 kHz
PGA = 38 dB –0.8 +0.8 dB 1.0 kHz

Gain Tracking Error ± 0.1 dB 1.0 kHz, +3 dBm0 to –50 dBm0
Signal to (Noise + Distortion)

PGA = 0 dB 73 77 dB 0 Hz to 4 kHz; f
PGA = 38 dB 62 dB 0 Hz to 4 kHz; f

= 8 kHz

S

= 64 kHz

S

Total Harmonic Distortion

PGA = 0 dB –83 –76 dB
PGA = 38 dB –70 dB

Intermodulation Distortion –76 dB PGA = 0 dB
Idle Channel Noise –70 dB PGA = 0 dB
Crosstalk ADC-to-ADC –83 dB ADC1 Input Signal Level: 1.0 kHz

ADC2 Input at Idle
DC Offset –30 +10 +45 mV PGA = 0 dB
Power Supply Rejection –55 dB Input Signal Level at AVDD and DVDD

Pins 1.0 kHz, 100 mV p-p Sine Wave
Group Delay

4, 5

25 µs 64 kHz Output Sample Rate
50 µs 32 kHz Output Sample Rate
95 µs 16 kHz Output Sample Rate
190 µs 8 kHz Output Sample Rate
25 kΩ

6

DMCLK = 16.384 MHz

Input Resistance at VIN

2, 4

FREQUENCY RESPONSE

(ADC)7 Typical Output

Frequency (Normalized to f

)

S

00dB

0.03125 –0.1 dB

0.0625 –0.25 dB

0.125 –0.6 dB

0.1875 –1.4 dB

0.25 –2.8 dB

0.3125 –4.5 dB

0.375 –7.0 dB

0.4375 –9.5 dB
> 0.5 < –12.5 dB

–2–

REV. A

AD73360

AD73360A

Parameter Min Typ Max Unit Test Conditions/Comments

LOGIC INPUTS

V

, Input High Voltage VDD – 0.8 V

INH

V

, Input Low Voltage 0 0.8 V

INL

, Input Current 10 µA

I

IH

DD

CIN, Input Capacitance 10 pF

LOGIC OUTPUTS

VOH, Output High Voltage VDD – 0.4 V

, Output Low Voltage 0 0.4 V |IOUT| ≤ 100 µA

V

OL

DD

Three-State Leakage Current –10 +10 µA

POWER SUPPLIES

AVDD1, AVDD2 2.7 3.3 V
DVDD 2.7 3.3 V

8

I

DD

NOTES

1

Operating temperature range is as follows: –40°C to +85°C. Therefore, T

2

Test conditions: Input PGA set for 0 dB gain (unless otherwise noted).

3

At input to sigma-delta modulator of ADC.

4

Guaranteed by design.

5

Overall group delay will be affected by the sample rate and the external digital filtering.

6

The ADC’s input impedance is inversely proportional to DMCLK and is approximated by: (4 × 1011)/DMCLK.

7

Frequency response of ADC measured with input at audio reference level (the input level that produces an output level of –10 dBm0), with 38 dB preamplifier
bypassed and input gain of 0 dB.

8

Test Conditions: no load on digital inputs, analog inputs ac coupled to ground.

Specifications subject to change without notice.

= –40°C and T

MIN

V

V |IOUT| ≤ 100 µA

See Table I

= +85°C.

MAX

Table I. Current Summary (AVDD = DVDD = 3.3 V)

Total

Analog Digital Current MCLK

Conditions Current Current (Max) SE ON Comments

ADCs Only On 12 10 26.5 1 YES REFOUT Disabled
REFCAP Only On 0.75 0.04 1.0 0 NO REFOUT Disabled
REFCAP and

REFOUT Only On 3.3 0.04 4.5 0 NO
All Sections Off 0.01 1.2 1.5 0 YES MCLK Active Levels Equal to 0 V and DVDD
All Sections Off 0.01 0.03 0.1 0 NO Digital Inputs Static and Equal to 0 V or DVDD

The above values are in mA and are typical values unless otherwise noted. MCLK = 16.384 MHz; SCLK = 16.384 MHz.

REV. A –3–

AD73360–SPECIFICATIONS

(AVDD = 5 V ⴞ 10%; DVDD = 5 V ⴞ 10%; DGND = AGND = 0 V, f

1

f

= 8.192 MHz, fS = 8 kHz; TA = T

SCLK

MIN

to T

, unless otherwise noted.)

MAX

= 16.384 MHz,

MCLK

AD73360A

Parameter Min Typ Max Unit Test Conditions/Comments

REFERENCE

REFCAP

Absolute Voltage, V

REFCAP

1.25 V 5VEN = 0

2.5 V 5VEN = 1

REFCAP TC 50 ppm/°C 0.1 µF Capacitor Required from REFCAP

to AGND2

REFOUT

Typical Output Impedance 130 Ω
Absolute Voltage, V

REFOUT

1.25 V 5VEN = 0, Unloaded

2.5 V 5VEN = 1, Unloaded
Minimum Load Resistance 2 kΩ 5VEN = 1
Maximum Load Capacitance 100 pF

ADC SPECIFICATIONS

Maximum Input Range at VIN

2, 3

3.2875 V p-p 5VEN = 1, Measured Differentially

3.17 dBm

Nominal Reference Level at VIN 2.2823 V p-p 5VEN = 1, Measured Differentially

(0 dBm0) 0 dBm

Absolute Gain

PGA = 0 dB 0.1 dB 1.0 kHz
PGA = 38 dB –0.5 dB 1.0 kHz

Gain Tracking Error ± 0.1 dB 1.0 kHz, +3 dBm0 to –50 dBm0
Signal to (Noise + Distortion)

PGA = 0 dB 76 dB 0 Hz to 4 kHz; f
PGA = 38 dB 70 dB 0 Hz to 4 kHz; f

= 8 kHz

S

= 64 kHz

S

Total Harmonic Distortion

PGA = 0 dB –86 dB
PGA = 38 dB –80 dB

Intermodulation Distortion –79 dB PGA = 0 dB
Idle Channel Noise –76 dB PGA = 0 dB
Crosstalk ADC-to-ADC –85 dB ADC1 Input Signal Level: 1.0 kHz, 0 dBm0

ADC2 Input at Idle
DC Offset 20 mV PGA = 0 dB
Power Supply Rejection –55 dB Input Signal Level at AVDD and DVDD

Pins 1.0 kHz, 100 mV p-p Sine Wave
Group Delay

4, 5

25 µs 64 kHz Output Sample Rate
50 µs 32 kHz Output Sample Rate
95 µs 16 kHz Output Sample Rate
190 µs 8 kHz Output Sample Rate
25 kΩ

6

DMCLK = 16.384 MHz

Input Resistance at VIN

2, 4

FREQUENCY RESPONSE

(ADC)7 Typical Output

Frequency (Normalized to f

)

S

00dB

0.03125 –0.1 dB

0.0625 –0.25 dB

0.125 –0.6 dB

0.1875 –1.4 dB

0.25 –2.8 dB

0.3125 –4.5 dB

0.375 –7.0 dB

0.4375 –9.5 dB
> 0.5 < –12.5 dB

–4–

REV. A

AD73360

AD73360A

Parameter Min Typ Max Unit Test Conditions/Comments

LOGIC INPUTS

V

, Input High Voltage VDD – 0.8 V

INH

V

, Input Low Voltage 0 0.8 V

INL

, Input Current –0.5 µA

I

IH

DD

CIN, Input Capacitance 10 pF

LOGIC OUTPUTS

VOH, Output High Voltage VDD – 0.4 V
V

, Output Low Voltage 0 0.4 V |IOUT| ≤ 100 µA

OL

DD

Three-State Leakage Current –0.3 µA

POWER SUPPLIES

AVDD1, AVDD2 4.5 5.5 V
DVDD 4.5 5.5 V

8

I

DD

NOTES

1

Operating temperature range is as follows: –40°C to +85°C. Therefore, T

2

Test conditions: Input PGA set for 0 dB gain (unless otherwise noted).

3

At input to sigma-delta modulator of ADC.

4

Guaranteed by design.

5

Overall group delay will be affected by the sample rate and the external digital filtering.

6

The ADC’s input impedance is inversely proportional to DMCLK and is approximated by: (4 × 1011)/DMCLK.

7

Frequency response of ADC measured with input at audio reference level (the input level that produces an output level of –10 dBm0), with 38 dB preamplifier
bypassed and input gain of 0 dB.

8

Test Conditions: no load on digital inputs, analog inputs ac coupled to ground.

Specifications subject to change without notice.

= –40°C and T

MIN

V

V |IOUT| ≤ 100 µA

See Table II

= +85°C.

MAX

Table II. Current Summary (AVDD = DVDD = 5.5 V)

Total

Analog Digital Current MCLK

Conditions Current Current (Typ) SE ON Comments

ADCs Only On 16 16 32 1 YES REFOUT Disabled
REFCAP Only On 0.8 0 0.8 0 NO REFOUT Disabled
REFCAP and

REFOUT Only On 3.5 0 3.5 0 NO
All Sections Off 0.1 1.9 2.0 0 YES MCLK Active Levels Equal to 0 V and DVDD
All Sections Off 0 0.05 0.06 0 NO Digital Inputs Static and Equal to 0 V or DVDD

The above values are in mA and are typical values unless otherwise noted.

Table III. Signal Ranges

3 V Power Supply 5 V Power Supply

5VEN = 0 5VEN = 0 5VEN = 1

V

REFCAP

V

REFOUT

1.25 V ± 10% 1.25 V 2.5 V

1.25 V ± 10% 1.25 V 2.5 V

ADC

Maximum Input Range at V

IN

1.64375 V p-p 1.64375 V p-p 3.2875 V p-p

Nominal Reference Level 1.1413 V p-p 1.1413 V p-p 2.2823 V p-p

REV. A –5–

AD73360

(AVDD = 3 V ⴞ 10%; DVDD = 3 V ⴞ 10%; AGND = DGND = 0 V; TA = T

TIMING CHARACTERISTICS

noted)

Limit at

Parameter TA = –40ⴗC to +85ⴗC Unit Description

Clock Signals See Figure 1

t

1

t

2

t

3

61 ns min MCLK Period

24.4 ns min MCLK Width High

24.4 ns min MCLK Width Low

Serial Port See Figures 3 and 4

t

4

t

5

t

6

t

7

t

8

t

9

t

10

t

11

t

12

t

13

t

1

0.4 × t

1

0.4 × t

1

20 ns min SDI/SDIFS Setup Before SCLK Low
0 ns min SDI/SDIFS Hold After SCLK Low
10 ns max SDOFS Delay from SCLK High
10 ns min SDOFS Hold After SCLK High
10 ns min SDO Hold After SCLK High
10 ns max SDO Delay from SCLK High
30 ns max SCLK Delay from MCLK

ns min SCLK Period
ns min SCLK Width High
ns min SCLK Width Low

MlN

to T

, unless otherwise

MAX

TIMING CHARACTERISTICS

(AVDD = 5 V ⴞ 10%; DVDD = 5 V ⴞ 10%; AGND = DGND = 0 V; TA = T
noted)

MlN

to T

Limit at

Parameter TA = –40ⴗC to +85ⴗC Unit Description

Clock Signals See Figure 1

t

1

t

2

t

3

61 ns min MCLK Period

24.4 ns min MCLK Width High

24.4 ns min MCLK Width Low

Serial Port See Figures 3 and 4

t

4

t

5

t

6

t

7

t

8

t

9

t

10

t

11

t

12

t

13

t

1

0.4 × t

0.4 × t

1

1

ns min SCLK Period
ns min SCLK Width High

ns min SCLK Width Low
20 ns min SDI/SDIFS Setup Before SCLK Low
0 ns min SDI/SDIFS Hold After SCLK Low
10 ns max SDOFS Delay from SCLK High
10 ns min SDOFS Hold After SCLK High
10 ns min SDO Hold After SCLK High
10 ns max SDO Delay from SCLK High
30 ns max SCLK Delay from MCLK

, unless otherwise

MAX

–6–

REV. A

AD73360

t

t

2

1

t

3

Figure 1. MCLK Timing

I

OL

+2.1V

I

OH

TO OUTPUT

PIN

15pF

100␮A

C

L

100␮A

Figure 2. Load Circuit for Timing Specifications

MCLK

SCLK*

t

1

t

13

* SCLK IS INDIVIDUALLY PROGRAMMABLE

IN FREQUENCY (MCLK/4 SHOWN HERE).

t

2

t

5

t

6

t

4

t

3

Figure 3. SCLK Timing

80

70

60

50

40

30

S/(N+D) – dB

20

10

0

–10

–85 5–75 –65 –55 –45 –35 –25 –15 –5

VIN – dBm0

3.17

Figure 5a. S/(N+D) vs. VIN (ADC @ 3 V) Over Voiceband
Bandwidth (300 Hz–3.4 kHz)

80

70

60

50

40

30

S/(N+D) – dB

20

10

0

–10

–85 5–75 –65 –55 –45 –35 –25 –15 –5

VIN – dBm0

3.17

Figure 5b. S/(N+D) vs. VIN (ADC @ 5 V) Over Voiceband
Bandwidth (300 Hz–3.4 kHz)

SCLK (O)

SDIFS (I)

SDOFS (O)

SDO (O)

REV. A

SE (I)

SDI (I)

THREE­STATE

THREE­STATE

THREE­STATE

t

7

t

8

t

9

t

10

t

t

12

11

D15 D2 D1 D0 D14

t

8

t

7

D0

D15D1D14D15

D15

Figure 4. Serial Port (SPORT)

–7–

AD73360

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

ORDERING GUIDE

(TA = +25°C unless otherwise noted)

AVDD, DVDD to GND . . . . . . . . . . . . . . . . . –0.3 V to +7 V

AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

Digital I/O Voltage to DGND . . . . . . –0.3 V to DVDD + 0.3 V

Analog I/O Voltage to AGND . . . . . –0.3 V to AVDD + 0.3 V

Operating Temperature Range

Industrial (A Version) . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Maximum Junction Temperature . . . . . . . . . . . . . . . . +150°C

SOIC, θ

Thermal Impedance . . . . . . . . . . . . . . . . . . 75°C/W

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi­tions for extended periods may affect device reliability.

Model Range Options

AD73360AR –40°C to +85°C R-28
AD73360ASU –40°C to +85°C SU-44
EVAL-AD73360EB Evaluation Board

EVAL-AD73360EZ Evaluation Board

NOTES

1

R = 0.3' Small Outline IC (SOIC); SU = Thin Quad Flatpack IC (TQFP).

2

The AD73360 evaluation board can be interfaced to an ADSP-2181 EZ-KIT Lite
or to a Texas Instruments EVM kit.

3

The upgrade consists of a connector for the expansion port P3 of the EZ-KIT
Lite. This option is intended for existing owners of EZ-KIT Lite.

4

The EZ-KIT Lite has been modified to allow it to interface with the AD73360
evaluation board. This option is intended for users who do not already have an
EZ-KIT Lite.

Temperature Package

+EZ-KIT Lite Upgrade

+EZ-KIT Lite

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD73360 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

1

2

3

2

4

PIN CONFIGURATIONS

R-28 SU-44

1

VINP2

VINN2

VINP1

VINN1

REFOUT

REFCAP

AVDD2

AGND2

DGND

DVDD

RESET

SCLK

MCLK

SDO

2

3

4

5

6

AD73360

7

TOP VIEW

(Not to Scale)

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

VINN3

VINP3

VINN4

VINP4

VINN5

VINP5

VINN6

VINP6

AVDD1

AGND1

SE

SDI

SDIFS

SDOFS

REFOUT

REFCAP

NC = NO CONNECT

AVDD2

AVDD2

AGND2

AGND2

AGND2

AGND2

DGND

DGND

DVDD

1

2

3

4

5

6

7

8

9

10

11

NC

VINN1

PIN 1
IDENTIFIER

VINP1

VINN2

VINP2

40 39 3841424344 36 35 3437

AD73360

TOP VIEW

(Not to Scale)

121314 1 5 16 1 7 18 192021 22

NC

RESETB

SCLK

MCLK

SDO

NC

NC

VINP3

VINN3

SDIFS

SDOFS

VINN4

SDI

VINP4

SE

NC

NC

33

32

31

30

29

28

27

26

25

24

23

NC

VINN5

VINP5

NC

VINN6

VINP6

NC

AVDD1

AVDD1

AGND1

AGND1

–8–

REV. A

AD73360

PIN FUNCTION DESCRIPTION

Mnemonic Function

VINP1 Analog Input to the Positive Terminal of Input Channel 1.
VINN1 Analog Input to the Negative Terminal of Input Channel 1.
VINP2 Analog Input to the Positive Terminal of Input Channel 2.
VINN2 Analog Input to the Negative Terminal of Input Channel 2.
VINP3 Analog Input to the Positive Terminal of Input Channel 3.
VINN3 Analog Input to the Negative Terminal of Input Channel 3.
VINP4 Analog Input to the Positive Terminal of Input Channel 4.
VINN4 Analog Input to the Negative Terminal of Input Channel 4.
VINP5 Analog Input to the Positive Terminal of Input Channel 5.
VINN5 Analog Input to the Negative Terminal of Input Channel 5.
VINP6 Analog Input to the Positive Terminal of Input Channel 6.
VINN6 Analog Input to the Negative Terminal of Input Channel 6.
REFOUT Buffered Reference Output, which has a nominal value of 1.25 V or 2.5 V, the value being dependent on the status

of Bit 5VEN (CRC:7).

REFCAP A Bypass Capacitor to AGND2 of 0.1 µF is required for the on-chip reference. The capacitor should be fixed to

this pin. This pin can be overdriven by an external reference if required.
AVDD2 Analog Power Supply Connection.
AGND2 Analog Ground/Substrate Connection.
DGND Digital Ground/Substrate Connection.
DVDD Digital Power Supply Connection.
RESET Active Low Reset Signal. This input resets the entire chip, resetting the control registers and clearing the digital

circuitry.
SCLK Output Serial Clock whose rate determines the serial transfer rate to/from the AD73360. It is used to clock data or

control information to and from the serial port (SPORT). The frequency of SCLK is equal to the frequency of the

master clock (MCLK) divided by an integer number—this integer number being the product of the external mas-

ter clock rate divider and the serial clock rate divider.
MCLK Master Clock Input. MCLK is driven from an external clock signal.
SDO Serial Data Output of the AD73360. Both data and control information may be output on this pin and are clocked

on the positive edge of SCLK. SDO is in three-state when no information is being transmitted and when SE is

low.
SDOFS Framing Signal Output for SDO Serial Transfers. The frame sync is one bit wide and it is active one SCLK period

before the first bit (MSB) of each output word. SDOFS is referenced to the positive edge of SCLK. SDOFS is in

three-state when SE is low.
SDIFS Framing Signal Input for SDI Serial Transfers. The frame sync is one bit wide and it is valid one SCLK period

before the first bit (MSB) of each input word. SDIFS is sampled on the negative edge of SCLK and is ignored

when SE is low.
SDI Serial Data Input of the AD73360. Both data and control information may be input on this pin and are clocked on

the negative edge of SCLK. SDI is ignored when SE is low.
SE SPORT Enable. Asynchronous input enable pin for the SPORT. When SE is set low by the DSP, the output pins

of the SPORT are three-stated and the input pins are ignored. SCLK is also disabled internally in order to decrease

power dissipation. When SE is brought high, the control and data registers of the SPORT are at their original values

(before SE was brought low); however, the timing counters and other internal registers are at their reset values.
AGND1 Analog Ground Connection.
AVDD1 Analog Power Supply Connection.

REV. A

–9–

AD73360

TERMINOLOGY
Absolute Gain

Absolute gain is a measure of converter gain for a known signal.
Absolute gain is measured (differentially) with a 1 kHz sine
wave at 0 dBm0 for each ADC. The absolute gain specification
is used for gain tracking error specification.

Crosstalk

Crosstalk is due to coupling of signals from a given channel to
an adjacent channel. It is defined as the ratio of the amplitude of
the coupled signal to the amplitude of the input signal. Crosstalk
is expressed in dB.

Gain Tracking Error

Gain tracking error measures changes in converter output for
different signal levels relative to an absolute signal level. The
absolute signal level is 0 dBm0 (equal to absolute gain) at 1 kHz
for each ADC. Gain tracking error at 0 dBm0 (ADC) is 0 dB by
definition.

Group Delay

Group Delay is defined as the derivative of radian phase with
respect to radian frequency, dø(f)/df. Group delay is a measure
of average delay of a system as a function of frequency. A linear
system with a constant group delay has a linear phase response.
The deviation of group delay from a constant indicates the de­gree of nonlinear phase response of the system.

Idle Channel Noise

Idle channel noise is defined as the total signal energy measured
at the output of the device when the input is grounded (mea­sured in the frequency range 0 Hz–4 kHz).

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m nor n are equal to zero. For final testing, the second
order terms include (fa + fb) and (fa – fb), while the third order
terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).

Power Supply Rejection

Power supply rejection measures the susceptibility of a device to
noise on the power supply. Power supply rejection is measured
by modulating the power supply with a sine wave and measuring
the noise at the output (relative to 0 dB).

Sample Rate

The sample rate is the rate at which each ADC updates its out­put register. It is set relative to the DMCLK and the program­mable sample rate setting.

SNR + THD

Signal-to-noise ratio plus harmonic distortion is defined to be
the ratio of the rms value of the measured input signal to the
rms sum of all other spectral components in a given frequency
range, including harmonics but excluding dc.

ABBREVIATIONS

ADC Analog-to-Digital Converter.

BW Bandwidth.

CRx A Control Register where x is a placeholder for

an alphabetic character (A–E). There are eight
read/write control registers on the AD73360—
designated CRA through CRE.

CRx:n A bit position, where n is a placeholder for a

numeric character (0–7), within a control regis­ter; where x is a placeholder for an alphabetic
character (A–E). Position 7 represents the MSB
and Position 0 represents the LSB.

DMCLK Device (Internal) Master Clock. This is the

internal master clock resulting from the external
master clock (MCLK) being divided by the on­chip master clock divider.

FSLB Frame Sync Loop-Back—where the SDOFS of

the final device in a cascade is connected to the
RFS and TFS of the DSP and the SDIFS of first
device in the cascade. Data input and output
occur simultaneously. In the case of nonFSLB,
SDOFS and SDO are connected to the Rx Port
of the DSP while SDIFS and SDI are connected
to the Tx Port.

PGA Programmable Gain Amplifier.

SC Switched Capacitor.

SNR Signal-to-Noise Ratio.

SPORT Serial Port.

THD Total Harmonic Distortion.

VBW Voice Bandwidth.

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REV. A

AD73360

FUNCTIONAL DESCRIPTION
General Description

The AD73360 is a six-channel, 16-bit, analog front end. It
comprises six independent encoder channels each featuring
signal conditioning, programmable gain amplifier, sigma-delta
A/D convertor and decimator sections. Each of these sections is
described in further detail below.

Encoder Channel

Each encoder channel consists of a signal conditioner, a
switched capacitor PGA and a sigma-delta analog-to-digital
converter (ADC). An on-board digital filter, which forms part
of the sigma-delta ADC, also performs critical system-level
filtering. Due to the high level of oversampling, the input
antialias requirements are reduced such that a simple single pole
RC stage is sufficient to give adequate attenuation in the band
of interest.

Signal Conditioner

Each analog channel has an independent signal conditioning
block. This allows the analog input to be configured by the user
depending on whether differential or single-ended mode is used.

Programmable Gain Amplifier

Each encoder section’s analog front end comprises a switched
capacitor PGA that also forms part of the sigma-delta modula­tor. The SC sampling frequency is DMCLK/8. The PGA,
whose programmable gain settings are shown in Table IV, may
be used to increase the signal level applied to the ADC from low
output sources such as microphones, and can be used to avoid
placing external amplifiers in the circuit. The input signal level
to the sigma-delta modulator should not exceed the maximum
input voltage permitted.

The PGA gain is set by bits IGS0, IGS1 and IGS2 in control
Registers D, E and F.

Analog Sigma-Delta Modulator

The AD73360 input channels employ a sigma-delta conversion
technique, which provides a high resolution 16-bit output with
system filtering being implemented on-chip.

Sigma-delta converters employ a technique known as over­sampling, where the sampling rate is many times the highest
frequency of interest. In the case of the AD73360, the initial
sampling rate of the sigma-delta modulator is DMCLK/8. The
main effect of oversampling is that the quantization noise is
spread over a very wide bandwidth, up to f

/2 = DMCLK/16

S

(Figure 6a). This means that the noise in the band of interest is
much reduced. Another complementary feature of sigma-delta
converters is the use of a technique called noise-shaping. This
technique has the effect of pushing the noise from the band of
interest to an out-of-band position (Figure 6b). The combina­tion of these techniques, followed by the application of a digital
filter, reduces the noise in band sufficiently to ensure good
dynamic performance from the part (Figure 6c).

BAND

OF

INTEREST

a.

NOISE-SHAPING

F

/2

S

DMCLK/16

Table IV. PGA Settings for the Encoder Channel

IxGS2 IxGS1 IxGS0 Gain (dB)

000 0
001 6
010 12
011 18
100 20
101 26
110 32
111 38

ADC

Each channel has its own ADC consisting of an analog sigma­delta modulator and a digital antialiasing decimation filter. The
sigma-delta modulator noise-shapes the signal and produces
1-bit samples at a DMCLK/8 rate. This bitstream, representing
the analog input signal, is input to the antialiasing decimation
filter. The decimation filter reduces the sample rate and in­creases the resolution.

BAND

OF

INTEREST

b.

DIGITAL FILTER

BAND

OF

INTEREST

c.

Figure 6. Sigma-Delta Noise Reduction

FS/2

DMCLK/16

F

/2

S

DMCLK/16

REV. A

–11–