Analog Devices AD73322LYST, AD73322LYRU, AD73322LYR, AD73322LAST, AD73322LARU Datasheet

Low Cost, Low Power CMOS

a

FEATURES
Two 16-Bit A/D Converters
Two 16-Bit D/A Converters
Programmable Input/Output Sample Rates
78 dB ADC SNR
78 dB DAC SNR
64 kS/s Maximum Sample Rate
–90 dB Crosstalk
Low Group Delay (25 s Typ per ADC Channel,

50 s Typ per DAC Channel)
Programmable Input/Output Gain
Flexible Serial Port which Allows Up to Four Dual

Codecs to be Connected in Cascade Giving Eight

I/O Channels
Single (2.7 V to 3.3 V) Supply Operation
50 mW Typ Power Consumption at 3.0 V
Temperature Range: –40C to +105C
On-Chip Reference
28-Lead SOIC, TSSOP, and 44-Lead LQFP Packages

APPLICATIONS
General-Purpose Analog I/O
Speech Processing
Cordless and Personal Communications
Telephony
Active Control of Sound and Vibration
Data Communications
Wireless Local Loop

General-Purpose Dual Analog Front End

AD73322L

FUNCTIONAL BLOCK DIAGRAM

VFBP1

VINP1

VINN1

VFBN1

VOUTP1

VOUTN1

REFOUT

REFCAP

VFBP2

VINP2

VINN2

VFBN2

VOUTP2

VOUTN2

AVDD1 AVDD2

ADC CHANNEL 1

DAC CHANNEL 1

REFERENCE

ADC CHANNEL 2

DAC CHANNEL 2

AGND1 AGND2 DGND

DVDD

AD73322L

SPORT

SDI

SDIFS

SCLK

SE

RESET

MCLK

SDOFS

SDO

GENERAL DESCRIPTION

The AD73322L is a dual front-end processor for general pur­pose applications including speech and telephony. It features
two 16-bit A/D conversion channels and two 16-bit D/A con­version channels. Each channel provides 78 dB signal-to-noise
ratio over a voiceband signal bandwidth. It also features an
input-to-output gain network in both the analog and digital
domains. This is featured on both codecs and can be used for
impedance matching or scaling when interfacing to Subscriber
Line Interface Circuits (SLICs).

The AD73322L is particularly suitable for a variety of applica­tions in the speech and telephony area, including low bit rate,
high quality compression, speech enhancement, recognition and
synthesis. The low group delay characteristic of the part makes
it suitable for single or multichannel active control applications.

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

The A/D and D/A conversion channels feature programmable
input/output gains with ranges 38 dB and 21 dB respectively.
An on-chip reference voltage is included to allow single­supply operation.

The sampling rate of the codecs is programmable with four
separate settings offering 64 kHz, 32 kHz, 16 kHz, and 8 kHz
sampling rates (from a master clock of 16.384 MHz).

A serial port (SPORT) allows easy interfacing of single or cas­caded devices to industry standard DSP engines. The SPORT
transfer rate is programmable to allow interfacing to both fast
and slow DSP engines.

The AD73322L is available in 28-lead SOIC, 28-lead TSSOP,
and 44-lead LQFP packages.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2001

AD73322L–SPECIFICATIONS

(AVDD = 3 V  10%; DVDD = 3 V  10%; DGND = AGND = 0 V, f

1

16.384 MHz, f

= 8 kHz; TA = T

SAMP

MIN

to T

, unless otherwise noted.)

MAX

DMCLK

=

A, Y Versions

Parameter Min Typ Max Unit Test Conditions/Comments

REFERENCE

REFCAP

Absolute Voltage, VREFCAP 1.08 1.2 1.32 V
REFCAP TC 50 ppm/°C 0.1 µF Capacitor Required from

REFOUT REFCAP to AGND2

Typical Output Impedance 130 Ω
Absolute Voltage, V

REFOUT

1.08 1.2 1.32 V Unloaded
Minimum Load Resistance 1 kΩ
Maximum Load Capacitance 100 pF

INPUT AMPLIFIER

Offset ± 1.0 mV
Maximum Output Swing 1.578 V Max Output Swing = (1.578/1.2) × VREFCAP
Feedback Resistance 50 kΩ f

= 32 kHz

C

Feedback Capacitance 100 pF

ANALOG GAIN TAP

Gain at Maximum Setting +1
Gain at Minimum Setting –1
Gain Resolution 5 Bits Gain Step Size = 0.0625
Gain Accuracy ± 1.0 % Output Unloaded
Settling Time 1.0 µs Tap Gain Change of –FS to +FS
Delay 0.5 µs

ADC SPECIFICATIONS DAC Unloaded

Maximum Input Range at VIN

2, 3

1.578 V p-p Measured Differentially
–2.85 dBm Max Input = (1.578/1.2) × VREFCAP

Nominal Reference Level at VIN 1.0954 V p-p Measured Differentially

(0 dBm0) –6.02 dBm

Absolute Gain

PGA = 0 dB –2.0 –0.7 +0.5 dB 1.0 kHz, 0 dBm0

Gain Tracking Error ± 0.1 dB 1.0 kHz, +3 dBm0 to –50 dBm0
Signal to (Noise + Distortion) Refer to TPC 1.

PGA = 0 dB 70 78 dB 300 Hz to 3400 Hz; f

79 dB 300 Hz to 3400 Hz; f

77.5 dB 0 Hz to f

SAMP

/2; f

SAMP

= 8 kHz, PUIA = 0

SAMP

= 8 kHz, PUIA = 1

SAMP

= 8 kHz

Total Harmonic Distortion

PGA = 0 dB –86 –75 dB 300 Hz to 3400 Hz; f

SAMP

= 8 kHz
Intermodulation Distortion –61 dB PGA = 0 dB
Idle Channel Noise Crosstalk –72 dBm0 PGA = 0 dB

ADC-to-DAC –107 dB ADC Input Signal Level: 1.0 kHz, 0 dBm0

DAC Input at Idle

ADC-to-ADC –92 dB ADC1 Input Signal Level: 1.0 kHz, 0 dBm0

ADC2 Input at Idle. Input Amplifiers Bypassed

–93 dB Input Amplifiers Included in Input Channel
DC Offset –20 0 +20 mV PGA = 0 dB
Power Supply Rejection –65 dB Input Signal Level at AVDD and DVDD

Group Delay

4, 5

Input Resistance at PGA

2, 4, 6

25 µs

20 kΩ Input Amplifiers Bypassed

Pins: 1.0 kHz, 100 mV p-p Sine Wave

DIGITAL GAIN TAP

Gain at Maximum Setting +1
Gain at Minimum Setting –1
Gain Resolution 16 Bits Tested to 5 MSBs of Settings
Delay 25 µs Includes DAC Delay
Settling Time 100 µs Tap Gain Change from –FS to +FS; Includes

DAC Settling Time

–2–

REV. 0

AD73322L

A, Y Versions

Parameter Min Typ Max Unit Test Conditions/Comments

DAC SPECIFICATIONS DAC Unloaded

Maximum Voltage Output Swing

Single-Ended 1.578 V p-p PGA = 6 dB

Differential 3.156 V p-p PGA = 6 dB

Nominal Voltage Output Swing (0 dBm0)

Single-Ended 1.0954 V p-p PGA = 6 dB

Differential 2.1909 V p-p PGA = 6 dB

Output Bias Voltage 1.2 V REFOUT Unloaded
Absolute Gain –1.75 –0.6 +0.75 dB 1.0 kHz, 0 dBm0; Unloaded
Gain Tracking Error ± 0.1 dB 1.0 kHz, +3 dBm0 to –50 dBm0
Signal to (Noise + Distortion) at 0 dBm0 Refer to TPC 2.

PGA = 0 dB 72 78.5 dB 300 Hz to 3400 Hz; f

Total Harmonic Distortion at 0 dBm0

PGA = 0 dB –89 –75 dB 300 Hz to 3400 Hz; f
Intermodulation Distortion –77 dB PGA = 0 dB
Idle Channel Noise Crosstalk –81 dBm0 PGA = 0 dB

DAC-to-ADC –73 dB ADC Input Signal Level: AGND; DAC

DAC-to-DAC –102 dB DAC1 Output Signal Level: AGND; DAC2

Power Supply Rejection –65 dB Input Signal Level at AVDD and DVDD

Group Delay

Output DC Offset
Minimum Load Resistance, R

Single-Ended

4, 5

2, 7

4

Differential 150 Ω
Maximum Load Capacitance, C

Single-Ended 500 pF

Differential 100 pF

FREQUENCY RESPONSE

(ADC and DAC)

9

Typical Output

Frequency (Normalized to FS)

00dB

0.03125 –0.1 dB

0.0625 –0.25 dB

0.125 –0.6 dB

0.1875 –1.4 dB

0.25 –2.8 dB

0.3125 –4.5 dB

0.375 –7.0 dB

0.4375 –9.5 dB

> 0.5 < –12.5 dB

2

–2.85 dBm Max Output = (1.578/1.2) × VREFCAP

3.17 dBm Max Output = 2 × ([1.578/1.2] × VREFCAP)

–6.02 dBm

0 dBm

= 8 kHz

SAMP

= 8 kHz

SAMP

Output Signal Level: 1.0 kHz, 0 dBm0
Input Amplifiers Bypassed

–74 dB Input Amplifiers Included in Input Channel

Output Signal Level: 1.0 kHz, 0 dBm0

Pins: 1.0 kHz, 100 mV p-p Sine Wave
25 µs Interpolator Bypassed
50 µs

2, 8

L

–50 +5 +60 mV

150 Ω

2, 8

L

REV. 0

–3–

AD73322L

A, Y Versions

Parameter Min Typ Max Unit Test Conditions/Comments

LOGIC INPUTS

V

, Input High Voltage DVDD – 0.8 DVDD V

INH

, Input Low Voltage 0 0.8 V

V

INL

I

, Input Current –10 +10 µA

IH

CIN, Input Capacitance 10 pF

LOGIC OUTPUT

, Output High Voltage DVDD – 0.4 DVDD V |IOUT| ≤ 100 µA

V

OH

, Output Low Voltage 0 0.4 V |IOUT| ≤ 100 µA

V

OL

Three-State Leakage Current –10 +10 µA

POWER SUPPLIES

AVDD1, AVDD2 2.7 3.3 V
DVDD 2.7 3.3 V

10

I

DD

NOTES

1

Operating temperature range as follows: A Grade, T

2

Test conditions: Input PGA set for 0 dB gain, Output PGA set for 6 dB gain, no load on analog outputs (unless otherwise noted).

3

At input to sigma-delta modulator of ADC.

4

Guaranteed by design.

5

Overall group delay will be affected by the sample rate and the external digital filtering.

6

The ADC’s input impedance is inversely proportional to DMCLK and is approximated by: (3.3 × 1011)/DMCLK.

7

Between VOUTP1 and VOUTN1 or between VOUTP2 and VOUTN2.

8

At VOUT output.

9

Frequency responses of ADC and DAC measured with input at audio reference level (the input level that produces an output level of –10 dBm0), with 38 dB pream­plifier bypassed and input gain of 0 dB.

10

Test Conditions: no load on digital inputs, analog inputs ac-coupled to ground, no load on analog outputs.

Specifications subject to change without notice.

= –40°C, T

MIN

= +85°C; Y Grade, T

MAX

= –40°C, T

MIN

See Table I

= +105°C.

MAX

Table I. Current Summary (AVDD = DVDD = 3.3 V)

Analog Digital Total Current Total Current MCLK

Conditions Current Current (Typ) (Max) SE ON Comments

ADCs On Only 3.4 6.3 9.7 12 1 YES REFOUT Disabled
DACs On Only 8.8 6.5 15.3 20 1 YES REFOUT Disabled
ADCs and DACs On 11.6 7.0 18.6 23 1 YES REFOUT Disabled
ADCs and DACs

and Input Amps On 13.8 7.0 20.8 26 1 YES REFOUT Disabled

ADCs and DACs

and AGT On 13.2 7.0 20.2 26 1 YES REFOUT Disabled
All Sections On 17.2 7.0 24.2 31 1 YES
REFCAP On Only 0.65 0 0.67 1.25 0 NO REFOUT Disabled
REFCAP and

REFOUT On Only 2.56 0 2.57 4.5 0 NO
All Sections Off 0 1.25 1.25 1.8 0 YES MCLK Active Levels Equal to

0 V and DVDD

All Sections Off 0 µA 12.5 µA 12.7 µA 40 µA 0 NO Digital Inputs Static and Equal

to 0 V or DVDD

The above values are in mA and are typical values unless otherwise noted.

–4–

REV. 0

Table II. Signal Ranges

3 V Power Supply
5VEN = 0

VREFCAP 1.2 V ± 10%
VREFOUT 1.2 V ± 10%
ADC Maximum Input Range at V

IN

1.578 V p-p

Nominal Reference Level 1.0954 V p-p

DAC Maximum Voltage Output Swing

Single-Ended 1.578 V p-p
Differential 3.156 V p-p

Nominal Voltage Output Swing

Single-Ended 1.0954 V p-p
Differential 2.1909 V p-p

Output Bias Voltage VREFOUT

AD73322L

TIMING CHARACTERISTICS

(AVDD = 3 V  10%; DVDD = 3 V  10%; AGND = DGND = 0 V; TA = T
otherwise noted.)

MlN

to T

MAX

Limit at

Parameter TA = –40C to +105C Unit Description

Clock Signals See Figure 1

t

1

t

2

t

3

61 ns min MCLK Period

24.4 ns min MCLK Width High

24.4 ns min MCLK Width Low

Serial Port See Figures 3 and 4

t

4

t

5

t

6

t

7

t

8

t

9

t

10

t

11

t

12

t

13

Specifications subject to change without notice.

t

1

0.4 × t

0.4 × t

1

1

ns min SCLK Period
ns min SCLK Width High

ns min SCLK Width Low
20 ns min SDI/SDIFS Setup Before SCLK Low
0 ns min SDI/SDIFS Hold After SCLK Low
10 ns max SDOFS Delay from SCLK High
10 ns min SDOFS Hold After SCLK High
10 ns min SDO Hold After SCLK High
10 ns max SDO Delay from SCLK High
30 ns max SCLK Delay from MCLK

, unless

REV. 0

–5–

AD73322L

t

t

2

1

TO OUTPUT

PIN

t

3

15pF

100A

C

L

100A

I

OL

2.1V

I

OH

SE (I)

SCLK (O)

SDIFS (I)

SDI (I)

SDOFS (O)

SDO (O)

Figure 1. MCLK Timing

THREE­STATE

t

THREE­STATE

THREE­STATE

9

MCLK

SCLK*

Figure 2. Load Circuit for Timing Specifications

t

1

t

13

* SCLK IS INDIVIDUALLY PROGRAMMABLE

IN FREQUENCY (MCLK/4 SHOWN HERE).

t

2

t

5

t

t

4

6

t

3

Figure 3. SCLK Timing

t

7

t

8

t

8

t

7

t

10

t

12

t

11

D15 D2 D1 D0 D14

D15D0D1D14D15

D15

Figure 4. Serial Port (SPORT)

–6–

REV. 0

AD73322L

WARNING!

ESD SENSITIVE DEVICE

3

4

5

6

7

1

2

10

11

8

9

40 39 3841424344 36 35 3437

29

30

31

32

33

27

28

25

26

23

24

PIN 1
IDENTIFIER

TOP VIEW

(Not to Scale)

AD73322L

121314 15 16 1 7 18 192021 22

NC

VOUTN1

VOUTP1

NC

VOUTN2

VOUTP2

NC

REFOUT

REFCAP

AVDD2

AVDD2

AGND2

AGND2

AGND2

NC = NO CONNECT

AGND2

DGND

DGND

DVDD

AVDD1

SDI

NC

AVDD1

SDIFS

AGND1

AGND1

NC

VFBN1

NC

RESET

VFBP1

VINN2

VFBP2

VINP2

NC

VINP1

SCLK

MCLK

SDO

VINN1

NC

SDOFS

VFBN2

SE

NC

ABSOLUTE MAXIMUM RATINGS*

(TA = 25°C unless otherwise noted)

AVDD, DVDD to GND . . . . . . . . . . . . . . . –0.3 V to +4.6 V

AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

Digital I/O Voltage to DGND . . . –0.3 V to (DVDD + 0.3 V)
Analog I/O Voltage to AGND . . . –0.3 V to (AVDD + 0.3 V)
Operating Temperature Range

Industrial (A Version) . . . . . . . . . . . . . . . –40°C to +85°C

Extended (Y Version) . . . . . . . . . . . . . . . . –40°C to +105°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

TSSOP, θJA Thermal Impedance . . . . . . . . . . . . . . 97.9°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

ORDERING GUIDE

Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C

SOIC, θ

Thermal Impedance . . . . . . . . . . . . . . . 71.4°C/W

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

LQFP, θ

Thermal Impedance . . . . . . . . . . . . . . . 53.2°C/W

JA

Model Range Descriptions Option

AD73322LAR –40°C to +85°C Wide Body SOIC R-28
AD73322LARU –40°C to +85°C Thin Shrink TSSOP RU-28
AD73322LAST –40°C to +85°C Plastic Thin Quad ST-44A

Temperature Package Package

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

AD73322LYR –40°C to +105°C Wide Body SOIC R-28
AD73322LYRU –40°C to +105°C Thin Shrink TSSOP RU-28
AD73322LYST –40°C to +105°C Plastic Thin Quad ST-44A

EVAL-AD73322LEB Evaluation Board

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD73322L features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

Flatpack (LQFP)

Flatpack (LQFP)

28-Lead Wide Body SOIC

(R-28)

1

VINP1

2

VFBP1

3

VINN1

4

VFBN1

AVDD2

AGND2

DGND

DVDD

RESET

SCLK

MCLK

SDO

10

11

12

13

14

5

6

AD73322L

7

TOP VIEW

(Not to Scale)

8

9

REFOUT

REFCAP

REV. 0

28

27

26

25

24

23

22

21

20

19

18

17

16

15

VFBN2

VINN2

VFBP2

VINP2

VOUTN1

VOUTP1

VOUTN2

VOUTP2

AVDD1

AGND1

SE

SDI

SDIFS

SDOFS

PIN CONFIGURATIONS

28-Lead Thin Shrink TSSOP

(RU-28)

1

VINP1

2

VFBP1

3

VINN1

4

VFBN1

5

REFOUT

6

REFCAP

AVDD2

AGND2

DGND

DVDD

RESET

SCLK

MCLK

SDO

AD73322L

7

TOP VIEW

(Not to Scale)

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

44-Lead Plastic Thin Quad Flatpack (LQFP)

(ST-44A)

VFBN2

VINN2

VFBP2

VINP2

VOUTN1

VOUTP1

VOUTN2

VOUTP2

AVDD1

AGND1

SE

SDI

SDIFS

SDOFS

–7–

AD73322L

PIN FUNCTION DESCRIPTIONS

Mnemonic Function

VINP1 Analog Input to the inverting input amplifier on Channel 1’s positive input.
VFBP1 Feedback Connection from the output of the inverting amplifier on Channel 1’s positive input. When the input

amplifiers are bypassed, this pin allows direct access to the positive input of Channel 1’s sigma-delta modulator.
VINN1 Analog Input to the inverting input amplifier on Channel 1’s negative input.
VFBN1 Feedback connection from the output of the inverting amplifier on Channel 1’s negative input. When the input

amplifiers are bypassed, this pin allows direct access to the negative input of Channel 1’s sigma-delta modulator.
REFOUT Buffered Reference Output, which has a nominal value of 1.2 V or 2.4 V, the value being dependent on the status

of Bit 5VEN (CRC:7). As the reference is common to the two codec units, the reference value is set by the wired

OR of the CRC:7 bits in Control Register C of each channel.
REFCAP A bypass capacitor to AGND2 of 0.1 µF is required for the on-chip reference. The capacitor should be fixed to

this pin.
AVDD2 Analog Power Supply Connection.
AGND2 Analog Ground/Substrate Connection2.
DGND Digital Ground/Substrate Connection.
DVDD Digital Power Supply Connection.
RESET Active Low Reset Signal. This input resets the entire chip, resetting the control registers and clearing the digital

circuitry.
SCLK Serial Clock Output whose rate determines the serial transfer rate to/from the codec. It is used to clock data or

control information to and from the serial port (SPORT). The frequency of SCLK is equal to the frequency of the

master clock (MCLK) divided by an integer number—this integer number being the product of the external mas-

ter clock rate divider and the serial clock rate divider.
MCLK Master Clock Input. MCLK is driven from an external clock signal.
SDO Serial Data Output. Both data and control information may be output on this pin and are clocked on the positive

edge of SCLK. SDO is in three-state when no information is being transmitted and when SE is low.
SDOFS Framing Signal Output for SDO Serial Transfers. The frame sync is one bit wide and is active one SCLK period

before the first bit (MSB) of each output word. SDOFS is referenced to the positive edge of SCLK. SDOFS is in

three-state when SE is low.
SDIFS Framing Signal Input for SDI Serial Transfers. The frame sync is one bit wide and is valid one SCLK period

before the first bit (MSB) of each input word. SDIFS is sampled on the negative edge of SCLK and is ignored

when SE is low.
SDI Serial Data Input. Both data and control information may be input on this pin and are clocked on the negative

edge of SCLK. SDI is ignored when SE is low.
SE SPORT Enable. Asynchronous input enable pin for the SPORT. When SE is set low by the DSP, the output

pins of the SPORT are three-stated and the input pins are ignored. SCLK is also disabled internally in order to

decrease power dissipation. When SE is brought high, the control and data registers of the SPORT are at their

original values (before SE was brought low); however, the timing counters and other internal registers are at

their reset values.
AGND1 Analog Ground/Substrate Connection.
AVDD1 Analog Power Supply Connection.
VOUTP2 Analog Output from the Positive Terminal of Output Channel 2.
VOUTN2 Analog Output from the Negative Terminal of Output Channel 2.
VOUTP1 Analog Output from the Positive Terminal of Output Channel 1.
VOUTN1 Analog Output from the Negative Terminal of Output Channel 1.
VINP2 Analog Input to the inverting input amplifier on Channel 2’s positive input.
VFBP2 Feedback connection from the output of the inverting amplifier on Channel 2’s positive input. When the input

amplifiers are bypassed, this pin allows direct access to the positive input of Channel 2’s sigma-delta modulator.
VINN2 Analog Input to the inverting input amplifier on Channel 2’s negative input.
VFBN2 Feedback connection from the output of the inverting amplifier on Channel 2’s negative input. When the input

amplifiers are bypassed, this pin allows direct access to the negative input of Channel 2’s sigma-delta modulator.

–8–

REV. 0

AD73322L

TERMINOLOGY
Absolute Gain

Absolute gain is a measure of converter gain for a known signal.
Absolute gain is measured (differentially) with a 1 kHz sine wave at
0 dBm0 for the DAC and with a 1 kHz sine wave at 0 dBm0 for
the ADC. The absolute gain specification is used for gain track­ing error specification.

Crosstalk

Crosstalk is due to coupling of signals from a given channel to
an adjacent channel. It is defined as the ratio of the amplitude of
the coupled signal to the amplitude of the input signal. Crosstalk
is expressed in dB.

Gain Tracking Error

Gain tracking error measures changes in converter output for
different signal levels relative to an absolute signal level. The
absolute signal level is 0 dBm0 (equal to absolute gain) at 1 kHz
for the DAC and 0 dBm0 (equal to absolute gain) at 1 kHz for
the ADC. Gain tracking error at 0 dBm0 (ADC) and 0 dBm0
(DAC) is 0 dB by definition.

Group Delay

Group Delay is defined as the derivative of radian phase with
respect to radian frequency, dø(f)/df. Group delay is a measure
of average delay of a system as a function of frequency. A linear
system with a constant group delay has a linear phase response.
The deviation of group delay from a constant indicates the
degree of nonlinear phase response of the system.

Idle Channel Noise

Idle channel noise is defined as the total signal energy measured
at the output of the device when the input is grounded (mea­sured in the frequency range 300 Hz–3400 Hz).

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m nor n is equal to zero. For final testing, the second
order terms include (fa + fb) and (fa – fb), while the third order
terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).

Power Supply Rejection

Power supply rejection measures the susceptibility of a device to
noise on the power supply. Power supply rejection is measured
by modulating the power supply with a sine wave and measuring
the noise at the output (relative to 0 dB).

Sample Rate

The sample rate is the rate at which the ADC updates its output
register and the DAC updates its output from its input register.
The sample rate can be chosen from a list of four that are fixed
relative to the DMCLK. Sample rate is set by programming bits
DIR0-1 in Control Register B of each channel.

SNR+THD

Signal-to-noise ratio plus harmonic distortion is defined to be
the ratio of the rms value of the measured input signal to the
rms sum of all other spectral components in the frequency range
300 Hz–3400 Hz, including harmonics but excluding dc.

ABBREVIATIONS

ADC Analog-to-Digital Converter.

AFE Analog Front End.

AGT Analog Gain Tap.

ALB Analog Loop-Back.

BW Bandwidth.

CRx A Control Register where x is a placeholder for an

alphabetic character (A–E). There are five read/
write control registers on the AD73322L—desig­nated CRA through CRE.

CRx:n A bit position, where n is a placeholder for a nu-

meric character (0–7), within a control register,
where x is a placeholder for an alphabetic charac­ter (A–E). Position 7 represents the MSB and
Position 0 represents the LSB.

DAC Digital-to-Analog Converter.

DGT Digital Gain Tap.

DLB Digital Loop-Back.

DMCLK Device (Internal) Master Clock. This is the inter-

nal master clock resulting from the external master
clock (MCLK) being divided by the on-chip mas­ter clock divider.

FS Full Scale.

FSLB Frame Sync Loop-Back—where the SDOFS of

the final device in a cascade is connected to the
RFS and TFS of the DSP and the SDIFS of
first device in the cascade. Data input and out­put occur simultaneously. In the case of NonFSLB,
SDOFS and SDO are connected to the Rx Port
of the DSP while SDIFS and SDI are connected
to the Tx Port.

PGA Programmable Gain Amplifier.

SC Switched Capacitor.

SLB Sport Loop-Back.

SNR Signal-to-Noise Ratio.

SPORT Serial Port.

THD Total Harmonic Distortion.

VBW Voice Bandwidth.

REV. 0

–9–

AD73322L

–Typical Performance Characteristics

80

70

60

50

40

30

S/(N+D) – dB

20

10

0

–10

–85 5–75 –65 –55 –45 –35 –25 –15 –5

VIN – dBm0

3.17

TPC 1. S/(N+D) vs. VIN (ADC @ 3 V) over Voiceband
Bandwidth (300 Hz–3.4 kHz)

80

70

60

50

40

30

S/(N+D) – dB

20

10

0

–10

–85 5–75 –65 –55 –45 –35 –25 –15 –5

VIN – dBm0

3.17

TPC 2. S/(N+D) vs. VIN (DAC @ 3 V) over Voiceband
Bandwidth (300 Hz–3.4 kHz)

DVDDAVDD2AVDD1

VFBN1

VINN1

VINP1

VFBP1

VOUTP1

VOUTN1

REFCAP

REFOUT

VFBN2

VINN2

VINP2

VFBP2

V

REF

ANALOG

LOOP
BACK

+6/15dB

PGA

GAIN

CONTINUOUS

LOW-PASS

FILTER

REFERENCE

1

TIME

INVERT

SINGLE-ENDED

ENABLE

SWITCHED

CAPACITOR

LOW-PASS

FILTER

0/38dB

PGA

1-BIT

DAC

ANALOG

SIGMA-DELTA

MODULATOR

DIGITAL

SIGMA­DELTA

MODULATOR

GAIN

1

DECIMATOR

INTER-

POLATOR

SERIAL

I/O

PORT

SDI

SDIFS

SCLK

RESET

MCLK

SE

AD73322L

SDO

V

REF

ANALOG

LOOP
BACK

GAIN

1

INVERT

SINGLE-ENDED

ENABLE

0/38dB

PGA

ANALOG

SIGMA-DELTA

MODULATOR

GAIN

1

DECIMATOR

SDOFS

VOUTP2

VOUTN2

CONTINUOUS

+6/–15dB

PGA

AGND1 AGND2 DGND

TIME

LOW-PASS

FILTER

SWITCHED

CAPACITOR

LOW-PASS

FILTER

1-BIT

DAC

DIGITAL

SIGMA­DELTA

MODULATOR

Figure 5. Functional Block Diagram

–10–

INTER-

POLATOR

REV. 0

AD73322L

FUNCTIONAL DESCRIPTION
Encoder Channels

Both encoder channels consist of a pair of inverting op amps
with feedback connections that can be bypassed if required, a

interest to an out-of-band position (Figure 7b). The combina­tion of these techniques, followed by the application of a digital
filter, sufficiently reduces the noise in band to ensure good

dynamic performance from the part (Figure 7c).
switched capacitor PGA and a sigma-delta analog-to-digital
converter (ADC). An on-board digital filter, which forms part of
the sigma-delta ADC, also performs critical system-level filtering.
Due to the high level of oversampling, the input antialias require­ments are reduced such that a simple single pole RC stage is
sufficient to give adequate attenuation in the band of interest.

Programmable Gain Amplifier

Each encoder section’s analog front end comprises a switched
capacitor PGA, which also forms part of the sigma-delta modula­tor. The SC sampling frequency is DMCLK/8. The PGA, whose
programmable gain settings are shown in Table III, may be used
to increase the signal level applied to the ADC from low output
sources such as microphones, and can be used to avoid placing
external amplifiers in the circuit. The input signal level to the
sigma-delta modulator should not exceed the maximum input
voltage permitted.

The PGA gain is set by bits IGS0, IGS1 and IGS2 (CRD:0–2)
in control register D.

Table III. PGA Settings for the Encoder Channel

IGS2 IGS1 IGS0 Gain (dB)

00 00
00 16
01 012
01 118
10 020
10 126
11 032
11 138

Figure 7 shows the various stages of filtering that are employed

in a typical AD73322L application. In Figure 7a we see the trans-

fer function of the external analog antialias filter. Even though it

ADC

Both ADCs consist of an analog sigma-delta modulator and a
digital antialiasing decimation filter. The sigma-delta modu­lator noise-shapes the signal and produces 1-bit samples at a
DMCLK/8 rate. This bitstream, representing the analog input
signal, is input to the antialiasing decimation filter. The decimation
filter reduces the sample rate and increases the resolution.

Analog Sigma-Delta Modulator

The AD73322L’s input channels employ a sigma-delta conversion
technique, which provides a high resolution 16-bit output with
system filtering being implemented on-chip.

Sigma-delta converters employ a technique known as over­sampling, where the sampling rate is many times the highest
frequency of interest. In the case of the AD73322L, the initial
sampling rate of the sigma-delta modulator is DMCLK/8. The
main effect of oversampling is that the quantization noise is
spread over a very wide bandwidth, up to F

/2 = DMCLK/16

S

(Figure 7a). This means that the noise in the band of interest is

is a single RC pole, its cutoff frequency is sufficiently far away

from the initial sampling frequency (DMCLK/8) that it takes

care of any signals that could be aliased by the sampling fre-

quency. This also shows the major difference between the initial

oversampling rate and the bandwidth of interest. In Figure 7b,

the signal and noise-shaping responses of the sigma-delta modu-

lator are shown. The signal response provides further rejection

of any high frequency signals while the noise-shaping will push

the inherent quantization noise to an out-of-band position. The

detail of Figure 7c shows the response of the digital decimation

filter (Sinc-cubed response) with nulls every multiple of DMCLK/

256, which corresponds to the decimation filter update rate

for a 64 kHz sampling. The nulls of the Sinc3 response corre-

spond with multiples of the chosen sampling frequency. The

final detail in Figure 7d shows the application of a final anti-

alias filter in the DSP engine. This has the advantage of being

implemented according to the user’s requirements and available

MIPS. The filtering in Figures 7a through 7c is implemented in

the AD73322L.
much reduced. Another complementary feature of sigma-delta

converters is the use of a technique called noise-shaping. This
technique has the effect of pushing the noise from the band of

BAND

OF

INTEREST

a.

NOISE SHAPING

BAND

OF

INTEREST

b.

DIGITAL FILTER

BAND

OF

INTEREST

c.

Figure 6. Sigma-Delta Noise Reduction

F

/2

S

DMCLK/16

F

/2

S

DMCLK/16

F

/2

S

DMCLK/16

REV. 0

–11–

AD73322L

= DMCLK/8

FB = 4kHz

a. Analog Antialias Filter Transfer Function

SIGNAL TRANSFER FUNCTION

NOISE TRANSFER FUNCTION

FB = 4kHz

b. Analog Sigma-Delta Modulator Transfer Function

F

F

SINIT

SINIT

= DMCLK/8

Word growth in the decimator is determined by the sampling
rate. At 64 kHz sampling, where the oversampling ratio between
sigma-delta modulator and decimator output equals 32, there
are five bits per stage of the three-stage Sinc3 filter. Due to symme­try within the sigma-delta modulator, the LSB will always be a
zero; therefore, the 16-bit ADC output word will have 2 LSBs
equal to zero, one due to the sigma-delta symmetry and the
other being a padding zero to make up the 16-bit word. At
lower sampling rates, decimator word growth will be greater
than the 16-bit sample word, therefore truncation occurs in
transferring the decimator output as the ADC word. For example,
at 8 kHz sampling, word growth reaches 24 bits due to the OSR
of 256 between sigma-delta modulator and decimator output.
This yields eight bits per stage of the three-stage Sinc3 filter.

ADC Coding

The ADC coding scheme is in twos complement format (see
Figure 8). The output words are formed by the decimation
filter, which grows the word length from the single-bit output
of the sigma-delta modulator to a word length of up to 24 bits
(depending on decimation rate chosen), which is the final out­put of the ADC block. In Data Mode this value is truncated to
16 bits for output on the Serial Data Output (SDO) pin.

FB = 4kHz

F

SINTER

= DMCLK/256

c. Digital Decimator Transfer Function

FB = 4kHz

SFINAL

= 8kHz

F

SINTER

= DMCLK/256F

d. Final Filter LPF (HPF) Transfer Function

Figure 7. ADC Frequency Responses

Decimation Filter

The digital filter used in the AD73322L carries out two important
functions. Firstly, it removes the out-of-band quantization
noise, which is shaped by the analog modulator and secondly,
it decimates the high frequency bit stream to a lower rate 16­bit word.

The antialiasing decimation filter is a sinc-cubed digital filter
that reduces the sampling rate from DMCLK/8 to DMCLK/256,
and increases the resolution from a single bit to 15 bits or greater
(depending on chosen sampling rate). Its Z transform is given as:

[(1 – Z

–N

)/(1 – Z –1)]

3

where N is set by the sampling rate (N = 32 @ 64 kHz sam­pling. . . N = 256 @ 8 kHz sampling). Thus when the sampling
rate is 64 kHz, a minimal group delay of 25 µs can be achieved.

V

INN

V

INP

00...00

ADC CODE DIFFERENTIAL

V

INN

V

INP

ADC CODE SINGLE-ENDED

01...11

01...11

ANALOG

INPUT

ANALOG

INPUT

V

+ (V

REF

REF

– (V

+ (V

– (V

 0.32875)

REF

 0.32875)

REF

 0.6575)

REF

 0.6575)

REF

V

REF

10...00

10...00 00...00

REF

V

REF

V

V

Figure 8. ADC Transfer Function

In mixed Control/Data Mode, the resolution is fixed at 15 bits,
with the MSB of the 16-bit transfer being used as a flag bit to
indicate either control or data in the frame.

Decoder Channel

The decoder channels consist of digital interpolators, digital
sigma-delta modulators, single-bit digital-to-analog converters
(DAC), analog smoothing filters and programmable gain ampli­fiers with differential outputs.

DAC Coding

The DAC coding scheme is in twos complement format with
0x7FFF being full-scale positive and 0x8000 being full­scale negative.

–12–

REV. 0