FEATURES
Two 16-Bit A/D Converters
Two 16-Bit D/A Converters
Programmable Input/Output Sample Rates
78 dB ADC SNR
77 dB DAC SNR
64 kS/s Maximum Sample Rate
–90 dB Crosstalk
Low Group Delay (25 s Typ per ADC Channel,
50 s Typ per DAC Channel)
Programmable Input/Output Gain
Flexible Serial Port which Allows Up to Four Dual
Codecs to be Connected in Cascade Giving Eight
I/O Channels
Single (+2.7 V to +5.5 V) Supply Operation
73 mW Typ Power Consumption at 3.0 V
On-Chip Reference
28-Lead SOIC and 44-Lead LQFP Packages
APPLICATIONS
General Purpose Analog I/O
Speech Processing
Cordless and Personal Communications
Telephony
Active Control of Sound and Vibration
Data Communications
Wireless Local Loop
VFBP1
VINP1
VINN1
VFBN1
VOUTP1
VOUTN1
REFOUT
REFCAP
VFBP2
VINP2
VINN2
VFBN2
VOUTP2
VOUTN2
AD73322
FUNCTIONAL BLOCK DIAGRAM
AVDD1 AVDD2
ADC CHANNEL 1
DAC CHANNEL 1
REFERENCE
ADC CHANNEL 2
DAC CHANNEL 2
AGND1 AGND2DGND
DVDD
AD73322
SPORT
SDI
SDIFS
SCLK
SE
RESET
MCLK
SDOFS
SDO
GENERAL DESCRIPTION
The AD73322 is a dual front-end processor for general-purpose
applications including speech and telephony. It features two
16-bit A/D conversion channels and two 16-bit D/A conversion
channels. Each channel provides 77␣ dB signal-to-noise ratio
over a voiceband signal bandwidth. It also features an input-tooutput gain network in both the analog and digital domains.
This is featured on both codecs and can be used for impedance
matching or scaling when interfacing to Subscriber Line Interface Circuits (SLICs).
The AD73322 is particularly suitable for a variety of applications in the speech and telephony area, including low bit rate,
high quality compression, speech enhancement, recognition, and
synthesis. The low group delay characteristic of the part makes
it suitable for single or multichannel active control applications.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
The A/D and D/A conversion channels feature programmable
input/output gains with ranges of 38 dB and 21 dB respectively.
An on-chip reference voltage is included to allow single-supply
operation. This reference is programmable to accommodate
either 3 V or 5 V operation.
The sampling rate of the codecs is programmable with four
separate settings, offering 64 kHz, 32 kHz, 16 kHz and 8 kHz
sampling rates (from a master clock of 16.384 MHz).
A serial port (SPORT) allows easy interfacing of single or cascaded devices to industry standard DSP engines. The SPORT
transfer rate is programmable to allow interfacing to both fast
and slow DSP engines.
The AD73322 is available in 28-lead SOIC and 44-lead LQFP
packages.
Gain Tracking Error±0.1dB1.0 kHz, +3 dBm0 to –50 dBm0
Signal to (Noise + Distortion) at 0 dBm0Refer to Figure 6; AVDD = 3.0 V ± 5%
PGA = 6 dB62.577dB300 Hz to 3400 Hz; f
Total Harmonic Distortion at 0 dBm0AVDD = 3.00 V ± 5%
PGA = 6 dB–80–62.5dB300 Hz to 3400 Hz; f
Intermodulation Distortion–85dBPGA = 0 dB
Idle Channel Noise–85dBm0PGA = 0 dB
CrosstalkDAC-to-ADC–90dBADC Input Signal Level: AGND; DAC
DAC-to-DAC–100dBDAC1 Output Signal Level: AGND; DAC2
Power Supply Rejection–65dBInput Signal Level at AVDD and DVDD
Group Delay
Output DC Offset
Minimum Load Resistance, R
Single-Ended
4, 5
2, 7
4
Differential150Ω
Maximum Load Capacitance, C
Single-Ended500pF
Differential100pF
FREQUENCY RESPONSE
(ADC and DAC)
9
Typical Output
Frequency (Normalized to FS)
00dB
0.03125–0.1dB
0.0625–0.25dB
0.125–0.6dB
0.1875–1.4dB
0.25–2.8dB
0.3125–4.5dB
0.375–7.0dB
0.4375–9.5dB
> 0.5< –12.5dB
2
–2.85dBmMax Output = (1.578/1.2) × VREFCAP
3.17dBmMax Output = 2 × ([1.578/1.2] × VREFCAP)
–6.02dBm
0dBm
= 64 kHz
SAMP
= 64 kHz
SAMP
Output Signal Level: 1.0 kHz, 0 dBm0
Input Amplifiers Bypassed
–77dBInput Amplifiers Included in Input Channel
Output Signal Level: 1.0 kHz, 0 dBm0
Pins: 1.0 kHz, 100 mV p-p Sine Wave
25µsInterpolator Bypassed
50µs
2, 8
L
–25+12+40mV
150Ω
2, 8
L
–3–REV. B
AD73322
AD73322A
ParameterMinTypMaxUnitsTest Conditions/Comments
LOGIC INPUTS
V
, Input High VoltageDVDD – 0.8DVDD V
INH
, Input Low Voltage00.8V
V
INL
I
, Input Current–10+10µA
IH
CIN, Input Capacitance10pF
LOGIC OUTPUT
V
, Output High VoltageDVDD – 0.4DVDD V|IOUT| ≤ 100 µA
OH
, Output Low Voltage00.4V|IOUT| ≤ 100 µA
V
OL
Three-State Leakage Current–10+10µA
POWER SUPPLIES
AVDD1, AVDD22.73.3V
DVDD2.73.3V
10
I
DD
NOTES
1
Operating temperature range is as follows: – 40°C to +85°C. Therefore, T
2
Test conditions: Input PGA set for 0 dB gain, Output PGA set for 6 dB gain, no load on analog outputs (unless otherwise noted).
3
At input to sigma-delta modulator of ADC.
4
Guaranteed by design.
5
Overall group delay will be affected by the sample rate and the external digital filtering.
6
The ADC’s input impedance is inversely proportional to DMCLK and is approximated by: (3.3 × 10
7
Between VOUTP1 and VOUTN1 or between VOUTP2 and VOUTN2.
8
At VOUT output.
9
Frequency responses of ADC and DAC measured with input at audio reference level (the input level that produces an output level of –10 dBm0), with 38 dB preamplifier bypassed and input gain of 0 dB.
10
Test Conditions: no load on digital inputs, analog inputs ac coupled to ground, no load on analog outputs.
Specifications subject to change without notice.
= –40°C and T
MIN
= +85°C.
MAX
See Table I
11
)/DMCLK.
Table I. Current Summary (AVDD = DVDD = +3.3 V)
AnalogDigitalTotal CurrentTotal CurrentMCLK
ConditionsCurrentCurrent(Typ)(Max)SEONComments
ADCs On Only74.511.5131YESREFOUT Disabled
DACs On Only15.54.520231YESREFOUT Disabled
ADCs and DACs On19.5524.5281YESREFOUT Disabled
ADCs and DACs
and Input Amps On25530341YESREFOUT Disabled
ADCs and DACs
and AGT On2452932.51YESREFOUT Disabled
All Sections On32537421YES
REFCAP On Only0.800.81.250NOREFOUT Disabled
REFCAP and
REFOUT On Only3.503.54.50NO
All Sections Off01.51.51.90YESMCLK Active Levels Equal to
0 V and DVDD
All Sections Off0.0010 µA10 µA40 µA0NODigital Inputs Static and Equal
to 0 V or DVDD
The above values are in mA and are typical values unless otherwise noted.
–4–
REV. B
AD73322
SPECIFICATIONS
(AVDD = +5 V ⴞ 10%; DVDD = +5 V ⴞ 10%; DGND = AGND = 0 V, f
Gain Tracking Error±0.1dB1.0 kHz, +3 dBm0 to –50 dBm0
Signal to (Noise + Distortion) at 0 dBm0Refer to Figure 8
PGA = 6 dB77dB300 Hz to 3400 Hz; f
Total Harmonic Distortion at 0 dBm0
PGA = 6 dB–80dB300 Hz to 3400 Hz; f
Intermodulation Distortion–85dBPGA = 0 dB
Idle Channel Noise–85dBm0PGA = 0 dB
CrosstalkDAC-to-ADC–90dBADC Input Signal Level: AGND; DAC
DAC-to-DAC–100dBDAC1 Output Signal Level: AGND; DAC2
Power Supply Rejection–65dBInput Signal Level at AVDD and DVDD
Group Delay
Output DC Offset
4, 5
2, 7
Minimum Load Resistance, R
Single-Ended150Ω
Differential150Ω
Maximum Load Capacitance, C
Single-Ended500pF
Differential100pF
FREQUENCY RESPONSE
(ADC and DAC)
9
Typical Output
Frequency (Normalized to FS)
00dB
0.03125–0.1dB
0.0625–0.25dB
0.125–0.6dB
0.1875–1.4dB
0.25–2.8dB
0.3125–4.5dB
0.375–7.0dB
0.4375–9.5dB
> 0.5< –12.5dB
2
3.17dBmMax Output = (3.156/2.4) × VREFCAP
9.19dBmMax Output = 2 × ([3.156/2.4] × VREFCAP)
0dBm
6.02dBm
= 64 kHz
SAMP
= 64 kHz
SAMP
Output Signal Level: 1.0 kHz, 0 dBm0;
Input Amplifiers Bypassed
–77dBInput Amplifiers Included In Input Channel
Output Signal Level: 1.0 kHz, 0 dBm0
Pins: 1.0 kHz, 100 mV p-p Sine Wave
25µsInterpolator Bypassed
50µs
2, 8
L
2, 8
L
+12mV
–6–
REV. B
AD73322
AD73322A
ParameterMinTypMaxUnitsTest Conditions/Comments
LOGIC INPUTS
, Input High VoltageDVDD – 0.8DVDDV
V
INH
V
, Input Low Voltage00.8V
INL
I
, Input Current±0.5µA
IH
CIN, Input Capacitance10pF
LOGIC OUTPUT
VOH, Output High VoltageDVDD – 0.4DVDDV|I
V
, Output Low Voltage00.4V|I
OL
Three-State Leakage Current±0.3µA
POWER SUPPLIES
AVDD1, AVDD24.55.5V
DVDD4.55.5V
10
I
DD
NOTES
1
Operating temperature range is as follows: –40°C to +85°C. Therefore, T
2
Test conditions: Input PGA set for 0 dB gain, Output PGA set for 6 dB gain, no load on analog outputs (unless otherwise stated).
3
At input to sigma-delta modulator of ADC.
4
Guaranteed by design.
5
Overall group delay will be affected by the sample rate and the external digital filtering.
6
The ADC’s input impedance is inversely proportional to DMCLK and is approximated by: (3.3 × 10
7
Between VOUTP and VOUTN.
8
At VOUT output.
9
Frequency responses of ADC and DAC measured with input at audio reference level (the input level that produces an output level of –10 dBm0), with 38 dB
preamplifier bypassed and input gain of 0 dB.
10
Test conditions: no load on digital inputs, analog inputs ac coupled to ground, no load on analog outputs.
Specifications subject to change without notice.
= –40°C and T
MIN
= +85°C.
MAX
11
)/DMCLK.
| ≤ 100 µA
OUT
| ≤ 100 µA
OUT
See Table II
Table II. Current Summary (AVDD = DVDD = +5.5 V)
AnalogDigitalTotal CurrentMCLK
ConditionsCurrentCurrent(Typ)SEONComments
ADCs On Only7.5916.51YESREFOUT Disabled
DACs On Only169251YESREFOUT Disabled
ADC and DAC On20.51030.51YESREFOUT Disabled
ADCs and DACs
and Input Amps On2710371YESREFOUT Disabled
ADCs and DACs
and AGT On2510351YESREFOUT Disabled
All Sections On3510451YES
REFCAP On Only0.800.80NOREFOUT Disabled
REFCAP and
REFOUT On Only3.503.50NO
All Sections Off0330YESMCLK Active Levels Equal to 0 V and DVDD
All Sections Off010 µA10 µA0NODigital Inputs Static and Equal to 0 V or DVDD
The above values are in mA and are typical values unless otherwise noted.
–7–REV. B
AD73322
Table III. Signal Ranges
3 V Power Supply5 V Power Supply
5VEN = 05VEN = 05VEN = 1
VREFCAP1.2 V ± 10%1.2 V2.4 V
VREFOUT1.2 V ± 10%1.2 V2.4 V
ADCMaximum Input Range
at V
IN
Nominal Reference Level1.0954 V p-p1.0954 V p-p2.1908 V p-p
DACMaximum Voltage
Output Swing
Single-Ended1.578 V p-p1.578 V p-p3.156 V p-p
Differential3.156 V p-p3.156 V p-p6.312 V p-p
Nominal Voltage
Output Swing
Single-Ended1.0954 V p-p1.0954 V p-p2.1908 V p-p
Differential2.1909 V p-p2.1909 V p-p4.3818 V p-p
Output Bias VoltageVREFOUTVREFOUTVREFOUT
1.578 V p-p1.578 V p-p3.156 V p-p
TIMING CHARACTERISTICS
(AVDD = +3 V ⴞ 10%; DVDD = +3 V ⴞ 10%; AGND = DGND = 0 V; TA = T
otherwise noted)
MlN
to T
Limit at
ParameterTA = –40ⴗC to +85ⴗCUnitsDescription
Clock SignalsSee Figure 1
t
1
t
2
t
3
61ns minMCLK Period
24.4ns minMCLK Width High
24.4ns minMCLK Width Low
Serial PortSee Figures 3 and 4
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
Specifications subject to change without notice.
t
1
0.4 × t
0.4 × t
20ns minSDI/SDIFS Setup Before SCLK Low
0ns minSDI/SDIFS Hold After SCLK Low
10ns maxSDOFS Delay from SCLK High
10ns minSDOFS Hold After SCLK High
10ns minSDO Hold After SCLK High
10ns maxSDO Delay from SCLK High
30ns maxSCLK Delay from MCLK
1
1
ns minSCLK Period
ns minSCLK Width High
ns minSCLK Width Low
, unless
MAX
–8–
REV. B
AD73322
t
11
t
7
t
9
t
10
t
7
t
8
t
8
SE (I)
SCLK (O)
SDIFS (I)
SDI (I)
SDOFS (O)
SDO (O)
THREESTATE
THREESTATE
THREESTATE
D15D2D1D0D14
D15D0D1D14D15
D15
t
12
TIMING CHARACTERISTICS
(AVDD = +5 V ⴞ 10%; DVDD = +5 V ⴞ 10%; AGND = DGND = 0 V; TA = T
otherwise noted)
MlN
to T
Limit at
ParameterTA = –40ⴗC to +85ⴗCUnitsDescription
Clock SignalsSee Figure 1
t
1
t
2
t
3
61ns minMCLK Period
24.4ns minMCLK Width High
24.4ns minMCLK Width Low
Serial PortSee Figures 3 and 4
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
1
0.4 × t
1
0.4 × t
1
20ns typSDI/SDIFS Setup Before SCLK Low
0ns typSDI/SDIFS Hold After SCLK Low
10ns typSDOFS Delay from SCLK High
10ns typSDOFS Hold After SCLK High
10ns typSDO Hold After SCLK High
10ns typSDO Delay from SCLK High
30ns typSCLK Delay from MCLK
Specifications subject to change without notice.
t
1
t
2
Figure 1. MCLK Timing
t
3
ns minSCLK Period
ns minSCLK Width High
ns minSCLK Width Low
I
OL
I
OH
TO OUTPUT
PIN
15pF
100mA
C
L
100mA
Figure 2. Load Circuit for Timing Specifications
, unless
MAX
+2.1V
MCLK
SCLK*
t
1
t
13
*SCLK IS INDIVIDUALLY PROGRAMMABLE
IN FREQUENCY (MCLK/4 SHOWN HERE).
t
2
t
5
t
t
4
6
t
3
Figure 3. SCLK Timing
Figure 4. Serial Port (SPORT)
–9–REV. B
AD73322
ABSOLUTE MAXIMUM RATINGS*
(T
= +25°C unless otherwise noted)
A
AVDD, DVDD to GND . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Digital I/O Voltage to DGND . . . . . –0.3 V to DVDD + 0.3 V
Analog I/O Voltage to AGND . . . . . –0.3 V to AVDD + 0.3 V
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
PIN CONFIGURATIONS
28-Lead Wide Body SOIC
(R-28)
ORDERING GUIDE
TemperaturePackagePackage
ModelRangeDescriptionsOptions
AD73322AR–40°C to +85°CWide Body SOIC R-28
AD73322AST–40°C to +85°CPlastic Thin Quad ST-44A
Flatpack (LQFP)
EVAL-AD73322EB Evaluation Board
+EZ-KIT Lite Upgrade
EVAL-AD73322EZ Evaluation Board
+EZ-KIT Lite
NOTES
1
The AD73322 evaluation board features a selectable number of codecs in
1
2
1
3
cascade (from 1 to 4). It can be interfaced to an ADSP-2181 EZ-KIT Lite or to
a Texas Instruments EVM kit.
2
The upgrade consists of a connector that is used to connect the EZ-KIT to the
AD73322 evaluation board. This option is intended for owners of the EZ-KIT
Lite.
3
The EZ-KIT Lite has been modified to allow it to interface with the AD73322
evaluation board. This option is intended for users who do not already have an
EZ-KIT Lite.
44-Lead Plastic Thin Quad Flatpack (LQFP)
(ST-44A)
VINP1
VFBP1
VINN1
VFBN1
REFOUT
REFCAP
AVDD2
AGND2
DGND
DVDD
RESET
SCLK
MCLK
SDO
1
2
3
4
5
6
AD73322
7
TOP VIEW
(Not to Scale)
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VFBN2
VINN2
VFBP2
VINP2
VOUTN1
VOUTP1
VOUTN2
VOUTP2
AVDD1
AGND1
SE
SDI
SDIFS
SDOFS
REFOUT
REFCAP
AVDD2
AVDD2
AGND2
AGND2
AGND2
AGND2
DGND
DGND
DVDD
NC
VFBN1
1
PIN 1
IDENTIFIER
2
3
4
5
6
7
8
9
10
11
121314 15 16 17 18 192021 22
NC
RESET
NC = NO CONNECT
VFBP1
VINN1
AD73322
(Not to Scale)
SCLK
MCLK
VINP1
VFBN2
NC
40 39 384142434436 35 3437
TOP VIEW
NC
SDO
SDOFS
VINN2
SDIFS
VFBP2
SDI
VINP2
SE
NC
NC
33
32
31
30
29
28
27
26
25
24
23
NC
VOUTN1
VOUTP1
NC
VOUTN2
VOUTP2
NC
AVDD1
AVDD1
AGND1
AGND1
–10–
REV. B
AD73322
PIN FUNCTION DESCRIPTIONS
MnemonicFunction
VINP1Analog Input to the inverting input amplifier on Channel 1’s positive input.
VFBP1Feedback Connection from the output of the inverting amplifier on Channel 1’s positive input. When the input
amplifiers are bypassed, this pin allows direct access to the positive input of Channel 1’s sigma-delta modulator.
VINN1Analog Input to the inverting input amplifier on Channel 1’s negative input.
VFBN1Feedback connection from the output of the inverting amplifier on Channel 1’s negative input. When the input
amplifiers are bypassed, this pin allows direct access to the negative input of Channel 1’s sigma-delta modulator.
REFOUTBuffered Reference Output, which has a nominal value of 1.2 V or 2.4 V, the value being dependent on the status
of Bit 5VEN (CRC:7). As the reference is common to the two codec units, the reference value is set by the wired
OR of the CRC:7 bits in Control Register C of each channel.
REFCAPA bypass capacitor to AGND2 of 0.1 µF is required for the on-chip reference. The capacitor should be fixed to this
pin.
AVDD2Analog Power Supply Connection.
AGND2Analog Ground/Substrate Connection2.
DGNDDigital Ground/Substrate Connection.
DVDDDigital Power Supply Connection.
RESETActive Low Reset Signal. This input resets the entire chip, resetting the control registers and clearing the digital
circuitry.
SCLKSerial Clock Output whose rate determines the serial transfer rate to/from the codec. It is used to clock data or
control information to and from the serial port (SPORT). The frequency of SCLK is equal to the frequency of the
master clock (MCLK) divided by an integer number—this integer number being the product of the external mas-
ter clock rate divider and the serial clock rate divider.
MCLKMaster Clock Input. MCLK is driven from an external clock signal.
SDOSerial Data Output. Both data and control information may be output on this pin and are clocked on the positive
edge of SCLK. SDO is in three-state when no information is being transmitted and when SE is low.
SDOFSFraming Signal Output for SDO Serial Transfers. The frame sync is one bit wide and is active one SCLK period
before the first bit (MSB) of each output word. SDOFS is referenced to the positive edge of SCLK. SDOFS is in
three-state when SE is low.
SDIFSFraming Signal Input for SDI Serial Transfers. The frame sync is one bit wide and is valid one SCLK period be-
fore the first bit (MSB) of each input word. SDIFS is sampled on the negative edge of SCLK and is ignored when
SE is low.
SDISerial Data Input. Both data and control information may be input on this pin and are clocked on the negative
edge of SCLK. SDI is ignored when SE is low.
SESPORT Enable. Asynchronous input enable pin for the SPORT. When SE is set low by the DSP, the output pins
of the SPORT are three-stated and the input pins are ignored. SCLK is also disabled internally in order to decrease
power dissipation. When SE is brought high, the control and data registers of the SPORT are at their original
values (before SE was brought low); however, the timing counters and other internal registers are at their reset
values.
AGND1Analog Ground/Substrate Connection.
AVDD1Analog Power Supply Connection.
VOUTP2Analog Output from the Positive Terminal of Output Channel 2.
VOUTN2Analog Output from the Negative Terminal of Output Channel 2.
VOUTP1Analog Output from the Positive Terminal of Output Channel 1.
VOUTN1Analog Output from the Negative Terminal of Output Channel 1.
VINP2Analog Input to the inverting input amplifier on Channel 2’s positive input.
VFBP2Feedback connection from the output of the inverting amplifier on Channel 2’s positive input. When the input
amplifiers are bypassed, this pin allows direct access to the positive input of Channel 2’s sigma-delta modulator.
VINN2Analog Input to the inverting input amplifier on Channel 2’s negative input.
VFBN2Feedback connection from the output of the inverting amplifier on Channel 2’s negative input. When the input
amplifiers are bypassed, this pin allows direct access to the negative input of Channel 2’s sigma-delta modulator.
–11–REV. B
AD73322
TERMINOLOGY
Absolute Gain
Absolute gain is a measure of converter gain for a known signal.
Absolute gain is measured (differentially) with a 1 kHz sine
wave at 0 dBm0 for the DAC and with a 1 kHz sine wave at
0 dBm0 for the ADC. The absolute gain specification is used for
gain tracking error specification.
Crosstalk
Crosstalk is due to coupling of signals from a given channel to
an adjacent channel. It is defined as the ratio of the amplitude of
the coupled signal to the amplitude of the input signal. Crosstalk
is expressed in dB.
Gain Tracking Error
Gain tracking error measures changes in converter output for
different signal levels relative to an absolute signal level. The
absolute signal level is 0 dBm0 (equal to absolute gain) at 1 kHz
for the DAC and 0 dBm0 (equal to absolute gain) at 1 kHz for
the ADC. Gain tracking error at 0 dBm0 (ADC) and 0 dBm0
(DAC) is 0 dB by definition.
Group Delay
Group Delay is defined as the derivative of radian phase with
respect to radian frequency, dø(f)/df. Group delay is a measure
of average delay of a system as a function of frequency. A linear
system with a constant group delay has a linear phase response.
The deviation of group delay from a constant indicates the
degree of nonlinear phase response of the system.
Idle Channel Noise
Idle channel noise is defined as the total signal energy measured
at the output of the device when the input is grounded (measured in the frequency range 300 Hz–3400 Hz).
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m nor n is equal to zero. For final testing, the second
order terms include (fa + fb) and (fa – fb), while the third order
terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).
Power Supply Rejection
Power supply rejection measures the susceptibility of a device to
noise on the power supply. Power supply rejection is measured
by modulating the power supply with a sine wave and measuring
the noise at the output (relative to 0 dB).
Sample Rate
The sample rate is the rate at which the ADC updates its output
register and the DAC updates its output from its input register.
The sample rate can be chosen from a list of four that are fixed
relative to the DMCLK. Sample rate is set by programming bits
DIR0-1 in Control Register B of each channel.
SNR+THD
Signal-to-noise ratio plus total harmonic distortion is defined to
be the ratio of the rms value of the measured input signal to the
rms sum of all other spectral components in the frequency range
300 Hz–3400 Hz, including harmonics but excluding dc.
ABBREVIATIONS
ADCAnalog-to-Digital Converter.
AFEAnalog Front End.
AGTAnalog Gain Tap.
ALBAnalog Loop-Back.
BWBandwidth.
CRxA Control Register where x is a placeholder for an
alphabetic character (A–E). There are five read/
write control registers on the AD73322—designated CRA through CRE.
CRx:nA bit position, where n is a placeholder for a nu-
meric character (0–7), within a control register,
where x is a placeholder for an alphabetic character (A–E). Position 7 represents the MSB and
Position 0 represents the LSB.
DACDigital-to-Analog Converter.
DGTDigital Gain Tap.
DLBDigital Loop-Back.
DMCLKDevice (Internal) Master Clock. This is the inter-
nal master clock resulting from the external master
clock (MCLK) being divided by the on-chip master clock divider.
FSFull Scale.
FSLBFrame Sync Loop-Back—where the SDOFS of
the final device in a cascade is connected to the
RFS and TFS of the DSP and the SDIFS of
first device in the cascade. Data input and output occur simultaneously. In the case of NonFSLB, SDOFS and SDO are connected to the
Rx Port of the DSP while SDIFS and SDI are
connected to the Tx Port.
PGAProgrammable Gain Amplifier.
SCSwitched Capacitor.
SLBSport Loop-Back
SNRSignal-to-Noise Ratio.
SPORTSerial Port.
THDTotal Harmonic Distortion.
VBWVoice Bandwidth.
–12–
REV. B
Typical Performance Characteristics
AD73322
80
70
60
50
40
30
S/(N+D) – dB
20
10
0
–10
–855–75–65 –55–45 –35 –25–15–5
VIN – dBm0
3.17
Figure 5. S/(N+D) vs. VIN (ADC @ 3 V) over Voiceband
Bandwidth (300 Hz–3.4 kHz)
80
70
60
50
40
30
S/(N+D) – dB
20
10
0
–10
–855–75 –65–55 –45–35 –25–15–5
VIN – dBm0
3.17
Figure 6. S/(N+D) vs. VIN (DAC @ 3 V) over Voiceband
Bandwidth (300 Hz–3.4 kHz)
80
70
60
50
40
30
S/(N+D) – dB
20
10
0
–10
–855–75 –65–55 –45–35 –25–15–5
VIN – dBm0
3.17
Figure 7. S/(N+D) vs. VIN (ADC @ 5 V) over Voiceband
Bandwidth (300 Hz–3.4 kHz)
80
70
60
50
40
30
S/(N+D) – dB
20
10
0
–10
–855–75 –65–55 –45–35 –25–15–5
VIN – dBm0
3.17
Figure 8. S/(N+D) vs. VIN (DAC @ 5 V) over Voiceband
Bandwidth (300 Hz–3.4 kHz)
–13–REV. B
Loading...
+ 30 hidden pages
You need points to download manuals.
1 point = 1 manual.
You can buy points or you can get point for every manual you upload.