FEATURES
16-Bit A/D Converter
16-Bit D/A Converter
Programmable Input/Output Sample Rates
76 dB ADC SNR
77 dB DAC SNR
Programmable Sampling Rate
64 kS/s Maximum Sample Rate
–90 dB Crosstalk
Low Group Delay (25 ms Typ per ADC Channel,
50 ms Typ per DAC Channel)
Programmable Input/Output Gain
Flexible Serial Port Which Allows Up to Eight Devices
to Be Connected in Cascade
Single (+3 V) Supply Operation
33 mW Max Power Consumption at 2.7 V
On-Chip Reference
20-Lead SOIC/SSOP/TSSOP Packages
APPLICATIONS
General Purpose Analog I/O
Speech Processing
Cordless and Personal Communications
Telephony
Active Control of Sound and Vibration
Data Communications
General Purpose Analog Front End
AD73311L
GENERAL DESCRIPTION
The AD73311L is a complete front-end processor for general
purpose applications including speech and telephony. It features
a 16-bit A/D conversion channel and a 16-bit D/A conversion
channel. Each channel provides 70 dB signal-to-noise ratio over
a voiceband signal bandwidth. The final channel bandwidth can
be reduced, and signal-to-noise ratio improved, by external
digital filtering in a DSP engine.
The AD73311L is suitable for a variety of applications in the
speech and telephony area, including low bit rate, high quality
compression, speech enhancement, recognition and synthesis.
The low group delay characteristic of the part makes it suitable
for single or multichannel active control applications.
The gains of the A/D and D/A conversion channels are programmable over 38 dB and 21 dB ranges respectively. An on-chip
reference voltage is included to allow single supply operation.
A serial port (SPORT) allows easy interfacing of single or cascaded devices to industry standard DSP engines.
The AD73311L is available in 20-lead SOIC, SSOP and
TSSOP packages.
FUNCTIONAL BLOCK DIAGRAM
AVDD2AVDD1
VINP
VINN
VOUTP
VOUTN
REFCAP
REFOUT
ANALOG
LOOPBACK/
SINGLE-ENDED
ENABLE
+6/–15dB
PGA
0/38dB
PGA
CONTINUOUS
TIME
LOW-PASS FILTER
REFERENCE
AGND1
AGND2
ANALOG
SIGMA-DELTA
MODULATOR
SWITCHED-
CAPACITOR
LOW-PASS FILTER
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
Gain Tracking Error± 0.1dB1.0 kHz, +3 dBm0 to –50 dBm0
Signal to (Noise + Distortion)Refer to Figure 5a
PGA = 0 dB7176dB300 Hz to 3400 Hz
7074dB0 Hz to f
72dB300 Hz to 3400 Hz; f
56dB0 Hz to f
SAMP
SAMP
/2
/2; f
SAMP
SAMP
= 64 kHz
= 64 kHz
PGA = 38 dB60dB300 Hz to 3.4 kHz
59dB0 Hz to f
SAMP
/2
Total Harmonic Distortion
PGA = 0 dB–85–75dB300 Hz to 3.4 kHz
PGA = 38 dB–85dB300 Hz to 3.4 kHz
Intermodulation Distortion–82dBPGA = 0 dB
Idle Channel Noise–76dBm0PGA = 0 dB
Crosstalk–100dBADC Input Signal Level: 1.0 kHz, 0 dBm0
DAC Input at Idle
DC Offset–20+2+25mVPGA = 0 dB
Power Supply Rejection–84dBInput Signal Level at AVDD and DVDD
Group Delay
Input Resistance at VIN
4, 5
2, 4
DAC SPECIFICATIONS
Maximum Voltage Output Swing
25µs64 kHz Output Sample Rate
45kΩ
2
6
Pins 1.0 kHz, 100 mV p-p Sine Wave
DMCLK = 16.384 MHz
Single-Ended1.578V p-pPGA = 6 dB
–2.85dBmMax Output = (1.578/1.2) × V
REFCAP
Differential3.156V p-pPGA = 6 dB
3.17dBmMax Output = 2 × ((1.578/1.2) × V
REFCAP
Nominal Voltage Output Swing (0 dBm0)
Single-Ended1.0954V p-pPGA = 6 dB
–6.02dBm
Differential2.1909V p-pPGA = 6 dB
0dBm
Output Bias Voltage
4
1.081.21.32VREFOUT Unloaded
Absolute Gain–1.8–0.7+0.4dB1.0 kHz, 0 dBm0
Gain Tracking Error± 0.1dB1.0 kHz, +3 dBm0 to –50 dBm0
Signal to (Noise + Distortion)Refer to Figure 5b
PGA = 0 dB7077dB300 Hz to 3.4 kHz Frequency Range
76dB300 Hz to 3400 Hz; f
SAMP
= 64 kHz
PGA = 6 dB77dB300 Hz to 3.4 kHz Frequency Range
77dB300 Hz to 3400 Hz; f
SAMP
= 64 kHz
Total Harmonic Distortion
PGA = 0 dB–80–70dB
PGA = 6 dB–80dB
Intermodulation Distortion–76dBPGA = 0 dB
Idle Channel Noise–82dBm0PGA = 0 dB
Crosstalk–100dBADC Input Signal Level: AGND; DAC
Output Signal Level: 1.0 kHz, 0 dBm0
–2–
REV. A
AD73311L
AD73311LA
ParameterMinTypMaxUnitTest Conditions/Comments
DAC SPECIFICATIONS (Continued)
Power Supply Rejection–81dBInput Signal Level at AVDD and DVDD
Group Delay
Output DC Offset
Minimum Load Resistance, R
4, 5
2, 7
25µs64 kHz Input Sample Rate, Interpolator
2, 8
L
–30+5+50mVPGA = 6 dB
Single-Ended150Ω
Differential150Ω
Maximum Load Capacitance, C
2, 8
L
Single-Ended500pF
Differential100pF
FREQUENCY RESPONSE
(ADC AND DAC)
9
Typical OutputNormalized to f
00dB
0.03125–0.1dB
0.0625–0.25dB
0.125–0.6dB
0.1875–1.4dB
0.25–2.8dB
0.3125–4.5dBChannel Frequency Response Is
0.375–7.0dBProgrammable by Means of External
0.4375–9.5dBDigital Filtering
> 0.5< –12.5dB
LOGIC INPUTS
V
, Input High VoltageVDD – 0.8V
INH
V
, Input Low Voltage00.8V
INL
, Input Current10µA
I
IH
DD
V
CIN, Input Capacitance10pF
LOGIC OUTPUT
, Output High VoltageVDD – 0.4V
V
OH
, Output Low Voltage00.4V|IOUT| ≤ 100 µA
V
OL
DD
V|IOUT| ≤ 100 µA
Three-State Leakage Current–10+10µA
POWER SUPPLIES
AVDD1, AVDD22.73.3V
DVDD2.73.3V
10
I
DD
NOTES
1
Operating temperature range is as follows: –40°C to +105°C. Therefore, T
2
Test conditions: Input PGA set for 0 dB gain, Output PGA set for 6 dB gain, no load on analog outputs (unless otherwise noted).
3
At input to sigma-delta modulator of ADC.
4
Guaranteed by design.
5
Overall group delay will be affected by the sample rate and the external digital filtering.
6
The ADC’s input impedance is inversely proportional to DMCLK and is approximated by: (4 × 1011)/DMCLK.
7
Between VOUTP and VOUTN.
8
At VOUT output.
9
Frequency responses of ADC and DAC measured with input at audio reference level (the input level that produces an output level of –10 dBm0), with 38 dB preamplifier
bypassed and input gain of 0 dB.
10
Test Conditions: no load on digital inputs, analog inputs ac coupled to ground, no load on analog outputs.
Specifications subject to change without notice.
= –40°C and T
MIN
= +105°C.
MAX
Table I. Current Summary (AVDD = DVDD = 3.3 V)
AnalogInternal Digital External InterfaceTotal CurrentMCLK
ConditionsCurrent CurrentCurrent(Max)SEONComments
ADC Only On24.50.58.01YESREFOUT Disabled
ADC and DAC On 5.64.80.512.51YESREFOUT Disabled
REFCAP Only On0.65001.00NOREFOUT Disabled
REFCAP and
REFOUT Only On 2.7003.80NO
All Sections Off00.600.750YESMCLK Active Levels Equal to
All Sections Off1 µA0.5 µA020 µA0NODigital Inputs Static and Equal
The above values are in mA and are typical values unless otherwise noted.
Pins: 1.0 kHz, 100 mV p-p Sine Wave
Bypassed (CRE:5 = 1)
SAMP
See Table I
0 V and DVDD
to 0 V or DVDD
REV. A–3–
AD73311L
(
Table II. Signal Ranges
ParameterConditionSignal Range
V
REFCAP
V
REFOUT
ADCMaximum Input Range at V
IN
Nominal Reference Level1.0954 V p-p
DACMaximum Voltage
Output Swing
Single-Ended1.578 V p-p
Differential3.156 V p-p
Nominal Voltage
Output Swing
Single-Ended1.0954 V p-p
Differential2.1909 V p-p
Output Bias VoltageV
1.2 V ± 10%
1.2 V ± 10%
1.578 V p-p
REFOUT
TIMING CHARACTERISTICS
(AVDD = DVDD = 2.7 V to 3.6 V; AGND = DGND = 0 V; TA = T
MlN
to T
, unless otherwise noted)
MAX
Limit at
ParameterTA = –40ⴗC to +105ⴗCUnitDescription
Clock SignalsSee Figure 1
t
1
t
2
t
3
61ns minMCLK Period
24.4ns minMCLK Width High
24.4ns minMCLK Width Low
Serial PortSee Figures 3 and 4
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
2
t
1
0.4 × t
0.4 × t
1
1
ns minSCLK Period
ns minSCLK Width High
ns minSCLK Width Low
20ns minSDI/SDIFS Setup Before SCLK Low
0ns minSDI/SDIFS Hold After SCLK Low
10ns maxSDOFS Delay from SCLK High
10ns minSDOFS Hold After SCLK High
10ns minSDO Hold After SCLK High
10ns maxSDO Delay from SCLK High
30ns maxSCLK Delay from MCLK
t
1
TO OUTPUT
PIN
t
3
15pF
C
100AI
L
100AI
OL
OH
2.1V
Figure 1. MCLK Timing
MCLK
SCLK
Figure 2. Load Circuit for Timing Specifications
t
1
t
13
*
SCLK IS INDIVIDUALLY PROGRAMMABLE
*
IN FREQUENCY
t
2
t
5
MCLK/4 SHOWN HERE).
t
t
4
t
3
6
Figure 3. SCLK Timing
–4–
REV. A
t
7
t
9
t
10
t
11
t
12
THREE-
STATE
THREE-
STATE
THREE-
STATE
SE (I)
SCLK (O)
SDIFS (I)
SDI (I)
SDOFS (O)
SDO (O)
D15D 14D1
D0
D15
D15D2D1D0
D15D14
t
8
t
7
t
8
Figure 4. Serial Port (SPORT)
AD73311L
80
70
60
50
40
30
S/(N+D) – dB
20
10
0
–10
–85
–75 –65 –55–45 –35–25 –150
VIN – dBm0
–5
3.17
Figure 5a. S/(N+D) vs. VIN (ADC @ 3 V) over Voiceband
Bandwidth (300 Hz – 3.4 kHz)
80
70
60
50
40
30
S/(N+D) – dB
20
10
0
–10
–85
–75 –65 –55–45 –35–25 –150
VIN – dBm0
–5
3.17
Figure 5b. S/(N+D) vs. VIN (DAC @ 3 V) over Voiceband
Bandwidth (300 Hz – 3.4 kHz)
REV. A
–5–
AD73311L
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C unless otherwise noted)
AVDD, DVDD to GND . . . . . . . . . . . . . . . –0.3 V to +4.6 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Digital I/O Voltage to DGND . . . –0.3 V to (DVDD + 0.3 V)
Analog I/O Voltage to AGND . . . –0.3 V to (AVDD + 0.3 V)
Operating Temperature Range
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
PIN CONFIGURATION
VOUTP
VOUTN
AVDD1
AGND1
VINN
REFOUT
REFCAP
AVDD2
AGND2
1
2
3
4
5
AD73311L
TOP VIEW
6
(Not to Scale)
7
8
9
10
20
19
18
17
16
15
14
13
12
11
SE
SDI
SDIFS
SDOFS
SDOVINP
MCLK
SCLK
RESET
DVDD
DGND
ORDERING GUIDE
TemperaturePackage
ModelRangeOption
1
AD73311LAR–40°C to +105°CR-20
AD73311LARS–40°C to +105°CRS-20
AD73311LARU–40°C to +105°CRU-20
EVAL-AD73311LEBEvaluation Board
NOTES
1
R = 0.3' Small Outline IC (SOIC), RS = Shrink Small Outline Package (SSOP),
RU = Thin Small Shrink Outline Package (TSSOP).
2
The AD73311L evaluation board features a cascade of two codecs interfaced to
an ADSP-2185L DSP. The board features a DSP software monitor which
allows interface to a PC serial port.
2
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD73311L features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
–6–
REV. A
AD73311L
PIN FUNCTION DESCRIPTIONS
Pin
NumberMnemonicFunction
1VOUTPAnalog Output from the Positive Terminal of the Output Channel.
2VOUTNAnalog Output from the Negative Terminal of the Output Channel.
3AVDD1Analog Power Supply Connection for the Output Driver.
4AGND1Analog Ground Connection for the Output Driver.
5VINPAnalog Input to the Positive Terminal of the Input Channel.
6VINNAnalog Input to the Negative Terminal of the Input Channel.
7REFOUTBuffered Reference Output, which has a nominal value of 1.2 V.
8REFCAPA Bypass Capacitor to AGND2 of 0.1 µF is required for the on-chip reference. The capacitor should
be fixed to this pin.
9AVDD2Analog Power Supply Connection.
10AGND2Analog Ground/Substrate Connection.
11DGNDDigital Ground/Substrate Connection.
12DVDDDigital Power Supply Connection.
13RESETActive Low Reset Signal. This input resets the entire chip, resetting the control registers and clearing
the digital circuitry.
14SCLKOutput Serial Clock whose rate determines the serial transfer rate to/from the codec. It is used to clock
data or control information to and from the serial port (SPORT). The frequency of SCLK is equal to
the frequency of the master clock (MCLK) divided by an integer number—this integer number being
the product of the external master clock rate divider and the serial clock rate divider.
15MCLKMaster Clock Input. MCLK is driven from an external clock signal.
16SDOSerial Data Output of the Codec. Both data and control information may be output on this pin and are
clocked on the positive edge of SCLK. SDO is in three-state when no information is being transmitted
and when SE is low.
17SDOFSFraming Signal Output for SDO Serial Transfers. The frame sync is on bit wide and is active one
SCLK period before the first bit (MSB) of each output word. SDOFS is referenced to the positive
edge of SCLK. SDOFS is in three-state when SE is low.
18SDIFSFraming Signal Input for SDI Serial Transfers. The frame sync is one bit wide and is valid one
SCLK period before the first bit (MSB) of each input word. SDIFS is sampled on the negative edge of
SCLK and ignored when SE is low.
19SDISerial Data Input of the Codec. Both data and control information may be input on this pin and are
clocked on the negative edge of SCLK. SDI is ignored when SE is low.
20SESPORT Enable. Asynchronous input enable pin for the SPORT. When SE is set low by the DSP, the
output pins of the SPORT are three-stated and the input pins are ignored. SCLK is also disabled
internally in order to decrease power dissipation. When SE is brought high, the control and data regis-
ters of the SPORT are at their original values (before SE was brought low); however, the timing
counters and other internal registers are at their reset values.
REV. A
–7–
AD73311L
TERMINOLOGY
Absolute Gain
Absolute gain is a measure of converter gain for a known signal.
Absolute gain is measured (differentially) with a 1 kHz sine wave
at 0 dBm0 for the DAC and with a 1 kHz sine wave at 0 dBm0
for the ADC. The absolute gain specification is used for gain
tracking error specification.
Crosstalk
Crosstalk is due to coupling of signals from a given channel
to an adjacent channel. It is defined as the ratio of the amplitude of the coupled signal to the amplitude of the input signal.
Crosstalk is expressed in dB.
Gain Tracking Error
Gain tracking error measures changes in converter output for
different signal levels relative to an absolute signal level. The
absolute signal level is 0 dBm0 (equal to absolute gain) at 1 kHz
for the DAC and 0 dBm0 (equal to absolute gain) at 1 kHz for
the ADC. Gain tracking error at 0 dBm0 (ADC) and 0 dBm0
(DAC) is 0 dB by definition.
Group Delay
Group delay is defined as the derivative of radian phase with
respect to radian frequency, dø(f)/df. Group delay is a measure
of average delay of a system as a function of frequency. A linear
system with a constant group delay has a linear phase response.
The deviation of group delay from a constant indicates the degree
of nonlinear phase response of the system.
Idle Channel Noise
Idle channel noise is defined as the total signal energy measured
at the output of the device when the input is grounded (measured
in the frequency range 300 Hz–3400 Hz).
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m nor n are equal to zero. For final testing, the second
order terms include (fa + fb) and (fa – fb), while the third order
terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).
Power Supply Rejection
Power supply rejection measures the susceptibility of a device to
noise on the power supply. Power supply rejection is measured
by modulating the power supply with a sine wave and measuring
the noise at the output (relative to 0 dB).
Sample Rate
The sample rate is the rate at which the ADC updates its output register and the DAC updates its output from its input
register. It is fixed relative to the DMCLK (= DMCLK/256)
and therefore may only be changed by changing the DMCLK.
SNR+THD
Signal-to-noise ratio plus harmonic distortion is defined to be
the ratio of the rms value of the measured input signal to the
rms sum of all other spectral components in the frequency range
300 Hz–3400 Hz, including harmonics but excluding dc.
ABBREVIATIONS
ADCAnalog-to-Digital Converter.
ALBAnalog Loop-Back.
BWBandwidth.
CRxA Control Register where x is a placeholder for an
alphabetic character (A–E). There are five read/
write control registers on the AD73311L—designated CRA through CRE.
CRx:nA bit position, where n is a placeholder for a
numeric character (0–7), within a control register;
where x is a placeholder for an alphabetic character (A–E). Position 7 represents the MSB and
Position 0 represents the LSB.
DACDigital-to-Analog Converter.
DLBDigital Loop-Back.
DMCLKDevice (Internal) Master Clock. This is the
internal master clock resulting from the external
master clock (MCLK) being divided by the on-chip
master clock divider.
FSLBFrame Sync Loop-Back—where the SDOFS of
the final device in a cascade is connected to the
RFS and TFS of the DSP and the SDIFS of first
device in the cascade. Data input and output
occur simultaneously. In the case of nonFSLB,
SDOFS and SDO are connected to the Rx Port
of the DSP while SDIFS and SDI are connected
to the Tx Port.
PGAProgrammable Gain Amplifier.
SCSwitched Capacitor.
SNRSignal-to-Noise Ratio.
SPORTSerial Port.
THDTotal Harmonic Distortion.
VBWVoice Bandwidth.
–8–
REV. A
AD73311L
BAND
OF
INTEREST
NOISE-SHAPING
F
S
/2
DMCLK/16
FUNCTIONAL DESCRIPTION
Encoder Channel
The encoder channel consists of an input configuration block, a
switched capacitor PGA and a sigma-delta analog-to-digital
converter (ADC). An on-board digital filter, which forms part
of the sigma-delta ADC, also performs critical system-level
filtering. Due to the high level of oversampling, the input antialias requirements are reduced such that a simple single pole
RC stage is sufficient to give adequate attenuation in the band
of interest.
Input Configuration Block
The input configuration block consists of a multiplexing arrangement that allows selection of various input configurations. This
includes ADC input selection from either the VINP, VINN pins
or from the DAC output via the Analog Loop-Back (ALB)
arrangement. Differential inputs can be inverted and it is also
possible to use the device in single-ended mode, which allows
the option of using the VINP, VINN pins as two separate
single-ended inputs, either of which can be selected under
software control.
Programmable Gain Amplifier
The encoder section’s analog front end comprises a switched
capacitor PGA that also forms part of the sigma-delta modulator.
The SC sampling frequency is DMCLK/8. The PGA, whose
programmable gain settings are shown in Table III, may be
used to increase the signal level applied to the ADC from low
output sources such as microphones, and can be used to avoid
placing external amplifiers in the circuit. The input signal level
to the sigma-delta modulator should not exceed the maximum
input voltage permitted.
The PGA gain is set by bits IGS0, IGS1 and IGS2 (CRD:0–2)
in Control Register D.
Table III. PGA Settings for the Encoder Channel
sampling rate of the sigma-delta modulator is DMCLK/8. The
main effect of oversampling is that the quantization noise is
spread over a very wide bandwidth, up to F
/2 = DMCLK/16
S
(Figure 6a). This means that the noise in the band of interest is
much reduced. Another complementary feature of sigma-delta
converters is the use of a technique called noise-shaping. This
technique has the effect of pushing the noise from the band of
interest to an out-of-band position (Figure 6b). The combination of these techniques, followed by the application of a
digital filter, reduces the noise in band sufficiently to ensure
good dynamic performance from the part (Figure 6c).
Figure 7 shows the various stages of filtering that are employed
in a typical AD73311L application. In Figure 7a we see the
transfer function of the external analog antialias filter. Even
though it is a single RC pole, its cutoff frequency is sufficiently
far away from the initial sampling frequency (DMCLK/8) that
ADC
The ADC consists of an analog sigma-delta modulator and a
digital antialiasing decimation filter. The sigma-delta modulator noise-shapes the signal and produces 1-bit samples at a
DMCLK/8 rate. This bitstream, representing the analog input
signal, is input to the antialiasing decimation filter. The decimation filter reduces the sample rate and increases the resolution.
Analog Sigma-Delta Modulator
The AD73311L input channel employs a sigma-delta conversion technique, which provides a high resolution 16-bit output
with system filtering being implemented on-chip.
Sigma-delta converters employ a technique known as oversampling, where the sampling rate is many times the highest
frequency of interest. In the case of the AD73311L, the initial
REV. A
it takes care of any signals that could be aliased by the sampling
frequency. This also shows the major difference between the
initial oversampling rate and the bandwidth of interest. In Figure
7b, the signal and noise-shaping responses of the sigma-delta
modulator are shown. The signal response provides further
rejection of any high frequency signals while the noise-shaping
will push the inherent quantization noise to an out-of-band
position. The detail of Figure 7c shows the response of the
digital decimation filter (Sinc-cubed response) with nulls every
multiple of DMCLK/256, which is the decimation filter update
rate. The final detail in Figure 7d shows the application of a
final antialias filter in the DSP engine. This has the advantage
of being implemented according to the user’s requirements and
available MIPS. The filtering in Figures 7a through 7c is implemented in the AD73311L.
–9–
BAND
OF
INTEREST
c.
Figure 6. Sigma-Delta Noise Reduction
F
/2
S
DMCLK/16
AD73311L
FB = 4kHzFS
a. Analog Antialias Filter Transfer Function
= DMCLK/8
INIT
ADC Coding
The ADC coding scheme is in twos complement format (see
Figure 8). The output words are formed by the decimation
filter, which grows the word length from the single-bit output of
the sigma-delta modulator to a 15-bit word, which is the 16-bit
transfer being used as a flag bit to indicate either control or data
in the frame.
V
V
+ (V
REF
ⴛ 0.32875)
REF
INN
SIGNAL TRANSFER FUNCTION
NOISE TRANSFER FUNCTION
FB = 4kHz
FS
INIT
= DMCLK/8
b. Analog Sigma-Delta Modulator Transfer Function
FB = 4kHz FS
= DMCLK/256
INTER
c. Digital Decimator Transfer Function
FB = 4kHz FS
FINAL
= 8kHz
FS
INTER
= DMCLK/256
d. Final Filter LPF (HPF) Transfer Function
Figure 7. AD73311L ADC Frequency Responses
Decimation Filter
The digital filter used in the AD73311L carries out two important functions. Firstly, it removes the out-of-band quantization
noise, which is shaped by the analog modulator and secondly, it
decimates the high frequency bitstream to a lower rate 15-bit word.
The antialiasing decimation filter is a sinc-cubed digital filter
that reduces the sampling rate from DMCLK/8 at the modulator to an output rate at the SPORT of DMCLK/M (where M
depends on the sample rate setting—M = 256 @ 64 kHz; M =
512 @ 32 kHz, M = 1024 @ 16 kHz, M = 2048 @ 8 kHz), and
increases the resolution from a single bit to 15 bits. Its Z transform is given as: [(1–Z–N)/(1–Z–1)]3 where N is determined by
the sampling rate (N = 32 @ 64 kHz, N = 64 @ 32 kHz, N =
128 @ 16 kHz, N = 256 @ 8 kHz). This ensures a minimal
group delay of 25 µs at the 64 kHz sampling rate.
ANALOG
INPUT
ANALOG
INPUT
V
– (V
REF
V
+ (V
REF
V
– (V
REF
ⴛ 0.32875)
REF
REF
ⴛ 0.6575)
REF
V
REF
V
INP
10...0000...0001...11
ADC CODE DIFFERENTIAL
ⴛ 0.6575)
V
INN
V
REF
V
INP
10...0000...0001...11
ADC CODE SINGLE-ENDED
Figure 8. ADC Transfer Function
Decoder Channel
The decoder channel consists of a digital interpolator, digital
sigma-delta modulator, a single bit digital-to-analog converter
(DAC), an analog smoothing filter and a programmable gain
amplifier with differential output.
DAC Coding
The DAC coding scheme is in twos complement format with
0x7FFF being full-scale positive and 0x8000 being full-scale
negative.
Interpolation Filter
The anti-imaging interpolation filter is a sinc-cubed digital filter
which up-samples the 16-bit input words from the SPORT
input rate of DMCLK/M (where M depends on the sample rate
setting—M = 256 @ 64 kHz; M = 512 @ 32 kHz, M = 1024 @
16 kHz, M = 2048 @ 8 kHz), to a rate of DMCLK/8 while
filtering to attenuate images produced by the interpolation process. Its Z transform is given as: [(1–Z
–N
)/(1–Z–1)]3 where N is
determined by the sampling rate (N = 32 @ 64 kHz, N = 64 @
32 kHz, N = 128 @ 16 kHz, N = 256 @ 8 kHz). The DAC
receives 16-bit samples from the host DSP processor at a rate of
DMCLK/M. If the host processor fails to write a new value to
the serial port, the existing (previous) data is read again. The
data stream is filtered by the anti-imaging interpolation filter,
but there is an option to bypass the interpolator for the minimum group delay configuration by setting the IBYP bit (CRE:5) of
Control Register E. The interpolation filter has the same characteristics as the ADC’s antialiasing decimation filter.
–10–
REV. A
AD73311L
The output of the interpolation filter is fed to the DAC’s digital
sigma-delta modulator, which converts the 16-bit data to 1-bit
samples at a rate of DMCLK/8. The modulator noise-shapes
the signal so that errors inherent to the process are minimized
in the passband of the converter. The bitstream output of the
sigma-delta modulator is fed to the single bit DAC where it is
converted to an analog voltage.
Analog Smoothing Filter and PGA
The output of the single-bit DAC is sampled at DMCLK/8,
therefore it is necessary to filter the output to reconstruct the
low frequency signal. The decoder’s analog smoothing filter
consists of a continuous-time filter preceded by a third-order
switched-capacitor filter. The continuous-time filter forms part
of the output programmable gain amplifier (PGA). The PGA
can be used to adjust the output signal level from –15 dB to
+6 dB in 3 dB steps, as shown in Table IV. The PGA gain is
set by bits OGS0, OGS1 and OGS2 (CRD:4-6) in Control
Register D.
The decoder has a differential analog output pair (VOUTP and
VOUTN). The output channel can be muted by setting the
MUTE bit (CRD:7) in Control Register D. The output signal
is dc-biased to the codec’s on-chip voltage reference.
Voltage Reference
The AD73311L reference, REFCAP, is a bandgap reference
that provides a low noise, temperature-compensated reference
to the DAC and ADC. A buffered version of the reference is
also made available on the REFOUT pin and can be used to
bias other external analog circuitry. The reference has a default
nominal value of 1.2 V.
The reference output (REFOUT) can be enabled for biasing
external circuitry by setting the RU bit (CRC:6) of CRC.
Serial Port (SPORT)
The codec communicates with a host processor via the bidirectional synchronous serial port (SPORT) which is compatible
with most modern DSPs. The SPORT is used to transmit and
receive digital data and control information.
In both transmit and receive modes, data is transferred at the
serial clock (SCLK) rate with the MSB being transferred first.
Due to the fact that the SPORT uses a common serial register for
serial input and output, communications between an AD73311L
codec and a host processor (DSP engine) must always be initiated by the codec itself. This ensures that there is no danger of
the information being sent to the codec being corrupted by
ADC samples being output by the codec.
SPORT Overview
The AD73311L SPORT is a flexible, full-duplex, synchronous
serial port whose protocol has been designed to allow up to eight
AD73311L devices to be connected, in cascade, to a single DSP
via a six-wire interface. It has a very flexible architecture that can
be configured by programming two of the internal control registers. The AD73311L SPORT has three distinct modes of operation: Control Mode, Data Mode and Mixed Control/Data Mode.
In Control Mode (CRA:0 = 0), the device’s internal configuration can be programmed by writing to the five internal control
registers. In this mode, control information can be written to or
read from the codec. In Data Mode (CRA:0 = 1), information
that is sent to the device is used to update the decoder section
(DAC), while the encoder section (ADC) data is read from the
device. In this mode, only DAC and ADC data is written to or
read from the device. Mixed mode (CRA:0 = 1 and CRA:1 = 1)
allows the user to choose whether the information being sent to
the device contains either control information or DAC data.
This is achieved by using the MSB of the 16-bit frame as a flag
bit. Mixed mode reduces the resolution to 15 bits with the MSB
being used to indicate whether the information in the 16-bit
frame is control information or DAC/ADC data.
The SPORT features a single 16-bit serial register that is used
for both input and output data transfers. As the input and output data must share the same register there are some precautions
that must be observed. The primary precaution is that no information must be written to the SPORT without reference to an
output sample event, which is when the serial register will be
overwritten with the latest ADC sample word. Once the SPORT
starts to output the latest ADC word then it is safe for the DSP
to write new control or data words to the codec. In certain configurations, data can be written to the device to coincide with
the output sample being shifted out of the serial register—see
section on interfacing devices. The serial clock rate (CRB:2–3)
defines how many 16-bit words can be written to a device before
the next output sample event will happen.
The SPORT block diagram, shown in Figure 9, details the six
control registers (A–F), external MCLK to internal DMCLK
divider and serial clock divider. The divider rates are controlled
by the setting of Control Register B. The AD73311L features a
master clock divider that allows users the flexibility of dividing
externally available high frequency DSP or CPU clocks to generate a lower frequency master clock internally in the codec which
may be more suitable for either serial transfer or sampling rate
requirements. The master clock divider has five divider options
(÷ 1 default condition, ÷ 2, ÷ 3, ÷ 4, ÷ 5) that are set by loading
the master clock divider field in Register B with the appropriate
code. Once the internal device master clock (DMCLK) has
been set using the master clock divider, the sample rate and
serial clock settings are derived from DMCLK.
The SPORT can work at four different serial clock (SCLK) rates:
chosen from DMCLK, DMCLK/2, DMCLK/4 or DMCLK/8,
where DMCLK is the internal or device master clock resulting
from the external or pin master clock being divided by the
master clock divider. When working at the lower SCLK rate of
DMCLK/8, which is intended for interfacing with slower DSPs,
the SPORT will support a maximum of two devices in cascade
with the sample rate of DMCLK/256.
REV. A
–11–
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