Analog Devices AD73311EZ, AD73311EB, AD73311AR, AD73311ARS Datasheet

Low Cost, Low Power CMOS

a

FEATURES
16-Bit A/D Converter
16-Bit D/A Converter
Programmable Input/Output Sample Rates
75 dB ADC SNR
70 dB DAC SNR
64 kS/s Maximum Sample Rate
–90 dB Crosstalk
Low Group Delay (25 ␮s Typ per ADC Channel,

50 ␮s Typ per DAC Channel)
Programmable Input/Output Gain
Flexible Serial Port which Allows up to 8 Devices

to Be Connected in Cascade
Single (+2.7 V to +5.5 V) Supply Operation
50 mW Max Power Consumption at 2.7 V
On-Chip Reference
20-Lead SOIC/SSOP Package

APPLICATIONS
General Purpose Analog I/O
Speech Processing
Cordless and Personal Communications
Telephony
Active Control of Sound & Vibration
Data Communications

General Purpose Analog Front End

AD73311

GENERAL DESCRIPTION

The AD73311 is a complete front-end processor for general
purpose applications including speech and telephony. It features
a 16-bit A/D conversion channel and a 16-bit D/A conversion
channel. Each channel provides 70 dB signal-to-noise ratio over
a voiceband signal bandwidth. The final channel bandwidth can
be reduced, and signal-to-noise ratio improved, by external
digital filtering in a DSP engine.

The AD73311 is suitable for a variety of applications in the
speech and telephony area including low bit rate, high quality
compression, speech enhancement, recognition and synthesis.
The low group delay characteristic of the part makes it suitable
for single or multichannel active control applications.

The gains of the A/D and D/A conversion channels are pro­grammable over 38 dB and 21 dB ranges respectively. An
on-chip reference voltage is included to allow single supply
operation. A serial port (SPORT) allows easy interfacing of
single or cascaded devices to industry standard DSP engines.

The AD73311 is available in both 20-lead SOIC and SSOP
packages.

FUNCTIONAL BLOCK DIAGRAM

AVDD2AVDD1

VINP

VINN

VOUTP

VOUTN

REFCAP

REFOUT

+6/–15dB

PGA

0/38dB

PGA

CONTINUOUS

TIME

LOW-PASS FILTER

REFERENCE

AGND1

AGND2

SWITCHED-

CAPACITOR

LOW-PASS FILTER

ANALOG

SIGMA-DELTA

MODULATOR

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

DVDD

SDI

SDIFS

SCLK

SDO

SDOFS

SE

MCLK

RESET

1-BIT

DAC

DIGITAL

SIGMA-DELTA

MODULATOR

DECIMATOR

INTERPOLATOR

SERIAL

I/O

PORT

AD73311

DGND

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

(AVDD = +3 V ⴞ 10%; DVDD = +3 V ⴞ 10%; DGND = AGND = 0 V, f

AD73311–SPECIFICATIONS

Parameter Min Typ Max Unit Test Conditions/Comments

REFERENCE 5VEN = 0

REFCAP

Absolute Voltage, V
REFCAP TC 50 ppm/°C 0.1 µF Capacitor Required from

REFOUT REFCAP to AGND2

Typical Output Impedance 68 Ω
Absolute Voltage, V
Minimum Load Resistance 1 kΩ
Maximum Load Capacitance 100 pF

ADC SPECIFICATIONS

Maximum Input Range at VIN

Nominal Reference Level at VIN 1.0954 V p-p 5VEN = 0, Measured Differentially

(0 dBm0) –6.02 dBm

Absolute Gain

PGA = 0 dB –0.75 0.1 +1.0 dB 1.0 kHz, 0 dBm0

PGA = 38 dB –1.5 –0.5 +0.5 dB 1.0 kHz, 0 dBm0
Gain Tracking Error ± 0.1 dB 1.0 kHz, +3 dBm0 to –50 dBm0
Signal to (Noise + Distortion) Refer to Figure 5

PGA = 0 dB 70 76 dB 300 Hz to 3.4 kHz Frequency Range

PGA = 38 dB 61 65 dB 300 Hz to 3.4 kHz Frequency Range

Total Harmonic Distortion

PGA = 0 dB –83 –70 dB

PGA = 38 dB –83 –70 dB
Intermodulation Distortion –78 dB PGA = 0 dB
Idle Channel Noise –76 dBm0 PGA = 0 dB
Crosstalk –100 dB ADC Input Signal Level: 1.0 kHz, 0 dBm0

DC Offset –20 +15 +50 mV PGA = 0 dB
Power Supply Rejection –55 dB Input Signal Level at AVDD and DVDD

Group Delay
Input Resistance at VIN

DAC SPECIFICATIONS

Maximum Voltage Output Swing

Single Ended 1.578 V p-p 5VEN = 0, PGA = 6 dB

Differential 3.156 V p-p 5VEN = 0, PGA = 6 dB

Nominal Voltage Output Swing (0 dBm0)

Single-Ended 1.0954 V p-p 5VEN = 0, PGA = 6 dB

Differential 2.1909 V p-p 5VEN = 0, PGA = 6 dB

Output Bias Voltage 1.08 1.2 1.32 V 5VEN = 0, REFOUT Unloaded
Absolute Gain –0.75 +0.2 +1.0 dB 1.0 kHz, 0 dBm0
Gain Tracking Error ± 0.1 dB 1.0 kHz, +3 dBm0 to –50 dBm0
Signal to (Noise + Distortion) AVDD = +3 V ± 5%; Refer to Figure 5

PGA = 0 dB 62.5 70 dB 300 Hz to 3.4 kHz Frequency Range

PGA = 6 dB 62.5 71 dB 300 Hz to 3.4 kHz Frequency Range

Total Harmonic Distortion AVDD = +3 V ± 5%

PGA = 0 dB –70 –62.5 dB

PGA = 6 dB –70 –62.5 dB
Intermodulation Distortion –68 dB PGA = 0 dB
Idle Channel Noise –82 dBm0 PGA = 0 dB
Crosstalk –100 dB ADC Input Signal Level: AGND; DAC

4, 5

REFCAP

REFOUT

2, 3

2, 4

2

1

FS = 64 kHz; TA = T

AD73311A

1.08 1.2 1.32 V

1.08 1.2 1.32 V Unloaded

1.578 V p-p 5VEN = 0, Measured Differentially
–2.85 dBm

55 56 dB 0 Hz to 32 kHz Frequency Range

53 54 dB 0 Hz to 32 kHz Frequency Range

25 µs 64 kHz Output Sample Rate
25 kΩ

–2.85 dBm

3.17 dBm

–6.02 dBm

0 dBm

62.5 dB 0 Hz to 32 kHz Frequency Range

62.5 dB 0 Hz to 32 kHz Frequency Range

MIN

to T

, unless otherwise noted)

MAX

DAC Input at Idle

Pins 1.0 kHz, 100 mV p-p Sine Wave

6

DMCLK = 16.384 MHz

Output Signal Level: 1.0 kHz, 0 dBm0

= 16.384 MHz,

MCLK

–2–

REV. B

AD73311

AD73311A

Parameter Min Typ Max Unit Test Conditions/Comments

DAC SPECIFICATIONS (Continued)

Power Supply Rejection –55 dB Input Signal Level at AVDD and DVDD

Group Delay

Output DC Offset
Minimum Load Resistance, R

4, 5

2, 7

L

2, 8

–30 +20 +70 mV PGA = 6 dB

25 µs 64 kHz Input Sample Rate, Interpolator

Single-Ended 150 Ω
Differential 150 Ω

Maximum Load Capacitance, C

2, 8

L

Single-Ended 500 pF
Differential 100 pF

FREQUENCY RESPONSE

(ADC AND DAC)9 Typical Output

0 Hz 0 dB
2000 Hz –0.1 dB
4000 Hz –0.25 dB
8000 Hz –0.6 dB
12000 Hz –1.4 dB
16000 Hz –2.8 dB
20000 Hz –4.5 dB Channel Frequency Response Is
24000 Hz –7.0 dB Programmable by Means of External
28000 Hz –9.5 dB Digital Filtering
> 32000 Hz < –12.5 dB

LOGIC INPUTS

, Input High Voltage VDD – 0.8 V

V

INH

V

, Input Low Voltage 0 0.8 V

INL

DD

V

IIH, Input Current 10 µA
CIN, Input Capacitance 10 pF

LOGIC OUTPUT

, Output High Voltage VDD – 0.4 V

V

OH

DD

V |IOUT| ≤ 100 µA
VOL, Output Low Voltage 0 0.4 V |IOUT| ≤ 100 µA
Three-State Leakage Current –10 +10 µA

POWER SUPPLIES

AVDD1, AVDD2 2.7 3.3 V
DVDD 2.7 3.3 V

10

I

DD

NOTES

1

Operating temperature range is as follows: –40°C to +85°C. Therefore, T

2

Test conditions: Input PGA set for 0 dB gain, Output PGA set for 6 dB gain, no load on analog outputs (unless otherwise noted).

3

At input to sigma-delta modulator of ADC.

4

Guaranteed by design.

5

Overall group delay will be affected by the sample rate and the external digital filtering.

6

The ADC’s input impedance is inversely proportional to DMCLK and is approximated by: (4 × 1011)/DMCLK.

7

Between VOUTP and VOUTN.

8

At VOUT output.

9

Frequency responses of ADC and DAC measured with input at audio reference level (the input level that produces an output level of –10 dBm0), with 38 dB preamplifier

bypassed and input gain of 0 dB.

10

Test Conditions: no load on digital inputs, analog inputs ac coupled to ground, no load on analog outputs.

Specifications subject to change without notice.

= –40°C and T

MIN

= +85°C.

MAX

Table I. Current Summary (AVDD = DVDD = +3.3 V)

Analog Internal Digital External Interface Total Current MCLK

Conditions Current Current Current (Max) SE ON Comments

ADC On Only 7 3 0.5 11.5 1 YES REFOUT Disabled
ADC and DAC On 10 5 0.5 17.5 1 YES REFOUT Disabled
REFCAP On Only 0.75 0 0 1.2 0 NO REFOUT Disabled
REFCAP and
REFOUT On Only 3.0 0 0 4.5 0 NO
All Sections Off 0 0.85 0 1.2 0 YES MCLK Active Levels Equal to

All Sections Off 0.00 0.007 0 0.04 0 NO Digital Inputs Static and Equal

The above values are in mA and are typical values unless otherwise noted.

Pins: 1.0 kHz, 100 mV p-p Sine Wave

Bypassed (CRE:5 = 1)

See Table I

0 V and DVDD

to 0 V or DVDD

REV. B

–3–

AD73311–SPECIFICATIONS

(AVDD = +5 V ⴞ 10%; DVDD = +5 V ⴞ 10%; DGND = AGND = 0 V, f

1

FS = 64 kHz; TA = T

MIN

to T

, unless otherwise noted)

MAX

= 16.384 MHz,

MCLK

AD73311A

Parameter Min Typ Max Unit Test Conditions/Comments

REFERENCE

REFCAP

Absolute Voltage, V

REFCAP

1.2 V 5VEN = 0

2.4 V 5VEN = 1

REFCAP TC 50 ppm/°C 0.1 µF Capacitor Required from

REFOUT REFCAP to AGND2

Typical Output Impedance 68 Ω
Absolute Voltage, V

REFOUT

1.2 V 5VEN = 0, Unloaded

2.4 V 5VEN = 1, Unloaded
Minimum Load Resistance 2 kΩ 5VEN = 1
Maximum Load Capacitance 100 pF

ADC SPECIFICATIONS

Maximum Input Range at VIN

2, 3

3.156 V p-p 5VEN = 1, Measured Differentially

3.17 dBm

Nominal Reference Level at VIN 2.1908 V p-p 5VEN = 1, Measured Differentially

(0 dBm0) 0 dBm

Absolute Gain

PGA = 0 dB 0.1 dB 1.0 kHz, 0 dBm0
PGA = 38 dB –0.5 dB 1.0 kHz, 0 dBm0

Gain Tracking Error ± 0.1 dB 1.0 kHz, +3 dBm0 to –50 dBm0
Signal to (Noise + Distortion) Refer to Figure 5

PGA = 0 dB 76 dB 300 Hz to 3.4 kHz Frequency Range

59 dB 0 Hz to 32 kHz Frequency Range

PGA = 38 dB 71 dB 300 Hz to 3.4 kHz Frequency Range

57 dB 0 Hz to 32 kHz Frequency Range

Total Harmonic Distortion

PGA = 0 dB –76 dB
PGA = 38 dB –69 dB

Intermodulation Distortion –69 dB PGA = 0 dB
Idle Channel Noise –67 dBm0 PGA = 0 dB
Crosstalk –80 dB ADC Input Signal Level: 1.0 kHz, 0 dBm0

DAC Input at Idle
DC Offset +20 mV PGA = 0 dB
Power Supply Rejection –55 dB Input Signal Level at AVDD and DVDD

Group Delay
Input Resistance at VIN

4, 5

2, 4

DAC SPECIFICATIONS

Maximum Voltage Output Swing

25 µs 64 kHz Output Sample Rate
25 kΩ

2

Pins 1.0 kHz, 100 mV p-p Sine Wave

6

DMCLK = 16.384 MHz

Single Ended 3.156 V p-p 5VEN = 1, PGA = 6 dB

3.17 dBm

Differential 6.312 V p-p 5VEN = 1, PGA = 6 dB

9.19 dBm

Nominal Voltage Output Swing (0 dBm0)

Single-Ended 2.1908 V p-p 5VEN = 1, PGA = 6 dB

0 dBm

Differential 4.3918 V p-p 5VEN = 1, PGA = 6 dB

6.02 dBm

Output Bias Voltage V

REFOUT

V typ 5VEN = 1, REFOUT Unloaded
Absolute Gain ± 0.4 dB 1.0 kHz, 0 dBm0
Gain Tracking Error ± 0.1 dB 1.0 kHz, +3 dBm0 to –50 dBm0
Signal to (Noise + Distortion) Refer to Figure 5

PGA = 0 dB 66 dB 300 Hz to 3.4 kHz Frequency Range

64 dB 0 Hz to 32 kHz Frequency Range

PGA = 6 dB 66 dB 300 Hz to 3.4 kHz Frequency Range

64 dB 0 Hz to 32 kHz Frequency Range

Total Harmonic Distortion

PGA = 0 dB –62.5 dB

PGA = 6 dB –62.5 dB
Intermodulation Distortion –60 dB PGA = 0
Idle Channel Noise –75 dBm0 PGA = 0
Crosstalk –80 dB ADC Input Signal Level: AGND; DAC

Output Signal Level: 1.0 kHz, 0 dBm0

–4–

REV. B

AD73311

AD73311A

Parameter Min Typ Max Unit Test Conditions/Comments

DAC SPECIFICATIONS (Continued)

Power Supply Rejection –55 dB Input Signal Level at AVDD and DVDD

Group Delay

Output DC Offset
Minimum Load Resistance, R

4, 5

2, 7

L

2, 8

25 µs 64 kHz Input Sample Rate, Interpolator

+30 mV PGA = 6 dB

Single-Ended 150 Ω
Differential 150 Ω

Maximum Load Capacitance, C

2, 8

L

Single-Ended 500 pF
Differential 100 pF

FREQUENCY RESPONSE

(ADC AND DAC)9 Typical Output

0 Hz 0 dB
2000 Hz –0.1 dB
4000 Hz –0.25 dB
8000 Hz –0.6 dB
12000 Hz –1.4 dB
16000 Hz –2.8 dB
20000 Hz –4.5 dB Channel Frequency Response Is
24000 Hz –7.0 dB Programmable by Means of External
28000 Hz –9.5 dB Digital Filtering
> 32000 Hz < –12.5 dB

LOGIC INPUTS

V

, Input High Voltage VDD – 0.8 V

INH

, Input Low Voltage 0 0.8 V

V

INL

, Input Current –0.5 µA

I

IH

DD

V

CIN, Input Capacitance 10 pF

LOGIC OUTPUT

V

, Output High Voltage VDD – 0.4 V

OH

, Output Low Voltage 0 0.4 V |I

V

OL

DD

V|I

Three-State Leakage Current –0.3 µA

POWER SUPPLIES

AVDD1, AVDD2 4.5 5.5 V
DVDD 4.5 5.5 V

10

I

DD

N

OTES

1

Operating temperature range is as follows: –40°C to +85°C. Therefore, T

2

Test conditions: Input PGA set for 0 dB gain, Output PGA set for 6 dB gain, no load on analog outputs (unless otherwise stated).

3

At input to sigma-delta modulator of ADC.

4

Guaranteed by design.

5

Overall group delay will be affected by the sample rate and the external digital filtering.

6

The ADC’s input impedance is inversely proportional to DMCLK and is approximated by: (4 × 1011)/DMCLK.

7

Between VOUTP and VOUTN.

8

At VOUT output.

9

Frequency responses of ADC and DAC measured with input at audio reference level (the input level that produces an output level of –10 dBm0), with 38 dB preamplifier

bypassed and input gain of 0 dB.

10

Test conditions: no load on digital inputs, analog inputs ac coupled to ground, no load on analog outputs.

Specifications subject to change without notice.

= –40°C and T

MIN

= +85°C.

MAX

Pins: 1.0 kHz, 100 mV p-p Sine Wave

Bypassed (CRE:5 = 1)

| < 100 µA

OUT

| < 100 µA

OUT

See Table II

REV. B

–5–

AD73311

Table II. Current Summary (AVDD = DVDD = +5.5 V)

Conditions Current Current Current Total Current SE ON Comments

ADC On Only 8.5 6 2 16.5 1 YES REFOUT Disabled
ADC and DAC On 14.5 6 2 22.5 1 YES REFOUT Disabled
REFCAP On Only 0.8 0 0 1.0 0 NO REFOUT Disabled
REFCAP and
REFOUT On Only 3.5 0 0 3.5 0 NO
All Sections Off 0 1.5 0 1.7 0 YES MCLK Active Levels Equal to

All Sections Off 0 0.01 0 0.02 0 NO Digital Inputs Static and

The above values are in mA and are typical values unless otherwise noted.

V

REFCAP

V

REFOUT

ADC Maximum Input Range

DAC Maximum Voltage

Analog Internal Digital External Interface MCLK

0 V and DVDD

Equal to 0 V or DVDD

Table III. Signal Ranges

3 V Power Supply 5 V Power Supply
5VEN = 0 5VEN = 0 5VEN = 1

1.2 V ± 10% 1.2 V 2.4 V

1.2 V ± 10% 1.2 V 2.4 V

at V

IN

1.578 V p-p 1.578 V p-p 3.156 V p-p

Nominal Reference Level 1.0954 V p-p 1.0954 V p-p 2.1908 V p-p

Output Swing
Single-Ended 1.578 V p-p 1.578 V p-p 3.156 V p-p
Differential 3.156 V p-p 3.156 V p-p 6.312 V p-p
Nominal Voltage
Output Swing
Single-Ended 1.0954 V p-p 1.0954 V p-p 2.1908 V p-p
Differential 2.1909 V p-p 2.1909 V p-p 4.3818 V p-p
Output Bias Voltage V

REFOUT

V

REFOUT

V

REFOUT

TIMING CHARACTERISTICS

(AVDD = +3 V ⴞ 10%; DVDD = +3 V ⴞ 10%; AGND = DGND = 0 V; TA = T
otherwise noted)

MlN

to T

Limit at

Parameter TA = –40ⴗC to +85ⴗC Unit Description

Clock Signals See Figure 1

t

1

t

2

t

3

61 ns min MCLK Period

24.4 ns min MCLK Width High

24.4 ns min MCLK Width Low

Serial Port See Figures 3 and 4

t

4

t

5

t

6

t

7

t

8

t

9

t

10

t

11

t

12

t

13

t

1

0.4 × t

0.4 × t

1

1

ns min SCLK Period
ns min SCLK Width High

ns min SCLK Width Low
20 ns min SDI/SDIFS Setup Before SCLK Low
0 ns min SDI/SDIFS Hold After SCLK Low
10 ns max SDOFS Delay from SCLK High
10 ns min SDOFS Hold After SCLK High
10 ns min SDO Hold After SCLK High
10 ns max SDO Delay from SCLK High
30 ns max SCLK Delay from MCLK

MAX

, unless

–6–

REV. B

AD73311

(

TIMING CHARACTERISTICS

(AVDD = +5 V ⴞ 10%; DVDD = +5 V ⴞ 10%; AGND = DGND = 0 V; TA = T
otherwise noted)

MlN

to T

Limit at

Parameter TA = –40ⴗC to +85ⴗC Unit Description

Clock Signals See Figure 1

t

1

t

2

t

3

61 ns min MCLK Period

24.4 ns min MCLK Width High

24.4 ns min MCLK Width Low

Serial Port See Figures 3 and 4

t

4

t

5

t

6

t

7

t

8

t

9

t

10

t

11

t

12

t

13

t

2

t

1

0.4 × t

0.4 × t

1

1

ns min SCLK Period
ns min SCLK Width High

ns min SCLK Width Low
20 ns typ SDI/SDIFS Setup Before SCLK Low
0 ns typ SDI/SDIFS Hold After SCLK Low
10 ns typ SDOFS Delay from SCLK High
10 ns typ SDOFS Hold After SCLK High
10 ns typ SDO Hold After SCLK High
10 ns typ SDO Delay from SCLK High
30 ns typ SCLK Delay from MCLK

t

1

100␮AI

OL

, unless

MAX

t

3

Figure 1. MCLK Timing

MCLK

*

SCLK

Figure 2. Load Circuit for Timing Specifications

t

1

t

13

SCLK IS INDIVIDUALLY PROGRAMMABLE

*

IN FREQUENCY

t

2

t

5

MCLK/4 SHOWN HERE).

t

t

4

6

Figure 3. SCLK Timing

TO OUTPUT

PIN

t

3

15pF

C

L

100␮AI

OH

+2.1V

REV. B

–7–

AD73311

SE (I)

SCLK (O)

SDIFS (I)

SDI (I)

SDOFS (O)

SDO (O)

THREE-

STATE

THREE-

STATE

THREE-

STATE

t

7

t

8

t

8

t

7

D15 D 14 D1 D0

t

9

t

10

t

t

12

11

D15 D2 D1 D0

D15

D15 D14

Figure 4. Serial Port (SPORT)

80

70

60

50

40

30

S/(N+D) – dB

20

10

0

–10

–85

–75 –65 –55 –45 –35 –25 –15 0

VIN – dBm0

–5

3.17

Figure 5a. S/(N+D) vs. VIN (ADC @ 3 V) over Voiceband
Bandwidth (300 Hz – 3.4 kHz)

80

70

60

50

40

30

S/(N+D) – dB

20

10

0

–10

–85

–75 –65 –55 –45 –35 –25 –15 0

VIN – dBm0

–5

3.17

Figure 5b. S/(N+D) vs. VIN (DAC @ 3 V) over Voiceband
Bandwidth (300 Hz – 3.4 kHz)

80

70

60

50

40

30

S/(N+D) – dB

20

10

0

–10

–85

–75 –65 –55 –45 –35 –25 –15 0

VIN – dBm0

–5

3.17

Figure 5c. S/(N+D) vs. VIN (ADC @ 5 V) over Voiceband
Bandwidth (300 Hz – 3.4 kHz)

80

70

60

50

40

30

S/(N+D) – dB

20

10

0

–10

–85

–75 –65 –55 –45 –35 –25 –15 0

VIN – dBm0

–5

3.17

Figure 5d. S/(N+D) vs. VIN (DAC @ 5 V) over Voiceband
Bandwidth (300 Hz – 3.4 kHz)

–8–

REV. B

AD73311

ABSOLUTE MAXIMUM RATINGS*

(TA = +25°C unless otherwise noted)

AVDD, DVDD to GND . . . . . . . . . . . . . . . . . –0.3 V to +7 V

AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

Digital I/O Voltage to DGND . . . . . .–0.3 V to DVDD + 0.3 V

Analog I/O Voltage to AGND . . . . . –0.3 V to AVDD + 0.3 V

Operating Temperature Range

Industrial (A Version) . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Maximum Junction Temperature . . . . . . . . . . . . . . . . +150°C

SOIC, θ

Thermal Impedance . . . . . . . . . . . . . . . . . . 75°C/W

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

SSOP, θ

Thermal Impedance . . . . . . . . . . . . . . . . . . 90°C/W

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

Model Range Option

AD73311AR –40°C to +85°C R-20
AD73311ARS –40°C to +85°C RS-20
EVAL-AD73311EB Evaluation Board

EVAL-AD73311EZ Evaluation Board

NOTES

1

R = 0.3' Small Outline IC (SOIC), RS = Shrink Small Outline Package (SSOP).

2

The AD73311 evaluation board features a selectable number of codecs in
cascade (from 1 to 4). It can be interfaced to an ADSP-2181 EZ-KIT Lite or
to a Texas Instruments EVM kit.

3

The upgrade consists of a replacement PROM and connector. This option is
intended for existing owners of EZ-KIT Lite.

4

The EZ-KIT Lite has been modified to allow it to interface with the AD73311
evaluation board. This option is intended for users who do not already have an
EZ-KIT Lite.

ORDERING GUIDE

Temperature Package

+EZ-KIT Lite Upgrade

+EZ-KIT Lite

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD73311 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

1

2

3

2

4

WARNING!

ESD SENSITIVE DEVICE

PIN CONFIGURATION

VOUTP

VOUTN

AVDD1

AGND1

VINN

REFOUT

REFCAP

AVDD2

AGND2

1

2

3

4

5

AD73311

TOP VIEW

6

(Not to Scale)

7

8

9

10

20

19

18

17

16

15

14

13

12

11

SE

SDI

SDIFS

SDOFS

SDOVINP

MCLK

SCLK

RESET

DVDD

DGND

REV. B

–9–

AD73311

PIN FUNCTION DESCRIPTIONS

Pin
Number Mnemonic Function

1 VOUTP Analog Output from the Positive Terminal of the Output Channel.
2 VOUTN Analog Output from the Negative Terminal of the Output Channel.
3 AVDD1 Analog Power Supply Connection for the Output Driver.
4 AGND1 Analog Ground Connection for the Output Driver.
5 VINP Analog Input to the Positive Terminal of the Input Channel.
6 VINN Analog Input to the Negative Terminal of the Input Channel.
7 REFOUT Buffered Reference Output, which has a nominal value of 1.2 V or 2.4 V, the value being dependent

on the status of Bit 5VEN (CRC:7).

8 REFCAP A Bypass Capacitor to AGND2 of 0.1 µF is required for the on-chip reference. The capacitor should

be fixed to this pin.
9 AVDD2 Analog Power Supply Connection.
10 AGND2 Analog Ground/Substrate Connection.
11 DGND Digital Ground/Substrate Connection.
12 DVDD Digital Power Supply Connection.
13 RESET Active Low Reset Signal. This input resets the entire chip, resetting the control registers and clearing

the digital circuitry.
14 SCLK Output Serial Clock whose rate determines the serial transfer rate to/from the codec. It is used to clock

data or control information to and from the serial port (SPORT). The frequency of SCLK is equal to

the frequency of the master clock (MCLK) divided by an integer number—this integer number being

the product of the external master clock rate divider and the serial clock rate divider.
15 MCLK Master Clock Input. MCLK is driven from an external clock signal.
16 SDO Serial Data Output of the Codec. Both data and control information may be output on this pin and is

clocked on the positive edge of SCLK. SDO is in three-state when no information is being transmitted

and when SE is low.
17 SDOFS Framing Signal Output for SDO Serial Transfers. The frame sync is one-bit wide and it is active one

SCLK period before the first bit (MSB) of each output word. SDOFS is referenced to the positive

edge of SCLK. SDOFS is in three-state when SE is low.
18 SDIFS Framing Signal Input for SDI Serial Transfers. The frame sync is one-bit wide and it is valid one

SCLK period before the first bit (MSB) of each input word. SDIFS is sampled on the negative edge of

SCLK and is ignored when SE is low.
19 SDI Serial Data Input of the Codec. Both data and control information may be input on this pin and are

clocked on the negative edge of SCLK. SDI is ignored when SE is low.
20 SE SPORT Enable. Asynchronous input enable pin for the SPORT. When SE is set low by the DSP, the

output pins of the SPORT are three-stated and the input pins are ignored. SCLK is also disabled

internally in order to decrease power dissipation. When SE is brought high, the control and data regis-

ters of the SPORT are at their original values (before SE was brought low), however the timing

counters and other internal registers are at their reset values.

–10–

REV. B

AD73311

TERMINOLOGY
Absolute Gain

Absolute gain is a measure of converter gain for a known signal.
Absolute gain is measured (differentially) with a 1 kHz sine
wave at 0 dBm0 for the DAC and with a 1 kHz sine wave at
0 dBm0 for the ADC. The absolute gain specification is used for
gain tracking error specification.

Crosstalk

Crosstalk is due to coupling of signals from a given channel
to an adjacent channel. It is defined as the ratio of the amplitude
of the coupled signal to the amplitude of the input signal.
Crosstalk is expressed in dB.

Gain Tracking Error

Gain tracking error measures changes in converter output for
different signal levels relative to an absolute signal level. The
absolute signal level is 0 dBm0 (equal to absolute gain) at 1 kHz
for the DAC and 0 dBm0 (equal to absolute gain) at 1 kHz for
the ADC. Gain tracking error at 0 dBm0 (ADC) and 0 dBm0
(DAC) is 0 dB by definition.

Group Delay

Group Delay is defined as the derivative of radian phase with
respect to radian frequency, dø(f)/df. Group delay is a measure
of average delay of a system as a function of frequency. A linear
system with a constant group delay has a linear phase response.
The deviation of group delay from a constant indicates the
degree of nonlinear phase response of the system.

Idle Channel Noise

Idle channel noise is defined as the total signal energy measured
at the output of the device when the input is grounded (mea­sured in the frequency range 300 Hz–3400 Hz).

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m nor n are equal to zero. For final testing, the second
order terms include (fa + fb) and (fa – fb), while the third order
terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).

Power Supply Rejection

Power supply rejection measures the susceptibility of a device to
noise on the power supply. Power supply rejection is measured
by modulating the power supply with a sine wave and measuring
the noise at the output (relative to 0 dB).

Sample Rate

The sample rate is the rate at which the ADC updates its output
register and the DAC updates its output from its input register.
It is fixed relative to the DMCLK (= DMCLK/256) and there­fore may only be changed by changing the DMCLK.

SNR+THD

Signal-to-noise ratio plus harmonic distortion is defined to be
the ratio of the rms value of the measured input signal to the
rms sum of all other spectral components in the frequency range
300 Hz–3400 Hz, including harmonics but excluding dc.

ABBREVIATIONS

ADC Analog-to-Digital Converter.

ALB Analog Loop-Back.

BW Bandwidth.

CRx A Control Register where x is a placeholder for an

alphabetic character (A–E). There are five read/
write control registers on the AD73311—desig­nated CRA through CRE.

CRx:n A bit position, where n is a placeholder for a nu-

meric character (0–7), within a control register;
where x is a placeholder for an alphabetic charac­ter (A–E). Position 7 represents the MSB and
Position 0 represents the LSB.

DAC Digital-to-Analog Converter.

DLB Digital Loop-Back.

DMCLK Device (Internal) Master Clock. This is the inter-

nal master clock resulting from the external master
clock (MCLK) being divided by the on-chip mas­ter clock divider.

FSLB Frame Sync Loop Back—where the SDOFS of

the final device in a cascade is connected to the
RFS and TFS of the DSP and the SDIFS of
first device in the cascade. Data input and out­put occur simultaneously. In the case of Non­FSLB, SDOFS and SDO are connected to the
Rx Port of the DSP while SDIFS and SDI are
connected to the Tx Port.

PGA Programmable Gain Amplifier.

SC Switched Capacitor.

SNR Signal-to-Noise Ratio.

SPORT Serial Port.

THD Total Harmonic Distortion.

VBW Voice Bandwidth.

REV. B

–11–