Analog Devices AD7328 prl Datasheet
8-Channel, Software Selectable True bipolar
Preliminary Technical Data
FEATURES
• 12-Bit plus Sign SAR ADC
• True Bipolar Input Ranges
• Software Selectable Input Ranges
± 10V, ± 5V, ± 2.5V, 0 to 10V
• 1 MSPS Throughput Rate
• Eight Analog Input Channels with Channel Sequencer
• Single Ended, True Differential and Pseudo Differential
Analog Input Capability
• High Analog Input Impedance
• Low Power:- 12 mW
• Full Power Signal Bandwidth: 7 MHz
• Internal 2.5 V Reference
• High Speed Serial Interface
• Power Down Modes
• 20-Lead TSSOP package
• iCMOS
• For four and two channel equivalent devices see
GENERAL DESCRIPTION
The AD7328 is an 8-Channel, 12-Bit plus Sign Successive
Approximation ADC. The ADC has a high speed serial interface
that can operate at throughput rates up to 1 Msps.
The AD7328 can accept true bipolar Analog Input signals. The
AD7328 has four software selectable inputs Ranges, ±10V, ±5V,
±2.5V and 0 to 10V. Each analog input channel can be
independently programmed to one of the four input ranges.
TM
Process Technology
AD7324 and AD7322 respectively.
Input, 12-Bit Plus Sign ADC
AD7328*
FUNCTIONAL BLOCK DIAGRAM
V
CC
APPROXIMATION
ADC
CONTROL
LOGIC &
REGISTERS
DOUT
SCLK
+5
DIN
V
DRIVE
Vin0
Vin1
Vin2
Vin3
Vin4
Vin5
Vin6
Vin7
I/P
MUX
CHANNEL
SEQUENCER
AGND
V
DD
T/H
V
SS
Figure 1.
2.5V
VREF
REFIN/OUT
13-BIT SUCCESSIVE
DGND
PRODUCT HIGHLIGHTS
1. The AD7328 can accept True Bipolar Analog Input signals,
±10V, ±5V, ±2.5V and 0 to 10V unipolar signals.
2. The Eight Analog Inputs can be configured as 8 Single-Ended
inputs, 4 True Differential, 4 Pseudo Differential or 7 Pseudo
Differential Inputs.
The Analog input channels on the AD7328 can be programmed
to be Single-Ended, true Differential or Pseudo Differential.
The ADC contains a 2.5V Internal reference. The AD7328 also
allows for external Reference operation. If a 3V reference is
applied the REF
±12V Analog Input. V
pin the AD7328 can accept a true Bipolar
IN/OUT
and VSS supplies of ±12V are required
DD
for the ±12V Input Range.
* Protected by U.S. Patent No. 6,731,232
TM
iCMOS
Process Technology
For analog systems designers within industrial/instrumentation equipment OEMs who need high performance ICs at higher-voltage levels, iCMOS is a technology platform
that enables the development of analog ICs capable of 30V and operating at +/- 15V supplies while allowing dramatic reductions in power consumption and package size, and
increased AC and DC performance.
Rev. PrL
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
3. 1 MSPS Serial Interface. SPI/QSPI/DSP/MICROWIRE
compatible Interface.
4. Low Power, 26 mW at maximum throughput rate of 1 MSPS.
5. Channel Sequencer..
Device Number Throughput
Number of bits Number of
Rate
AD7324 1000 ksps 12 bit + Sign 4
AD7322 1000 ksps 12 bit + Sign 2
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
www.analog.com
Channels
Preliminary Technical Data
TABLE OF CONTENTS
AD7328
AD7328—SPECIFICATIONS ............................ 3
ABSOLUTE MAXIMUM RATINGS................. 7
PIN FUNCTIONAL DESCRIPTIONS........................... 8
TERMINOLOGY................................................ 9
THEORY OF OPERATION ....................................... 10
AD7328 REGISTERS........................................ 14
REVISION HISTORY
Revision PrL: Preliminary Version
SEQUENCER OPERATION............................. 18
MODES OF OPERATION ................................ 22
SERIAL INTERFACE.......................................23
OUTLINE DIMENSIONS................................. 24
Rev. PrL | Page 2 of 24
Preliminary Technical Data
AD7328—SPECIFICATIONS
Table 1. Unless otherwise noted, VDD = + 12V to +16.5V, VSS = -12V to –16.5V, VCC = 2.7V to 5.25V, V
2.5V Internal/External, f
= 20 MHz, fS = 1 MSPS TA = T
SCLK
1
= 2.7V to 5.25V, V
DRIVE
to T
MAX
MIN
Parameter Specification Units Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal to Noise Ratio (SNR)
2
76 dB min Differential Mode
F
= 50 kHz Sine Wave
IN
72 dB min Single-Ended/Pesudo Differential Mode
Signal to Noise + Distortion (SINAD)2 75 dB min Differential Mode
71.5 dB min Single-Ended/Pseudo Differential Mode
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise
2
(SFDR)
Intermodulation Distortion (IMD)
2
2
-80 dB max
-80
F
dB max
= 40.1 kHz, Fb = 41.5 kHz
a
Second Order Terms -88 dB typ
Third Order Terms
Aperature Delay
Aperature Jitter
-88 dB typ
10 ns max
50 ps typ
Common Mode Rejection (CMRR) TBD dB typ
Channel-to-Channel Isolation
Full Power Bandwidth
DC ACCURACY
-80 dB typ F
7
1.5
MHz typ
MHz typ
= 400 kHz
IN
@ 3 dB
@ 0.1 dB
Resolution 12 + Sign Bits
Integral Nonlinearity
Differential Nonlinearity
2
2
±1.5 LSB max
± 0.95 LSB max Guaranteed No missing Codes to 13-Bits
Offset Error2 ±8 LSB max Unipolar Range with Straight Binary output coding
Offset Error Match ±0.5 LSB max
Gain Error2 ±6 LSB max
Gain Error Match ±0.6 LSB max
Positive Full-Scale Error
2
±3 LSB max Bipolar Range with Twos Complement Output Coding
Positive Full Scale Error Match ±0.6 LSB max
Bipolar Zero Error2 ±8 LSB max
Bipolar Zero Error Match ±0.5 LSB max
Negative Full Scale Error2 ±4 LSB max
Negative Full Scale Error Match ±0.5 LSB max
ANALOG INPUT
Input Voltage Ranges
(Programmed via Range Register)
±10V
±5V
±2.5V
0 to 10V
Volts VDD = +10V min , VSS = -10V min, VCC = 2.7V to 5.25V
V
= +5V min, VSS = -5V min, VCC = 2.7V to 5.25V
DD
V
= +5V min, VSS = - 5V min, VCC = 2.7V to 5.25V
DD
= +10V min, VSS = AGND min, VCC = 2.7V to 5.25V
V
DD
See Table 5
DC Leakage Current ±10 nA max
Input Capacitance 12 pF typ When in Track, ±10V Range
15 pF typ When in Track, ±5V, 0 to 10V Range
20 pF typ When in Track, ±2.5V Range
3 pF typ When in Hold
REFERENCE INPUT/OUTPUT
Input Voltage Range +2.5 to +3V
V min to
max
Input DC Leakage Current ±1 µA max
Input Capactiance 20 pF typ
Reference Output Voltage 2.49/2.51 Vmin/max
AD7328
=
REF
Rev. PrL | Page 3 of 24
AD328
Preliminary Technical Data
Parameter Specification Units Test Conditions/Comments
Reference Temperature Coefficient 25 ppm/°C max
10 ppm/°C typ
Reference Output Impedance 25
LOGIC INPUTS
Input High Voltage, V
Input Low Voltage, V
2.4 V min
INH
0.8 V max V
INL
Ω typ
0.4 V max V
= 4.75 to 5.25 V
CC
= 2.7 to 3.6 V
CC
Input Current, IIN ± 1 µA max VIN = 0V or VCC
Input Capacitance, C
3
IN
10 pF max
LOGIC OUTPUTS
Output High Voltage, VOH V
Output Low Voltage, VOL 0.4 V max I
- 0.2V V min I
DRIVE
= 200 µA
SOURCE
= 200 µA
SINK
Floating State Leakage Current ±1 µA max
Floating State Output Capacitance
Output Coding
3
10 pF max
Straight
Coding bit set to 1 in Control Register
Natural
Binary
Two’s
Coding bit set to 0 in Control Register
Complement
CONVERSION RATE
Conversion Time 800 ns max 16 SCLK Cycles with SCLK = 20 MHz
Track-and-Hold Acquisition Time 200 ns max Sine Wave Input
200 ns max Full Scale Step input
Throughput Rate 1 MSPS max See Serial Interface section
POWER REQUIREMENTS
4
V
12V/+16.5V V min/max See Table 5
DD
4
V
-12V/16.5V V min/max See Table 5
SS
Digital Inputs = 0V or VCC
VCC 2.7V / 5.25V V min/max See Table 5
V
2.7V/5.25V V min/max
DRIVE
Normal Mode
IDD 300 µA max VDD = +16.5V
ISS 370 µA max VSS = -16.5V
ICC 2 mA max VCC = 5.25V
Auto-Standby Mode F
SAMPLE
= TBD
IDD TBD µA max
ISS TBD µA max
ICC 1.6 mA typ
Auto-Standby Mode F
SAMPLE
= TBD
IDD TBD µA max
ISS TBD µA max
ICC 1 mA typ
Full Shutdown Mode
IDD 0.9 µA max
ISS 0.9 µA max
ICC 0.9 µA max SCLK On or Off
POWER DISSIPATION
Normal Mode 26 mW max V
12 mW typ V
Full Shutdown Mode 35 µW max V
= +16.5V, VSS = -16.5V, V
DD
= +5V, VSS = -5V, V
DD
= +16.5V, VSS = -16.5V, V
DD
CC
CC
= 5V,
CC
= 5.25V,
= 5.25V,
Rev. PrL | Page 4 of 24
Preliminary Technical Data
AD7328
NOTES
1
Temperature ranges as follows: -40°C to +85°C
2
See Terminology
3
Guaranteed by initial Characterization
4
Functional from VDD = +4.75V and VSS = -4.75
Specifications subject to change without notice.
Rev. PrL | Page 5 of 24
Preliminary Technical Data
TIMING SPECIFICATIONS
Table 2. Unless otherwise noted,
2.5V Internal/External, T
Parameter Limit at T
f
SCLK
10 kHz min
20 MHz max
t
CONVERT
t
50 ns max
QUIET
t
1
t
2
t
3
t
4
16×t
10 ns min
10 ns min
20 ns max
TBD ns max Data Access Time after SCLK Falling Edge.
t5 0.4t
t6 0.4t
t
7
t
8
10 ns min SCLK to Data Valid Hold Time
25 ns max SCLK Falling Edge to D
10 ns min SCLK Falling Edge to D
t
9
t
10
TBD ns min DIN set-up time prior to SCLK falling edge
5 ns min DIN hold time after SCLK falling edge
1 µs max Power up from Auto Standby
TBD µs max Power up from Full Shutdown/Auto Shutdown Mode
MIN
ns max T
SCLK
SCLK
ns min SCLK High Pulsewidth
SCLK
VDD = +12V to + 16.5V, VSS = -12 to –16.5V, V
= T
, T
A
to T
MAX
Unit Description
MAX
ns min SCLK Low Pulsewidth
MIN
SCLK
= 1/f
SCLK
Minimum Time between End of Serial Read and Next Falling Edge of
Minimum CS pulse width
CS
to SCLK Setup Time
Delay from CS until D
Three-State Disabled
OUT
High Impedance
OUT
High Impedance
OUT
=2.7V to 5.25, V
CC
=2.7V to 5.25, V
DRIVE
AD7328
REF
CS
=
Rev. PrL | Page 6 of 24
Figure 2. Serial Interface timing Diagram
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Table 3. TA = 25°C, unless otherwise noted
VDD to AGND, DGND -0.3 V to +16.5 V
VSS to AGND, DGND +0.3 V to –16.5 V
VCC to AGND, DGND -0.3V to +7V
V
to VCC -0.3 V to VCC + 0.3V
DRIVE
AGND to DGND -0.3 V to +0.3 V
Analog Input Voltage to AGND
Digital Input Voltage to DGND -0.3 V to +7 V
Digital Output Voltage to GND -0.3 V to V
REFIN to AGND -0.3 V to VCC +0.3V
Input Current to Any Pin Except Supplies
Operating Temperature Range -40°C to +85°C
Storage Temperature Range -65°C to +150°C
Junction Temperature +150°C
TSSOP Package
θJA Thermal Impedance 143 °C/W
θJC Thermal Impedance 45 °C/W
Pb/SN Temperature, Soldering
Reflow (10 s to 30 s) 240(+0/-5)°C
Pb-free Temperature, Soldering
Reflow 260(+0)°C
ESD TBD
-0.5V to +VDD +
V
SS
2
DRIVE
±10mA
0.5V
+0.3V
AD7328
Rev. PrL | Page 7 of 24
Preliminary Technical Data
Pin Functional Descriptions
AD7328
CS
DIN
DGND
AGND
REFIN/OUT
V
SS
VIN0
VIN1
VIN4
VIN5
1
2
AD7328
3
4
5
6
TOP VIEW
7
8
9
10
(Not to
Scale)
SCLK
20
19
DGND
18
DOUT
17
V
DRIVE
16
V
CC
15
V
DD
VIN2
14
VIN3
13
VIN6
12
VIN7
11
Figure 3. AD7328 Pin Configuration TSSOP
Table 4. AD7328 Pin Function Descriptions
Pin Mnemonic Pin Number Description
SCLK 20
Serial Clock. Logic Input. A serial clock input provides the SCLK used for accessing the data
from the AD7328. This clock is also used as the clock source for the conversion process.
D
18
OUT
Serial Data Output. The conversion output data is supplied to this pin as a serial data stream.
The bits are clocked out on the falling edge of the SCLK input and 16 SCLKs are required to
access the data. The data stream consists of three channel identification bits, followed by the
sign bit followed by the 12 bits of conversion data. The data is provided MSB first.
See the Serial Interface section.
CS
1
Chip Select. Active low logic input. This input provides the dual function of initiating
conversions on the AD7328 and frames the serial data transfer.
DIN 2
Data In. Data to be written to the on-chip registers is provided on this input and is clocked into
the register on the falling edge of SCLK. See Register section.
V
17
DRIVE
Logic power supply input. The voltage supplied at this pin determines at what voltage the
interface will operate. This pin should be decoupled to DGND. The voltage at this pin may be
but should never exceed VCC by more than 0.3V.
CC
DGND 3, 19
different to that at V
Digital Ground. Ground reference point for all digital circuitry on the AD7328. The DGND and
AGND voltages ideally should be at the same potential and must not be more than 0.3 V apart
even on a transient basis.
AGND 4
Analog Ground. Ground reference point for all analog circuitry on the AD7328. All analog input
signals and any external reference signal should be referred to this AGND voltage. The AGND
and DGND voltages ideally should be at the same potential and must not be more than 0.3 V
apart, even on a transient basis.
REF
REF
IN/
5
OUT
Reference Input/ Reference Output pin. The on-chip reference is available on this pin for use
external to the AD7328. Alternativley, the internal reference can be disabled and an external
reference applied to this input. On power up this is the default condition. The nominal internal
reference voltage is 2.5 V, which appears at the pin. A 470 nF capacitor should be placed on
the Reference pin. (See Reference Section)
VCC 16
Analog Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for the ADC core on the
AD7328. This supply should be decoupled to AGND.
VDD 15 Positive power supply voltage. This is the positive supply voltage for the Analog Input section.
VSS 6
Negative power supply voltage. This is the negavtive supply voltage for the Analog Input
section.
Vin0-Vin7 7,8,9,10,11,12,13,14
Analog input 0 through Analog Input 7. The analog inputs are multiplexed into the on-chip
track-and-hold. The analog input channel for conversion is selected by programming the
channel address bits, ADD2 through ADD0, in the control register. The inputs can be
configured as 8 Single-Ended Inputs, 4 True Differential Input pairs, 4 Pseudo differential
inputs or 7 pseudo differential inputs. The configuration of the Analog inputs is selected by
programming the Mode bits, Mode1 and Mode0, in the Control Register. The input range on
each input channel is controlled by programming the range registers. Inputs ranges of ±10V,
±5V, ±2.5V and 0 to 10V can be selected on each analog input channel. See Register section.
Rev. PrL | Page 8 of 24
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