ANALOG DEVICES AD7328 Service Manual

8-Channel, Software-Selectable True

V

FEATURES

12-bit plus sign SAR ADC True bipolar input ranges Software-selectable input ranges

±10 V, ±5 V, ±2.5 V, 0 V to +10 V 1 MSPS throughput rate Eight analog input channels with channel sequencer Single-ended, true differential, and pseudo differential

analog input capability High analog input impedance Low power: 21 mW Temperature indicator Full power signal bandwidth: 22 MHz Internal 2.5 V reference High speed serial interface Power-down modes 20-lead TSSOP package

™

process technology

iCMOS

GENERAL DESCRIPTION

The AD73281 is an 8-channel, 12-bit plus sign, successive approximation ADC designed on the iCMOS (industrial CMOS) process. iCMOS is a process combining high voltage silicon with submicron CMOS and complementary bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no previous generation of high voltage parts could achieve. Unlike analog ICs using conventional CMOS processes, iCMOS components can accept bipolar input signals while providing increased performance, dramatically reduced power consumption, and reduced package size.

Bipolar Input, 12-Bit Plus Sign ADC

AD7328

FUNCTIONAL BLOCK DIAGRAM

DD

AD7328

VIN0

VIN1

VIN2

VIN3

VIN4

VIN5

VIN6

VIN7

I/P

MUX

CHANNEL

SEQUENCER

AGND V

T/H

SS

PRODUCT HIGHLIGHTS

1. The AD7328 can accept true bipolar analog input signals,

±10 V, ±5 V, ±2.5 V, and 0 V to +10 V unipolar signals.

2. The eight analog inputs can be configured as eight single-

ended inputs, four true differential input pairs, four pseudo differential inputs, or seven pseudo differential inputs.

3. 1 MSPS serial interface. SPI®-/QSPI™-/DSP-/MICROWIRE™-

compatible interface.

4. Low power, 30 mW, at a maximum throughput rate of

1 MSPS.

REFIN/OUT

2.5V

VREF

TEMPERAT URE

INDICATOR

Figure 1.

CC

13-BIT

SUCCESSIVE

APPROXIMATION

ADC

CONTROL L OGIC AND REGIS TERS

DGND

DOUT

SCLK

CS

DIN

V

DRIVE

04852-001

The AD7328 can accept true bipolar analog input signals. The AD7328 has four software-selectable input ranges, ±10 V, ±5 V, ±2.5 V, and 0 V to +10 V. Each analog input channel can be independently programmed to one of the four input ranges. The analog input channels on the AD7328 can be programmed to be single-ended, true differential, or pseudo differential.

The ADC contains a 2.5 V internal reference. The AD7328 also allows for external reference operation. If a 3 V reference is applied to the REFIN/OUT pin, the AD7328 can accept a true bipolar ±12 V analog input. Minimum ±12 V V

and VSS supplies are

DD

required for the ±12 V input range. The ADC has a high speed serial interface that can operate at throughput rates up to 1 MSPS.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

5. Channel sequencer.

Table 1. Similar Product Selection

Device Number

Throughput Rate

Number of Bits

Number of Channels

AD7329 1000 kSPS 12-bit plus sign 8 AD7327 500 kSPS 12-bit plus sign 8 AD7324 1000 kSPS 12-bit plus sign 4 AD7323 500 kSPS 12-bit plus sign 4 AD7322 1000 kSPS 12-bit plus sign 2 AD7321 500 kSPS 12-bit plus sign 2

1

Protected by U.S. Patent No. 6,731,232.

AD7328

REVISION HISTORY

6/06—Rev. 0 to Rev. A

Changes to Table 1............................................................................ 1

Changes to Specifications................................................................ 3

Added Thermal Hysteresis to Terminology Section.................. 14

Change to Figure 42 ....................................................................... 20

Change to Control Register Section............................................. 23

10/05—Revision 0: Initial Version

AD7328 to ADSP-BF53x........................................................... 32

Application Hints ........................................................................... 33

Layout and Grounding .............................................................. 33

Outline Dimensions ....................................................................... 34

Ordering Guide .......................................................................... 34

Rev. A | Page 2 of 36

AD7328

SPECIFICATIONS

Unless otherwise noted, VDD = 12 V to 16.5 V, VSS = −12 V to −16.5 V, VCC = 4.75 V to 5.25 V, V internal/external, f

= 20 MHz, fS = 1 MSPS, TA = T

SCLK

MAX

to T

. With VCC < 4.75 V, all specifications are typical.

MIN

Table 2.

B Version Parameter

DYNAMIC PERFORMANCE f

Signal-to-Noise Ratio (SNR)

1

Min Typ Max Unit Test Conditions/Comments

= 50 kHz sine wave

2

76 dB Differential mode

IN

72.5 dB Single-ended/pseudo differential mode Signal-to-Noise + Distortion

(SINAD)

2

75 dB Differential mode; ±2.5 V and ±5 V ranges

76 dB Differential mode; 0 V to +10 V and ±10 V ranges 72 dB

Single-ended/pseudo differential mode; ±2.5 V and ±5 V ranges

72.5 dB

Single-ended/pseudo differential mode; 0 V to +10 V and ±10 V ranges

Total Harmonic Distortion (THD)2 −80 dB Differential mode; ±2.5 V and ±5 V ranges

−82 dB Differential mode; 0 V to +10 V and ±10 V ranges

−77 dB

Single-ended/pseudo differential mode; ±2.5 V and ±5 V ranges

−80 dB

Single-ended/pseudo differential mode; 0 V to +10 V and ±10 V ranges

Peak Harmonic or Spurious Noise

2

(SFDR)

−80 dB Differential mode; ±2.5 V and ±5 V ranges

−82 dB Differential mode; 0 V to +10 V and ±10 V ranges

−78 dB

Single-ended/pseudo differential mode; ±2.5 V and ±5 V ranges

−79 dB

Single-ended/pseudo differential mode; 0 V to +10 V and ±10 V ranges

2

Intermodulation Distortion (IMD)

fa = 50 kHz, fb = 30 kHz Second-Order Terms −88 dB Third-Order Terms

Aperture Delay Aperture Jitter Common-Mode Rejection Ratio

(CMRR)

2

Channel-to-Channel Isolation Full Power Bandwidth

3

−90 dB

7 ns

50 ps

−79 dB Up to 100 kHz ripple frequency; see Figure 17

2

−72 dB fIN on unselected channels up to 100 kHz; see Figure 14

22 MHz At 3 dB

5 MHz At 0.1 dB

DC ACCURACY

4

All specifications are typical for 0 V to 10 V mode.

Resolution 13 Bits No Missing Codes

12-bit

Bits Differential mode

plus sign

11-bit

Bits Single-ended/pseudo differential mode

plus sign

Integral Nonlinearity

2

±1.1 LSB Differential mode

±1 LSB Single-ended/pseudo differential mode

−0.7/+1.2 LSB

Single-ended/pseudo differential mode (LSB = FSR/8192)

Differential Nonlinearity

2

−0.9/+1.5 LSB

Differential mode; guaranteed no missing codes to 13 bits

±0.9 LSB

Single-ended mode; guaranteed no missing codes to 12 bits

−0.7/+1 LSB

Single-ended/psuedo differential mode (LSB = FSR/8192)

= 2.7 V to 5.25 V, V

DRIVE

= 2.5 V to 3.0 V

REF

Rev. A | Page 3 of 36

AD7328

B Version Parameter

Offset Error

−7/+10 LSB Differential mode Offset Error Match ±0.5 LSB Differential mode Gain Error ±14 LSB Differential mode Gain Error Match ±0.5 LSB Differential mode Positive Full-Scale Error ±7 LSB Differential mode Positive Full-Scale Error Match ±0.5 LSB Differential mode Bipolar Zero Error ±7.5 LSB Differential mode Bipolar Zero Error Match ±0.5 LSB Differential mode Negative Full-Scale Error ±6 LSB Differential mode

Negative Full-Scale Error Match ±0.5 LSB Differential mode ANALOG INPUT

Input Voltage Ranges Reference = 2.5 V; see Table 6

±5 V VDD = 5 V min, VSS = −5 V min, VCC = 2.7 V to 5.25 V

±2.5 V VDD = 5 V min, VSS = − 5 V min, VCC = 2.7 V to 5.25 V

0 to 10 V VDD = 10 V min, VSS = AGND min, VCC = 2.7 V to 5.25 V

±3.5 V Reference = 2.5 V; range = ±10 V

±6 V Reference = 2.5 V; range = ±5 V

±5 V Reference = 2.5 V; range = ±2.5 V

+3/−5 V Reference = 2.5 V; range = 0 V to +10 V

DC Leakage Current ±200 nA VIN = VDD or V

Input Capacitance

16.5 pF When in track, ±5 V and 0 V to +10 V ranges

21.5 pF When in track, ±2.5 V range 3 pF When in hold, all ranges REFERENCE INPUT/OUTPUT

Input Voltage Range 2.5 3 V

Input DC Leakage Current ±1 μA

Input Capacitance 10 pF

Reference Output Voltage 2.5 V

Long Term Stability 150 ppm For 1000 hours

Output Voltage Hysteresis

Reference Output Voltage Error

Reference Output Voltage

Reference Temperature

6 ppm/°C

Reference Output Impedance 7 Ω

1

2, 5

2, 6

(Programmed via Range

Register)

Pseudo Differential VIN(−)

Input Range

3

@ 25°C

to T

T

MIN

MAX

Coefficient

Min Typ Max Unit Test Conditions/Comments

−4/+9 LSB Single-ended/pseudo differential mode

±0.6 LSB Single-ended/pseudo differential mode

±8 LSB Single-ended/pseudo differential mode

±0.5 LSB Single-ended/pseudo differential mode

±4 LSB Single-ended/pseudo differential mode

2, 6

±0.5 LSB Single-ended/pseudo differential mode

±8.5 LSB Single-ended/pseudo differential mode

±0.5 LSB Single-ended/pseudo differential mode

±4 LSB Single-ended/pseudo differential mode

2, 6

±0.5 LSB Single-ended/pseudo differential mode

±10 V V

= 10 V min, VSS = −10 V min, VCC = 2.7 V to 5.25 V

DD

= 16.5 V, VSS = −16.5 V, VCC = 5 V; see Figure 40 and

V

DD

Figure 41

SS

13.5 pF When in track, ±10 V range

2

50 ppm ±5 mV

±10 mV

25 ppm/°C

Rev. A | Page 4 of 36

AD7328

B Version Parameter

LOGIC INPUTS

Input High Voltage, V Input Low Voltage, V

0.4 V VCC = 2.7 to 3.6 V Input Current, I Input Capacitance, C

LOGIC OUTPUTS

Output High Voltage, V

Output Low Voltage, V Floating-State Leakage Current ±1 μA Floating-State Output

Output Coding Straight natural binary Coding bit set to 1 in control register Twos complement Coding bit set to 0 in control register CONVERSION RATE

Conversion Time 800 ns 16 SCLK cycles with SCLK = 20 MHz

Track-and-Hold Acquisition

Throughput Rate 1 MSPS See the Serial Interface section; VCC = 4.75 V to 5.25 V 770 kSPS VCC < 4.75 V POWER REQUIREMENTS Digital inputs = 0 V or V

V

Normal Mode (Static) 0.9 mA VDD/VSS = ±16.5 V, VCC/V

Normal Mode (Operational) f

Autostandby Mode (Dynamic) f

Autoshutdown Mode (Static) SCLK on or off

Full Shutdown Mode SCLK on or off

POWER DISSIPATION

Normal Mode 30 mW VDD = 16.5 V, VSS = −16.5 V, VCC = 5.25 V

21 mW VDD = 12 V, VSS = −12 V, VCC = 5 V

Full Shutdown Mode 38.25 μW VDD = 16.5 V, VSS = −16.5 V, VCC = 5.25 V

1

Temperature range is −40°C to +85°C.

2

See the Terminology section.

3

Sample tested during initial release to ensure compliance.

4

For dc accuracy specifications, the LSB size for differential mode is FSR/8192. For single-ended mode/pseudo differential mode, the LSB size is FSR/4096, unless otherwise noted.

5

Unipolar 0 V to 10 V range with straight binary output coding.

6

Bipolar range with twos complement output coding.

1

Capacitance

2, 3

Time

DD

SS

CC

DRIVE

I

DD

I

SS

ICC and I

DRIVE

I

DD

I

SS

ICC and I

DRIVE

I

DD

I

SS

ICC and I

DRIVE

I

DD

I

SS

ICC and I

DRIVE

Min Typ Max Unit Test Conditions/Comments

INH

INL

IN

3

IN

OH

2.4 V

0.8 V VCC = 4.75 V to 5.25 V

±1 μA V

= 0 V or V

IN

DRIVE

10 pF

V

DRIVE

V I

−

SOURCE

= 200 μA

0.2

OL

3

0.4 V I

5 pF

= 200 μA

SINK

305 ns Full-scale step input; see the Terminology section

DRIVE

12 16.5 V See Tabl e 6

−12 −16.5 V See Table 6

2.7 5.25 V See Table 6; typical specifications for VCC < 4.75 V

2.7 5.25 V = 5.25 V

DRIVE

= 1 MSPS

SAMPLE

360 μA VDD = 16.5 V 410 μA VSS = −16.5 V

3.2 mA VCC/V

SAMPLE

= 5.25 V

DRIVE

= 250 kSPS 200 μA VDD = 16.5 V 210 μA VSS = −16.5 V

1.3 mA VCC/V

DRIVE

= 5.25 V

1 μA VDD = 16.5 V 1 μA VSS = −16.5 V 1 μA VCC/V

DRIVE

= 5.25 V

1 μA VDD = 16.5 V 1 μA VSS = −16.5 V 1 μA VCC/V

Rev. A | Page 5 of 36

DRIVE

= 5.25 V

AD7328

TIMING SPECIFICATIONS

VDD = 12 V to 16.5 V, VSS = −12 V to −16.5 V, VCC = 2.7 V to 5.25 V, V T

= T

to T

A

MAX

. Timing specifications apply with a 32 pF load, unless otherwise noted.

MIN

Table 3.

Limit at T

MIN

, T

MAX

Description

Parameter VCC < 4.75 V VCC = 4.75 V to 5.25 V Unit V

f

SCLK

50 50 kHz min 14 20 MHz max t

CONVER T

t

QUIET

t

1

2

t

2

16 × t

SCLK

16 × t

SCLK

ns max t 75 60 ns min 12 5 ns min

25 20 ns min

45 35 ns min Unipolar input range (0 V to 10 V) t

3

t

4

t

5

t

6

t

7

t

8

26 14 ns max 57 43 ns max Data access time after SCLK falling edge

0.4 × t

SCLK

0.4 × t

SCLK

ns min SCLK low pulse width

ns min SCLK high pulse width 13 8 ns min SCLK to data valid hold time 40 22 ns max SCLK falling edge to DOUT high impedance

10 9 ns min SCLK falling edge to DOUT high impedance t

9

t

10

t

POWER-UP

1

Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V ) and timed from a voltage level of 1.6 V.

2

When using the 0 V to 10 V unipolar range, running at 1 MSPS throughput rate with t at 20 ns, the mark space ratio needs to be limited to 50:50.

4 4 ns min DIN set-up time prior to SCLK falling edge 2 2 ns min DIN hold time after SCLK falling edge 750 750 ns max Power up from autostandby

500 500 μs max Power up from full shutdown/autoshutdown mode, internal reference

25 25 μs typ Power up from full shutdown/autoshutdown mode, external reference

= 2.7 V to 5.25 V, V

DRIVE

≤ V

DRIVE

CC

= 1/f

SCLK

= 2.5 V to 3.0 V internal/external,

REF

1

Minimum time between end of serial read and next falling edge of Minimum

CS pulse width

CS to SCLK set-up time; bipolar input ranges (±10 V, ±5 V, ±2.5 V)

Delay from

2

CS until DOUT three-state disabled

DRIVE

CS

t

QUIET

1

04852-002

SCLK

DOUT

DIN

CS

THREE-

STATE

t

2

1 2 3 4 5 13 14 15 16

3 IDENTIFICATION BITS

t

3

ADD1

ADD2

WRITE

ADD0 SI GN DB11 DB10 DB2 DB1 DB0

t

9

REG

SEL2

MSB

SEL1

t

6

t

4

CONVERT

t

7

t

10

t

5

LSB

DON’T

CARE

t

8

THREE-STATE

Figure 2. Serial Interface Timing Diagram

Rev. A | Page 6 of 36

AD7328

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted

Table 4.

Parameter Rating

VDD to AGND, DGND −0.3 V to +16.5 V VSS to AGND, DGND +0.3 V to −16.5 V VDD to V

CC

VCC − 0.3 V to +16.5 V VCC to AGND, DGND −0.3 V to +7 V V

to AGND, DGND −0.3 V to +7 V

DRIVE

AGND to DGND −0.3 V to +0.3 V Analog Input Voltage to AGND

1

VSS − 0.3 V to VDD + 0.3 V Digital Input Voltage to DGND −0.3 V to +7 V Digital Output Voltage to GND −0.3 V to V

DRIVE

+ 0.3 V REFIN to AGND −0.3 V to VCC + 0.3 V Input Current to Any Pin

Except Supplies

2

±10 mA

Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C TSSOP Package

θJA Thermal Impedance 143°C/W θJC Thermal Impedance 45°C/W

Pb-Free Temperature, Soldering

Reflow 260(0)°C

ESD 2.5 kV

1

If the analog inputs are driven from alternative VDD and VSS supply circuitry,

Schottky diodes should be placed in series with the AD7328’s VDD and VSS supplies.

2

Transient currents of up to 100 mA do not cause SCR latch-up.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Rev. A | Page 7 of 36

AD7328

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

REFIN/OUT

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1

CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on

the AD7328 and frames the serial data transfer.

2 DIN

Data In. Data to be written to the on-chip registers is provided on this input and is clocked into the register on the falling edge of SCLK (see the

3, 19 DGND

Digital Ground. Ground reference point for all digital circuitry on the AD7328. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis.

4 AGND

Analog Ground. Ground reference point for all analog circuitry on the AD7328. All analog input signals and any external reference signal should be referred to this AGND voltage. The AGND and DGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis.

5 REFIN/OUT

Reference Input/Reference Output. The on-chip reference is available on this pin for use external to the AD7328. The nominal internal reference voltage is 2.5 V, which appears at the pin. A 680 nF capacitor should be placed on the reference pin. Alternatively, the internal reference can be disabled and an external reference applied to this input. On power-up, the external reference mode is the default

condition (see the 6 V 7, 8, 14, 13, 9, 10,

12, 11

SS

0 to VIN7

V

IN

Negative Power Supply Voltage. This is the negative supply voltage for the analog input section.

Analog Input 0 to Analog Input 7. The analog inputs are multiplexed into the on-chip track-and-hold.

The analog input channel for conversion is selected by programming the Channel Address Bit ADD2

through Bit ADD0 in the control register. The inputs can be configured as eight single-ended inputs,

four true differential input pairs, four pseudo differential inputs, or seven pseudo differential inputs.

The configuration of the analog inputs is selected by programming the mode bits, Bit Mode 1 and

Bit Mode 0, in the control register. The input range on each input channel is controlled by program-

ming the range registers. Input ranges of ±10 V, ±5 V, ±2.5 V, and 0 V to +10 V can be selected on each

analog input channel when a +2.5 V reference voltage is used (see the 15 V 16 V

DD

CC

Positive Power Supply Voltage. This is the positive supply voltage for the analog input section.

Analog Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for the ADC core on the AD7328.

This supply should be decoupled to AGND. 17 V

DRIVE

Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface

operates. This pin should be decoupled to DGND. The voltage at this pin may be different to that at V

but it should not exceed V 18 DOUT

Serial Data Output. The conversion output data is supplied to this pin as a serial data stream. The bits

are clocked out on the falling edge of the SCLK input, and 16 SCLKs are required to access the data. The

data stream consists of three channel identification bits, the sign bit, and 12 bits of conversion data.

The data is provided MSB first (see the 20 SCLK

Serial Clock, Logic Input. A serial clock input provides the SCLK used for accessing the data from the

AD7328. This clock is also used as the clock source for the conversion process.

CS

DIN

DGND

AGND

V

IN

V

IN

V

IN

VIN5

SS

0

1

4

1

2

3

4

(Not to Scale)

5

6

7

8

9

10

AD7328

TOP VIEW

20

SCLK

19

DGND

18

DOUT

17

V

16

V

15

V

14

VIN2

13

V

12

V

11

V

Figure 3. TSSOP Pin Configuration

Registers section).

Reference section).

Specifications apply from VCC = 4.75 V to 5.25 V.

by more than 0.3 V.

CC

Serial Interface section).

DRIVE

CC

DD

3

IN

6

IN

7

IN

04852-003

Reference section).

,

CC

Rev. A | Page 8 of 36

AD7328

TYPICAL PERFORMANCE CHARACTERISTICS

SNR (dB)

–20

–40

–60

–80

–100

–120

–140

0

50 100 150 200 250 300 350 400 450

FREQUENCY (kHz)

4096 POINT FFT V

CC=VDRIVE

V

DD,VSS

T

= 25°C

A

INT/EXT 2.5V REFERENCE ±10V RANGE F

= 50kHz

IN

SNR = 77. 30dB SINAD = 76. 85dB THD = –86. 96dB SFDR = –88.22dB

Figure 4. FFT True Differential Mode

= ±15V

=5V

500

04852-004

1.0 VCC=V

0.8

T

= 25°C

A

V

DD,VSS

0.6

0.4

0.2

0

–0.2

INL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

0 8192

512 1536 2560 3584 4608 5632 6656 7680

=5V

DRIVE

= ±15V

1024 2048 3072 4096 512 0 6144 7168

INT/EXT 2.5V REFERENCE ±10V RANGE +INL = + 0.55LSB –INL = –0.68LSB

CODE

Figure 7. Typical INL True Differential Mode

04852-007

SNR (dB)

–20

–40

–60

–80

–100

–120

–140

0

50 100 150 200 250 300 350 400 450

FREQUENCY (kHz)

4096 POINT FFT V

CC=VDRIVE

V

DD,VSS

T

A

INT/EXT 2.5V REFERENCE ±10V RANGE F

IN

SNR = 74. 67dB SINAD = 74.03dB THD = –82. 68dB SFDR = – 85.40dB

= 25°C

= 50kHz

= ±15V

=5V

Figure 5. FFT Single-Ended Mode

1.0

0.8

0.6

0.4

0.2

0

–0.2

DNL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

0 8192

1024 2048 3072 4096 5120 6144 7168

512 1536 2560 3584 4608 5632 6656 7680

VCC=V

DRIVE

T

=25°C

A

V

=±15V

DD,VSS

INT/EXT 2.5V REFERENCE ±10V RANGE +DNL = +0.72LSB –DNL = –0.22LSB

CODE

=5V

Figure 6. Typical DNL True Differential Mode

500

1.0

0.8

0.6

0.4

0.2

0

–0.2

DNL ERROR (LSB)

–0.4

VCC=V

–0.6

T

= 25°C

A

V

–0.8

DD,VSS

04852-005

INT/EXT 2.5V REFERENCE

–1.0

0 8192

512 1536 2560 358 4 4608 5632 6656 7680

=5V

DRIVE

= ±15V

1024 2048 3072 4096 5120 6144 7168

±10V RANGE +DNL = +0.79LSB –DNL = –0.38LSB

CODE

04852-043

Figure 8. Typical DNL Single-Ended Mode

1.0

0.8

0.6

0.4

0.2

0

–0.2

INL ERROR (LSB)

–0.4

–0.6

–0.8

04852-006

–1.0

0 8192

1024 2048 3072 4096 5120 6144 7168

512 1536 2560 358 4 4608 5632 6656 7680

VCC=V

DRIVE

T

= 25°C

A

V

= ±15V

DD,VSS

INT/EXT 2.5V REFERENCE ±10V RANGE +INL = + 0.87LSB –INL = –0.49LSB

CODE

=5V

04852-044

Figure 9. Typical INL Single-Ended Mode

Rev. A | Page 9 of 36

AD7328

–

50

VCC=5V V

–55

–60

–65

–70

–75

THD (dB)

–80

–85

–90

–95

–100

10

Figure 10. THD vs. Analog Input Frequency for Single-Ended (SE) and True

50

–55

–60

–65

–70

–75

THD (dB)

–80

–85

–90

–95

–100

10 1000

= ±12V

DD/VSS

T

= 25°C

A

f

=1MSPS

S

0V TO +10V SE

±10V DIF F

ANALOG INPUT F REQUENCY (kHz)

Differential Mode (Diff) at 5 V V

VCC=3V

= ±12V

V

DD/VSS

= 25°C

T

A

=1MSPS

f

S

0V TO + 10V SE

±10V DIFF

ANALOG INPUT FREQUENCY (kHz)

100

±10V SE

0V TO +10V DIF F

±5V SE

±5V DIFF

±2.5V DIFF

±2.5V SE

1000

CC

±10V SE

±5V SE

±2.5V SE

±5V DIFF

±2.5V DIFF

04852-008

Rev. A | Page 10 of 36

AD7328

–

8k

7k

6k

5k

4k

3k

2k

NUMBER OF OCCURRENCES

1k

023

0

–3

–2–10123

1201

7600

CODE

VCC=5V V

DD/VSS

RANGE = ±10V 10k SAMPLE S T

A

1165

Figure 16. Histogram of Codes, Single-Ended Mode

50

–55

–60

–65

VCC=5V

–70

–75

CMRR (dB)

–80

–85

–90

–95

–100

V

=3V

CC

DIFFERENTIAL MODE

= 50kHz

F

IN

V

DD/VSS

= 1MSPS

f

S

=25°C

T

A

200 400 600 800 1000 1200

0

RIPPLE F REQUENCY (kHz)

Figure 17. CMRR vs. Common-Mode Ripple Frequency

=25°C

11 0

= ±12V

04852-014

04852-055

2.0

1.5

1.0

0.5

0

–0.5

INL ERROR (LSB)

–1.0

–1.5

–2.0

5 7 9 11 13 15 17 19

INL = 1MSPS

±V

INL = 500kSPS

SUPPLY VOLTAGE (V)

DD/VSS

INL = 750kSPS

INL = 1MSPS

INL = 750kSPS

±5V RANGE V

CC=VDRIVE

INTERNAL RE FERENCE SINGLE-E NDED MODE

=5V

04852-050

Figure 19. INL Error vs. Supply Voltage at 500 kSPS, 750 kSPS, and 1 MSPS

50

100mV p-p SINE WAVE ON EACH SUPPLY

–55

NO DECOUPL ING SINGLE-E NDED MODE f

=1MSPS

S

–60

–65

–70

–75

PSRR (dB)

–80

–85

–90

–95

–100

200 400 600 800 1000

0 1200

SUPPLY RIPPLE F REQUENCY (kHz)

VCC=5V

VCC=3V

VDD= 12V

VSS= –12V

04852-054

Figure 20. PSRR vs. Supply Ripple Frequency Without Supply Decoupling

2.0

1.5

1.0

0.5

±V

DD/VSS

DNL = 1MSPS

DNL = 750kSPS

SUPPLY VOLTAGE (V)

0

–0.5

DNL ERROR (LSB)

–1.0

±5V RANGE V

CC=VDRIVE

–1.5

INTERNAL REF ERENCE SINGLE-ENDED MODE

–2.0

5 7 9 11 13 15 17 19

=5V

DNL = 750kSPS

DNL = 500kSPS

DNL = 1MSPS

DNL = 500kS PS

04852-049

50

–55

–60

–65

–70

–75

THD (dB)

–80

–85

–90

–95

10 1000

ANALOG INPUT F REQUENCY (kHz)

100

04852-015

Figure 18. DNL Error vs. Supply Voltage at 500 kSPS, 750 kSPS, and 1 MSPS

Rev. A | Page 11 of 36

ANALOG DEVICES AD7328 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS