ANALOG DEVICES AD7327 Service Manual

500 kSPS, 8-Channel, Software-Selectable,

V

True Bipolar Input, 12-Bit Plus Sign ADC

FEATURES

12-bit plus sign SAR ADC True bipolar input ranges Software-selectable input ranges

±10 V, ±5 V, ±2.5 V, 0 V to +10 V 500 kSPS throughput rate 8 analog input channels with channel sequencer Single-ended, true differential, and pseudo differential

analog input capability High analog input impedance Low power: 18 mW Temperature indicator Full power signal bandwidth: 22 MHz Internal 2.5 V reference High speed serial interface Power-down modes 20-lead TSSOP package iCMOS™ process technology

GENERAL DESCRIPTION

The AD73271 is an 8-channel, 12-bit plus sign successive approximation ADC designed on the iCMOS (industrial CMOS) process. iCMOS is a process combining high voltage silicon with submicron CMOS and complementary bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no previous generation of high voltage parts could achieve. Unlike analog ICs using conventional CMOS processes, iCMOS components can accept bipolar input signals while providing increased performance, dramatically reduced power consumption, and reduced package size.

The AD7327 can accept true bipolar analog input signals. The AD7327 has four software-selectable input ranges: ±10 V, ±5 V, ±2.5 V, and 0 V to +10 V. Each analog input channel can be independently programmed to one of the four input ranges. The analog input channels on the AD7327 can be programmed to be single-ended, true differential, or pseudo differential.

The ADC contains a 2.5 V internal reference. The AD7327 also allows external reference operation. If a 3 V reference is applied to the REFIN/OUT pin, the AD7327 can accept a true bipolar ±12 V analog input. Minimum ±12 V V required for the ±12 V input range. The ADC has a high speed serial interface that can operate at throughput rates up to 500 kSPS.

1

Protected by U.S. Patent No. 6,731,232.

and VSS supplies are

DD

AD7327

FUNCTIONAL BLOCK DIAGRAM

DD

AD7327

0

IN

1

IN

2

IN

3

IN

4

IN

5

IN

6

IN

7

IN

I/P

MUX

CHANNEL

SEQUENCER

AGND V

T/H

SS

PRODUCT HIGHLIGHTS

1. The AD7327 can accept true bipolar analog input signals,

±10 V, ±5 V, ±2.5 V, and 0 V to +10 V unipolar signals.

2. The eight analog inputs can be configured as eight single-

ended inputs, four true differential inputs, four pseudo differential inputs, or seven pseudo differential inputs.

3. 500 kSPS serial interface. SPI®-/QSPI™-/DSP-/MICROWIRE™-

compatible interface.

4. Low power, 18 mW, at a maximum throughput rate of

500 kSPS.

5. Channel sequencer.

Table 1. Similar Devices

Device Number

AD7329 1000 kSPS 12-bit plus sign 8 AD7328 1000 kSPS 12-bit plus sign 8 AD7324 1000 kSPS 12-bit plus sign 4 AD7323 500 kSPS 12-bit plus sign 4 AD7322 1000 kSPS 12-bit plus sign 2 AD7321 500 kSPS 12-bit plus sign 2

Throughput Rate Number of bits

REFIN/OUT

2.5V

VREF

TEMPERATURE

INDICATOR

Figure 1.

CC

13-BIT

SUCCESSIVE

APPROXIMATION

ADC

CONTROL LO GIC AND REGISTERS

DGND

DOUT

SCLK

CS

DIN

V

DRIVE

Number of Channels

5401-001

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD7327

REVISION HISTORY

1/10—Rev. 0 to Rev. A

Change to Features and Product Highlights Sections ................. 1

Changes to Table 2 ............................................................................ 5

Change to Endnote 1 in Table 4 ...................................................... 8

Added Power Supply Configuration Section, Figure 56, and

Table 16 ............................................................................................ 33

1/06—Revision 0: Initial Version

Rev. A | Page 2 of 36

AD7327

SPECIFICATIONS

VDD = 12 V to 16.5 V, VSS = −12 V to −16.5 V, VCC = 2.7 V to 5.25 V, V f

= 10 MHz, fS = 500 kSPS, TA = T

SCLK

MAX

to T

, unless otherwise noted.

MIN

Table 2.

B Version Parameter

1

Min Typ Max Unit Test Conditions/Comments

DYNAMIC PERFORMANCE F

2

Signal-to-Noise Ratio (SNR)

76 dB Differential mode, VCC = 4.75 V to 5.25 V

75.5 dB Differential mode, VCC < 4.75 V

72.5 dB

72 dB

Signal-to-Noise + Distortion

(SINAD)

2

75 dB Differential mode; ±2.5 V and ±5 V ranges

74 Differential mode; 0 V to 10 V

76 dB Differential mode; ±10 V range

72 dB

72.5 dB

Total Harmonic Distortion

(THD)

2

−80 dB Differential mode; ±2.5 V and ±5 V ranges

−79 dB Differential mode; 0 V to 10 V ranges

−82 dB Differential mode; ±10 V range

−77 dB Single-ended/pseudo differential mode; ±5 V range

−79 dB Single-ended/pseudo differential mode; ±2.5 V range

−80 dB

Peak Harmonic or Spurious

Noise (SFDR)

2

−81 dB Differential mode; ±2.5 V and ±5 V ranges

−80 dB Differential mode; 0 V to 10 V ranges

−82 dB Differential mode; ±10 V ranges

−78 dB Single-ended/pseudo differential mode; ±5 V range

−80 Single-ended/pseudo differential mode; ±2.5 V range

−79 dB

Intermodulation Distortion

2

(IMD)

fa = 50 kHz, fb = 30 kHz

Second-Order Terms −88 dB

Third-Order Terms

Aperture Delay

Aperture Jitter

Common-Mode Rejection

(CMRR)

2

Channel-to-Channel Isolation

Full Power Bandwidth

3

−90 dB 7 ns 50 ps

2

−72 dB FIN on unselected channels up to 100 kHz; see Figure 14 22 MHz At 3 dB

5 MHz At 0.1 dB

= 2.7 V to 5.25 V, V

DRIVE

= 2.5 V to 3.0 V internal/external,

REF

= 50 kHz sine wave

IN

Single-ended/pseudo differential mode; ±10 V, ±2.5 V and ±5 V ranges, V

= 4.75 V to 5.25 V

CC

Single-ended/pseudo differential mode ; 0 V to 10 V

= 4.75 V to 5.25 V and all ranges at VCC < 4.75 V

V

CC

Single-ended/pseudo differential mode; ±2.5 V and ±5 V ranges

Single-ended/pseudo differential mode; 0 V to +10 V and ±10 V ranges

−79 dB Up to 100 kHz ripple frequency; see Figure 17

Rev. A | Page 3 of 36

AD7327

B Version Parameter

DC ACCURACY

Resolution 13 Bits No Missing Codes

Integral Nonlinearity

−0.7/+1.2 LSB

Differential Nonlinearity

±0.9 LSB

−0.7/+1 LSB

Offset Error

−7/+10 LSB Differential mode Offset Error Match ±0.5 LSB Differential mode Gain Error ±14 LSB Differential mode Gain Error Match ±0.5 LSB Differential mode Positive Full-Scale Error ±7 LSB Differential mode Positive Full-Scale Error Match ±0.5 LSB Differential mode Bipolar Zero Error ±7.5 LSB Differential mode Bipolar Zero Error Match ±0.5 LSB Differential mode Negative Full-Scale Error ±6 LSB Differential mode

Negative Full-Scale Error Match ±0.5 LSB Differential mode ANALOG INPUT

Input Voltage Ranges Reference = 2.5 V; see Tabl e 6

±5 V VDD = +5 V min, VSS = −5 V min, VCC = +2.7 V to +5.25 V

±2.5 V VDD = +5 V min, VSS = −5 V min, VCC = +2.7 V to +5.25 V

0 to 10 V VDD = +10 V min, VSS = AGND min, VCC = +2.7 V to +5.25 V

±3.5 V Reference = 2.5 V; range = ±10 V

±6 V Reference = 2.5 V; range = ±5 V

±5 V Reference = 2.5 V; range = ±2.5 V

+3/−5 V Reference = 2.5 V; range = 0 V to +10 V

1

4

2

−0.9/+1.2 LSB

2, 5

−4/+9 LSB Single-ended/pseudo differential mode

2, 5

±0.6 LSB Single-ended/pseudo differential mode

2, 5

±8 LSB Single-ended/pseudo differential mode

2, 5

±0.5 LSB Single-ended/pseudo differential mode

2, 6

±4 LSB Single-ended/pseudo differential mode

2, 6

±8.5 LSB Single-ended/pseudo differential mode

2, 6

(Programmed via Range

Registers)

Pseudo Differential VIN(−)

Input Range

Min Typ Max Unit Test Conditions/Comments

Single-ended/pseudo differential mode 1 LSB = FSR/4096, unless otherwise noted. Differential mode 1 LSB = FSR/8192, unless otherwise noted.

12-bit

Bits Differential mode plus sign (13 bits)

11-bit

Bits Single-ended/pseudo differential mode plus sign (12 bits)

±1.1 LSB Differential mode; VCC = 3 V to 5.25 V, typ for VCC = 2.7 V ±1 LSB

Single-ended/pseudo differential mode, V

5.25 V, typ for V

= 2.7 V

CC

Single-ended/pseudo differential mode (LSB = FSR/8192)

Differential mode; guaranteed no missing codes to 13 bits

Single-ended mode; guaranteed no missing codes to 12 bits

Single-ended/pseudo differential mode (LSB = FSR/8192)

2, 6

±0.5 LSB Single-ended/pseudo differential mode

±4 LSB Single-ended/pseudo differential mode

2, 6

±0.5 LSB Single-ended/pseudo differential mode

±10 V V

Rev. A | Page 4 of 36

= +10 V min, VSS = −10 V min, VCC = +2.7 V to +5.25 V

DD

VDD = +16.5 V, VSS = −16.5 V, VCC = +5 V; see Figure 40 and Figure 41

= 3 V to

CC

AD7327

B Version Parameter

DC Leakage Current ±80 nA VIN = VDD or VSS 3 nA Per input channel, VIN = VDD or VSS

Input Capacitance

16.5 pF When in track, ±5 V and 0 V to +10 V ranges

21.5 pF When in track, ±2.5 V range 3 pF When in hold, all ranges REFERENCE INPUT/OUTPUT

Input Voltage Range 2.5 3 V Input DC Leakage Current ±1 μA Input Capacitance 10 pF Reference Output Voltage 2.5 V Reference Output Voltage Error

Reference Output Voltage

Reference Temperature

3 ppm/°C Reference Output Impedance 7 Ω

LOGIC INPUTS

Input High Voltage, V Input Low Voltage, V

0.4 V VCC = 2.7 to 3.6 V Input Current, IIN ±1 μA VIN = 0 V or V Input Capacitance, C

LOGIC OUTPUTS

Output High Voltage, VOH

Output Low Voltage, VOL 0.4 V I Floating-State Leakage Current ±1 μA Floating-State Output

Output Coding Straight natural binary Coding bit set to 1 in control register Twos complement Coding bit set to 0 in control register CONVERSION RATE

Conversion Time 1.6 μs 16 SCLK cycles with SCLK = 10 MHz

Track-and-Hold Acquisition

Throughput Rate 500 kSPS See the Serial Interface section POWER REQUIREMENTS Digital inputs = 0 V or V

V

VSS −12 −16.5 V See Tab le 6

VCC 2.7 5.25 V See Table 6

V

Normal Mode (Static) 0.9 mA VDD/VSS = ±16.5 V, VCC/V

Normal Mode (Operational) f

Autostandby Mode (Dynamic) f

1

3

13.5 pF When in track, ±10 V range

Min Typ Max Unit Test Conditions/Comments

±5 mV

at 25°C

±10 mV

to T

MAX

T

MIN

25 ppm/°C

Coefficient

2.4 V

INH

0.8 V VCC = 4.75 V to 5.25 V

INL

3

IN

10 pF

V I

−

V

DRIVE

SOURCE

DRIVE

= 200 μA

0.2 V = 200 μA

SINK

3

Capacitance

2, 3

Time

12 16.5 V See Table 6

DD

2.7 5.25 V

DRIVE

5 pF

305 ns Full-scale step input; see the Terminology section

= 500 kSPS

SAMPLE

IDD 180 μA VDD = 16.5 V ISS 205 μA VSS = −16.5 V ICC and I

2.2 mA VCC/V

DRIVE

= 250 kSPS

SAMPLE

= 5.25 V

IDD 100 μA VDD = 16.5 V ISS 110 μA VSS = −16.5 V ICC and I

0.75 mA VCC/V

DRIVE

Rev. A | Page 5 of 36

DRIVE

= 5.25 V

DRIVE

= 5.25 V

AD7327

B Version Parameter

Autoshutdown Mode (Static) SCLK on or off

Full Shutdown Mode SCLK on or off

POWER DISSIPATION

Normal Mode (Operational) 18 mW VDD = +16.5 V, VSS = −16.5 V, VCC = +5.25 V Full Shutdown Mode 38.25 μW VDD = +16.5 V, VSS = −16.5 V, VCC = +5.25 V

1

Temperature range is −40°C to +85°C.

2

See the Terminology section.

3

Sample tested during initial release to ensure compliance.

4

For dc accuracy specifications, the LSB size for differential mode is FSR/8192. For single-ended mode/pseudo differential mode, the LSB size is FSR/4096, unless

otherwise noted.

5

Unipolar 0 V to 10 V range with straight binary output coding.

6

Bipolar range with twos complement output coding.

1

Min Typ Max Unit Test Conditions/Comments

IDD 1 μA VDD = 16.5 V ISS 1 μA VSS = −16.5 V ICC and I

1 μA VCC/V

DRIVE

= 5.25 V

IDD 1 μA VDD = 16.5 V ISS 1 μA VSS = −16.5 V ICC and I

1 μA VCC/V

DRIVE

= 5.25 V

Rev. A | Page 6 of 36

AD7327

TIMING SPECIFICATIONS

VDD = 12 V to 16.5 V, VSS = −12 V to −16.5 V, VCC = 2.7 V to 5.25 V, V T

= T

to T

A

MAX

. Timing specifications apply with a 32 pF load, unless otherwise noted.1

MIN

Table 3.

Limit at T

MIN

, T

MAX

Description

Parameter VCC < 4.75 V VCC = 4.75 V to 5.25 V Unit V

f

SCLK

50 50 kHz min 10 10 MHz max t

CONVER T

t

75 60 ns min

QUIET

t

1

2

t

2

16 × t

SCLK

ns max t

SCLK

12 5 ns min

25 20 ns min 45 35 ns min Unipolar input range (0 V to 10 V) t

3

t

4

t5 0.4 × t t6 0.4 × t t

7

t

8

26 14 ns max

57 43 ns max Data access time after SCLK falling edge

SCLK

0.4 × t

SCLK

0.4 × t

SCLK

ns min SCLK high pulse width

SCLK

ns min SCLK low pulse width

13 8 ns min SCLK to data valid hold time

40 22 ns max SCLK falling edge to DOUT high impedance 10 9 ns min SCLK falling edge to DOUT high impedance t

9

t

10

t

POWER-UP

1

Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V

2

When using the 0 V to 10 V unipolar range, running at 500 kSPS throughput rate with t2 at 20 ns, the mark space ratio needs to be limited to 50:50.

4 4 ns min DIN set-up time prior to SCLK falling edge

2 2 ns min DIN hold time after SCLK falling edge

750 750 ns max Power-up from autostandby

500 500 μs max

25 25 μs typ

CS

t

6

t

4

CONVERT

t

7

t

10

SCLK

DOUT

DIN

THREE-

STATE

t

2

1 2 3 4 5 13 14 15 16

3 IDENTIFICATION BITS

t

3

ADD1

ADD2

WRITE

ADD0 SIGN DB11 DB10 DB2 DB1 DB0

t

9

REG

SEL1

SEL2

Figure 2. Serial Interface Timing Diagram

= 2.7 V to 5.25 V, V

DRIVE

≤ VCC

DRIVE

SCLK

= 1/f

SCLK

= 2.5 V to 3.0 V internal/external,

REF

Minimum time between end of serial read and next falling edge of CS Minimum CS

to SCLK set-up time; bipolar input ranges (±10 V, ±5 V, ±2.5 V)

CS

Delay from CS

pulse width

until DOUT three-state disabled

Power-up from full shutdown/autoshutdown mode, internal reference

Power-up from full shutdown/autoshutdown mode, external reference

) and timed from a voltage level of 1.6 V.

DRIVE

t

1

t

5

DON’T

LSBMSB

CARE

t

8

THREE-STATE

t

QUIET

05401-002

Rev. A | Page 7 of 36

AD7327

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 4.

Parameter Rating

VDD to AGND, DGND −0.3 V to +16.5 V VSS to AGND, DGND +0.3 V to −16.5 V VDD to VCC V

− 0.3 V to 16.5 V

CC

VCC to AGND, DGND −0.3 V to +7 V V

to AGND, DGND −0.3 V to +7 V

DRIVE

AGND to DGND −0.3 V to +0.3 V Analog Input Voltage to AGND

1

VSS − 0.3 V to VDD + 0.3 V Digital Input Voltage to DGND −0.3 V to +7 V Digital Output Voltage to GND −0.3 V to V

DRIVE

+ 0.3 V REFIN to AGND −0.3 V to VCC + 0.3 V Input Current to Any Pin

Except Supplies

2

±10 mA

Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C TSSOP Package

θJA Thermal Impedance 143°C/W θJC Thermal Impedance 45°C/W

Pb-Free Temperature, Soldering

Reflow 260(0)°C

ESD 2.5 kV

1

If the analog inputs are driven from alternative VDD and VSS supply circuitry,

Schottky diodes should be placed in series with the AD7327 VDD and VSS supplies. See Power Supply Configuration section.

2

Transient currents of up to 100 mA do not cause SCR latch-up.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. A | Page 8 of 36

AD7327

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

CS

DIN

DGND

AGND

REFIN/OUT

V

IN

V

IN

V

IN

VIN5

SS

0

1

4

1

2

3

4

TOP VIEW

(Not to Scale)

5

6

7

8

9

10

AD7327

20

SCLK

19

DGND

18

DOUT

17

V

DRIVE

16

V

CC

15

V

DD

14

VIN2

13

3

V

IN

12

6

V

IN

11

V

7

IN

05401-003

Figure 3. TSSOP Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1

CS

Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7327 and frames the serial data transfer.

2 DIN

Data In. Data to be written to the on-chip registers is provided on this input and is clocked into the AD7327 on the falling edge of SCLK (see the Registers section).

3, 19 DGND

Digital Ground. Ground reference point for all digital circuitry on the AD7327. The DGND and AGND voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a transient basis.

4 AGND

Analog Ground. Ground reference point for all analog circuitry on the AD7327. All analog input signals and any external reference signal should be referred to this AGND voltage. The AGND and DGND voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a transient basis.

5 REFIN/OUT

Reference Input/Reference Output. The on-chip reference is available on this pin for external use to the AD7327. The nominal internal reference voltage is 2.5 V, which appears at this pin. A 680 nF capacitor should be placed on the reference pin (see the Reference section). Alternatively, the internal reference can be disabled and an external reference applied to this input. On power-up, the external reference mode is the default condition.

6 VSS Negative Power Supply Voltage. This is the negative supply voltage for the analog input section.

V

7, 8, 14, 13, 9, 10, 12, 11

0 to VIN7

IN

Analog Input 0 to Analog Input 7. The analog inputs are multiplexed into the on-chip track-and-hold. The analog input channel for conversion is selected by programming the channel address Bit ADD2 through Bit ADD0 in the control register. The inputs can be configured as eight single-ended inputs, four true differential input pairs, four pseudo differential inputs, or seven pseudo differential inputs. The configuration of the analog inputs is selected by programming the mode bits, Bit Mode 1 and Bit Mode 0, in the control register. The input range on each input channel is controlled by programming the range registers. Input ranges of ±10 V, ±5 V, ±2.5 V, and 0 V to +10 V can be selected on each

analog input channel when a +2.5 V reference voltage is used (see the Registers section). 15 VDD Positive Power Supply Voltage. This is the positive supply voltage for the analog input section. 16 VCC

Analog Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for the ADC core on the AD7327.

This supply should be decoupled to AGND. 17 V

DRIVE

Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface

operates. This pin should be decoupled to DGND. The voltage at this pin may be different to that at V

but it should not exceed V 18 DOUT

Serial Data Output. The conversion output data is supplied to this pin as a serial data stream. The bits

by more than 0.3 V.

CC

are clocked out on the falling edge of the SCLK input, and 16 SCLKs are required to access the data. The

data stream consists of three channel identification bits, the sign bit, and 12 bits of conversion data.

The data is provided MSB first (see the Serial Interface section). 20 SCLK

Serial Clock, Logic Input. A serial clock input provides the SCLK used for accessing the data from the

AD7327. This clock is also used as the clock source for the conversion process.

,

CC

Rev. A | Page 9 of 36

AD7327

TYPICAL PERFORMANCE CHARACTERISTICS

SNR (dB)

–20

–40

–60

–80

–100

–120

–140

–20

–40

–60

–80

–100

–120

–140

0

50 100 150 200 250

FREQUENC Y (kHz)

Figure 4. FFT True Differential Mode

0

50 100 150 200 250

FREQUENC Y (kHz)

Figure 5. FFT Single-Ended Mode

4096 POINT FFT V

CC=VDRIVE

V

DD,VSS

T

A

INT/EX T 2.5V REFERENCE ±10V RANGE F

IN

SNR = 77.30d B SINAD = 76.85dB THD = –86. 96dB SFDR = –88. 22dB

4096 POINT FFT V

CC=VDRIVE

V

DD,VSS

T

=25°C

A

INT/EXT 2.5V REFERENCE ±10V RANGE F

IN

SNR = 74.67dB SINAD = 74. 03dB THD = –82.68d B SFDR = –85. 40dB

=25°C

= 50kHz

=±15V

= ±15V

=5V

05401-004

5401-005

1.0 VCC=V T

0.8

A

V

DD,VSS

0.6

0.4

0.2

0

–0.2

INL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

08

512 1536 2560 3584 4608 5632 6656 7680

=5V

DRIVE

= 25°C

1024 2048 3072 4096 5120 6144 7168

INT/EXT 2.5V REF ERENCE ±10V RANGE

= ±15V

+INL = +0. 55LSB –INL = –0.68L SB

CODE

192

05401-007

Figure 7. Typical INL True Differential Mode

1.0

0.8

0.6

0.4

0.2

0

–0.2

DNL ERROR (LSB)

–0.4

VCC=V

–0.6

T

A

V

–0.8

DD,VSS

INT/EXT 2.5V REFERENCE

–1.0

0

512 1536 2560 3584 4608 5632 6656 7680

=5V

DRIVE

=25°C

= ±15V

1024 2048 3072 4096 5120 6144 7168

±10V RANGE +DNL = +0. 79LSB –DNL = –0.38LS B

CODE

8192

05401-043

Figure 8. Typical DNL Single-Ended Mode

1.0

0.8

0.6

0.4

0.2

0

–0.2

DNL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

08192

1024 2048 3072 4096 5120 6144 7168

512 1536 2560 3584 4608 5632 6656 7680

VCC=V

DRIVE

T

= 25°C

A

V

= ±15V

DD,VSS

INT/EXT 2.5V REFERENCE ±10V RANGE +DNL = +0.72LSB –DNL = –0. 22LSB

CODE

=5V

05401-006

Figure 6. Typical DNL True Differential Mode

0.8

0.6

0.4

0.2

0

–0.2

INL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

0

1024 2048 3072 4096 5120 6144 7168

512 1536 2560 3584 4608 5632 6656 7680

Figure 9. Typical INL Single-Ended Mode

Rev. A | Page 10 of 36

VCC=V

DRIVE

= 25°C

T

A

=±15V

V

DD,VSS

INT/EXT 2.5V REFERENCE ±10V RANGE +INL = + 0.87LSB –INL = –0.49L SB

CODE

=5V

8192

05401-044

AD7327

–

50

VCC=V V

–55

DD/VSS

T

=25°C

A

f

= 500kSPS

–60

S

INTERNAL REFERENCE

–65

–70

–75

THD (dB)

–80

–85

–90

–95

–100

10 1000

=3V

DRIVE

= ±12V

0V TO + 10V SE

±5V SE

100

ANALOG I NPUT FRE QUENCY (kHz )

±10V SE

±10V DIFF

0V TO +10V DI FF

±5V DIFF

±2.5V DIFF

±2.5V SE

Figure 10. THD vs. Analog Input Frequency

for Single-Ended (SE) and True Differential Mode (Diff) at 3 V V

05401-060

CC

80

75

70

65

SINAD (dB)

60

55

50

10 1000

ANALOG I NPUT FRE QUENCY (kHz)

±5V DIFF

±2.5V DIFF

±10V SE

0V TO +10V SE

VCC=V V

DD/VSS

T

A

f

= 500kSPS

S

INTERNAL REFERENCE

100

0V TO +10V DIFF

DRIVE

=±12V

= 25°C

±5V SE

±2.5V SE

±10V DIFF

=5V

Figure 13. SINAD vs. Analog Input Frequency

for Single-Ended (SE) and True Differential Mode (Diff) at 5 V V

05401-063

CC

50

VCC=V

–55

V

DD/VSS

T

A

f

= 500kSPS

–60

S

INTERNAL REFERENCE

–65

–70

–75

THD (dB)

–80

–85

–90

–95

–100

10 1000

=5V

DRIVE

=±12V

= 25°C

ANALOG I NPUT FRE QUENCY (kHz)

0V TO + 10V SE

±10V SE

±10V DIFF

0V TO + 10V DIFF

±5V SE

±5V DIFF

±2.5V SE

±2.5V DIFF

100

Figure 11. THD vs. Analog Input Frequency

for Single-Ended (SE) and True Differential Mode (Diff) at 5 V V

80

75

70

65

SINAD (dB)

60

55

50

10 1000

ANALOG I NPUT FRE QUENCY (kHz)

±5V DIFF

±10V SE

0V TO + 10V SE

VCC=V V

DD/VSS

T

= 25°C

A

f

= 500kSPS

S

INTERNAL REFERENCE

100

±2.5V DIFF

±5V SE

±2.5V SE

0V TO +10V DIFF

±10V DIFF

=3V

DRIVE

=±12V

Figure 12. SINAD vs. Analog Input Frequency

for Single-Ended (SE) and True Differential Mode (Diff) at 3 V V

50

–55

–60

–65

–70

–75

–80

–85

–90

CHANNEL-TO-CHANNE L ISOLATION (dB)

–95

05401-061

100 200 300 400 500

0 600

FREQUENCY OF INPUT NOISE (kHz)

VCC=3V

VDD/VSS=±12V SINGLE -ENDED M ODE f

S

T

A

50kHz ON SELECTED CHANNEL

= 500kSPS

=25°C

VCC=5V

05401-012

Figure 14. Channel-to-Channel Isolation

CC

10k

9k

8k

7k

6k

5k

4k

3k

NUMBER OF OCCURRENCES

2k

1k

0

–2

05401-062

228

–1 0 1 2

9469

CODE

VCC=5V V

=±12V

DD/VSS

RANGE = ±10V 10k SAMPLES T

= 25°C

A

303

0

05401-013

Figure 15. Histogram of Codes, True Differential Mode

CC

Rev. A | Page 11 of 36

ANALOG DEVICES AD7327 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS