Analog Devices AD624SD-883B, AD624SCHIPS, AD624CD, AD624BD, AD624AD Datasheet

REV. C

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a

AD624

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

Precision

Instrumentation Amplifier

PRODUCT DESCRIPTION

The AD624 is a high precision, low noise, instrumentation
amplifier designed primarily for use with low level transducers,
including load cells, strain gauges and pressure transducers. An
outstanding combination of low noise, high gain accuracy, low
gain temperature coefficient and high linearity make the AD624
ideal for use in high resolution data acquisition systems.

The AD624C has an input offset voltage drift of less than

0.25 µV/°C, output offset voltage drift of less than 10 µV/°C,
CMRR above 80 dB at unity gain (130 dB at G = 500) and a
maximum nonlinearity of 0.001% at G = 1. In addition to these
outstanding dc specifications, the AD624 exhibits superior ac
performance as well. A 25 MHz gain bandwidth product, 5 V/µs
slew rate and 15 µs settling time permit the use of the AD624 in
high speed data acquisition applications.

The AD624 does not need any external components for pre­trimmed gains of 1, 100, 200, 500 and 1000. Additional gains
such as 250 and 333 can be programmed within one percent
accuracy with external jumpers. A single external resistor can
also be used to set the 624’s gain to any value in the range of 1
to 10,000.

PRODUCT HIGHLIGHTS

1. The AD624 offers outstanding noise performance. Input

noise is typically less than 4 nV/√Hz at 1 kHz.

2. The AD624 is a functionally complete instrumentation am­plifier. Pin programmable gains of 1, 100, 200, 500 and 1000
are provided on the chip. Other gains are achieved through
the use of a single external resistor.

3. The offset voltage, offset voltage drift, gain accuracy and gain
temperature coefficients are guaranteed for all pretrimmed
gains.

4. The AD624 provides totally independent input and output
offset nulling terminals for high precision applications.
This minimizes the effect of offset voltage in gain ranging
applications.

5. A sense terminal is provided to enable the user to minimize
the errors induced through long leads. A reference terminal is
also provided to permit level shifting at the output.

FEATURES
Low Noise: 0.2 ␮V p-p 0.1 Hz to 10 Hz
Low Gain TC: 5 ppm max (G = 1)
Low Nonlinearity: 0.001% max (G = 1 to 200)
High CMRR: 130 dB min (G = 500 to 1000)
Low Input Offset Voltage: 25 ␮V, max
Low Input Offset Voltage Drift: 0.25 ␮V/ⴗC max
Gain Bandwidth Product: 25 MHz
Pin Programmable Gains of 1, 100, 200, 500, 1000
No External Components Required
Internally Compensated

FUNCTIONAL BLOCK DIAGRAM

225.3⍀

124⍀

4445.7⍀

80.2⍀

50⍀

V

B

50⍀

20k⍀ 10k⍀

10k⍀

10k⍀

AD624

–INPUT

G = 100

G = 200

G = 500

RG

1

RG

2

+INPUT

SENSE

OUTPUT

REF

20k⍀ 10k⍀

REV. C

–2–

AD624–SPECIFICATIONS

Model AD624A AD624B AD624C AD624S

Min Typ Max Min Typ Max Min Typ Max Min Typ Max Units

GAIN

Gain Equation

(External Resistor Gain
Programming)

40, 000

R

G

+ 1











± 20%

40, 000

R

G

+ 1











± 20%

40, 000

R

G

+ 1











± 20%

40, 000

R

G

+ 1











± 20%

Gain Range (Pin Programmable) 1 to 1000 1 to 1000 1 to 1000 1 to 1000
Gain Error

G = 1

±

0.05

±

0.03

±

0.02

±

0.05 %

G = 100

±

0.25

±

0.15

±

0.1

±

0.25 %

G = 200, 500

±

0.5

±

0.35

±

0.25

±

0.5 %

Nonlinearity

G = 1 ±0.005 ±0.003 ±0.001 ±0.005 %
G = 100, 200 ±0.005 ±0.003 ±0.001 ±0.005 %
G = 500 ±0.005 ±0.005 ±0.005 ±0.005 %

Gain vs. Temperature

G = 1 5 5 5 5 ppm/°C
G = 100, 200 10 10 10 10 ppm/°C
G = 500 25 15 15 15 ppm/°C

VOLTAGE OFFSET (May be Nulled)

Input Offset Voltage 200 75 25 75 µV

vs. Temperature 2 0.5 0.25 2.0 µV/°C

Output Offset Voltage 5323mV

vs. Temperature 50 25 10 50 µV/°C

Offset Referred to the Input vs. Supply

G = 1 70 75 80 75 dB
G = 100, 200 95 105 110 105 dB
G = 500 100 110 115 110 dB

INPUT CURRENT

Input Bias Current

±

50

±

25

±

15

±

50 nA

vs. Temperature ±50 ± 50 ±50 ± 50 pA/°C

Input Offset Current

±

35

±

15

±

10

±

35 nA

vs. Temperature ±20 ± 20 ±20 ± 20 pA/°C

INPUT

Input Impedance

Differential Resistance 10

9

10

9

10

9

10

9

Ω

Differential Capacitance 10 10 10 10 pF
Common-Mode Resistance 10

9

10

9

10

9

10

9

Ω

Common-Mode Capacitance 10 10 10 10 pF

Input Voltage Range

1

Max Differ. Input Linear (VDL) ± 10 ±10 ± 10 ± 10 V

Max Common-Mode Linear (V

CM

)

12 V −

G

2

× V

D











12 V −

G

2

× V

D











12 V −

G

2

× V

D











12 V −

G

2

× V

D











V

Common-Mode Rejection dc
to 60 Hz with 1 kΩ Source Imbalance

G = 1 70 75 80 70 dB
G = 100, 200 100 105 110 100 dB
G = 500 110 120 130 110 dB

OUTPUT RATING

V

OUT

, RL = 2 kΩ±10 ± 10 ±10 ± 10 V

DYNAMIC RESPONSE

Small Signal –3 dB

G = 1 1111MHz
G = 100 150 150 150 150 kHz
G = 200 100 100 100 100 kHz
G = 500 50 50 50 50 kHz
G = 1000 25 25 25 25 kHz

Slew Rate 5.0 5.0 5.0 5.0 V/µs
Settling Time to 0.01%, 20 V Step

G = 1 to 200 15 15 15 15 µs
G = 500 35 35 35 35 µs
G = 1000 75 75 75 75 µs

NOISE

Voltage Noise, 1 kHz

R.T.I. 4 4 4 4 nV/√Hz
R.T.O. 75 75 75 75 nV/√Hz

R.T.I., 0.1 Hz to 10 Hz

G = 1 10101010µV p-p
G = 100 0.3 0.3 0.3 0.3 µV p-p
G = 200, 500, 1000 0.2 0.2 0.2 0.2 µV p-p

Current Noise

0.1 Hz to 10 Hz 60 60 60 60 pA p-p

SENSE INPUT

R

IN

8 10 12 8 10 12 8 10 12 8 10 12 kΩ

I

IN

30 30 30 30 µA

Voltage Range ±10 ±10 ± 10 ±10 V
Gain to Output 1 1 1 1 %

(@ VS = ⴞ15 V, RL = 2 k⍀ and TA = +25ⴗC, unless otherwise noted)

REV. C –3–

AD624

Model AD624A AD624B AD624C AD624S

Min Typ Max Min Typ Max Min Typ Max Min Typ Max Units

REFERENCE INPUT

R

IN

16 20 24 16 20 24 16 20 24 16 20 24 kΩ

I

IN

30 30 30 30 µA

Voltage Range ± 10 ±10 ± 10 ±10 V
Gain to Output 1 1 1 1 %

TEMPERATURE RANGE

Specified Performance –25 +85 –25 +85 –25 +85 –55 +125 °C
Storage –65 +150 –65 +150 –65 +150 –65 +150 °C

POWER SUPPLY

Power Supply Range

ⴞ

6

ⴞ

15

ⴞ

18

ⴞ

6

ⴞ

15

ⴞ

18

ⴞ

6

ⴞ

15

ⴞ

18

ⴞ

6

ⴞ

15

ⴞ

18 V

Quiescent Current 3.5 5 3.5 5 3.5 5 3.5 5 mA

NOTES

1

VDL is the maximum differential input voltage at G = 1 for specified nonlinearity, VDL at other gains = 10 V/G. VD = actual differential input voltage.

1

Example: G = 10, VD = 0.50. VCM = 12 V – (10/2 × 0.50 V) = 9.5 V.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all production unit at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min

and max specifications are guaranteed, although only those shown in boldface are tested on all production units.

ABSOLUTE MAXIMUM RATINGS*

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V

Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . 420 mW

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± V

S

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . ±V

S

Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite

Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C

Operating Temperature Range

AD624A/B/C . . . . . . . . . . . . . . . . . . . . . . . –25°C to +85°C

AD624S . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C

Lead Temperature (Soldering, 60 secs) . . . . . . . . . . . . +300°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

CONNECTION DIAGRAM

–INPUT

+INPUT

RG

1

OUTPUT NULL

INPUT NULL

REF

–V

S

G = 200

G = 500

SENSE

RG

2

INPUT NULL

OUTPUT NULL

G = 100

+V

S

OUTPUT

1

2

5

6

7

3

4

8

16

15

12

11

10

14

13

9

TOP VIEW

(Not to Scale)

AD624

SHORT TO
RG

2

FOR
DESIRED
GAIN

FOR GAINS OF 1000 SHORT RG1 TO PIN 12
AND PINS 11 AND 13 TO RG

2

METALIZATION PHOTOGRAPH

Contact factory for latest dimensions

Dimensions shown in inches and (mm).

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

AD624AD –25°C to +85°C 16-Lead Ceramic DIP D-16
AD624BD –25°C to +85°C 16-Lead Ceramic DIP D-16
AD624CD –25°C to +85°C 16-Lead Ceramic DIP D-16
AD624SD –55°C to +125°C 16-Lead Ceramic DIP D-16
AD624SD/883B* –55°C to +125°C 16-Lead Ceramic DIP D-16
AD624AChips –25°C to +85°CDie
AD624SChips –25°C to +85°CDie

*See Analog Devices’ military data sheet for 883B specifications.

REV. C

AD624–Typical Characteristics

20

0

0

20

15

5

5

10

15

10

SUPPLY VOLTAGE – ⴞV

INPUT VOLTAGE RANGE – ⴞV

+25ⴗC

Figure 1. Input Voltage Range vs.
Supply Voltage, G = 1

8.0

0

0

20

6.0

2.0

5

4.0

1510

SUPPLY VOLTAGE – ⴞV

AMPLIFIER QUIESCENT CURRENT – mA

Figure 4. Quiescent Current vs.
Supply Voltage

16

0

20

4

2

50

8

6

10

12

14

15

10

INPUT VOLTAGE – ⴞV

INPUT BIAS CURRENT – ⴞnA

Figure 7. Input Bias Current vs. CMV

20

0

0

20

15

5

5

10

15

10

SUPPLY VOLTAGE – ⴞV

OUTPUT VOLTAGE SWING – ⴞV

Figure 2. Output Voltage Swing vs.
Supply Voltage

16

0

20

4

2

50

8

6

10

12

14

15

10

SUPPLY VOLTAGE – ⴞV

INPUT BIAS CURRENT – ⴞnA

Figure 5. Input Bias Current vs.
Supply Voltage

–1

7

8.0

5

6

1.00

3

4

2

1

0

7.06.05.04.03.02.0

WARM-UP TIME – Minutes

⌬VOS FROM FINAL VALUE – ␮V

Figure 8. Offset Voltage, RTI, Turn
On Drift

10

100 10k1k

30

20

0

10

LOAD RESISTANCE – ⍀

OUTPUT VOLTAGE SWING – V p-p

Figure 3. Output Voltage Swing vs.
Load Resistance

40

–40

125

–20

–30

–75

0

–10

10

20

30

7525–25

TEMPERATURE – ⴗC

INPUT BIAS CURRENT – nA

–125

Figure 6. Input Bias Current vs.
Temperature

0

500

100

10

1

1

10 10M1M100k10k1k100

FREQUENCY – Hz

GAIN – V/V

Figure 9. Gain vs. Frequency

–4–

REV. C

AD624

–5–

0

1

10 10M1M100k10k1k100

FREQUENCY – Hz

–100

–80

–60

–40

CMRR – dB

–120

–140

–20

G = 500

G = 1

G = 100

Figure 10. CMRR vs. Frequency RTI,
Zero to 1k Source Imbalance

160

0

100k

40

20

10

80

60

100

120

140

10k1k100

FREQUENCY – Hz

POWER SUPPLY REJECTION – dB

G = 500

G = 100

G = 1

–VS = –15V dc+
1V p-p SINEWAVE

Figure 13. Negative PSRR vs.
Frequency

Figure 16. Low Frequency Voltage
Noise

,

G = 1 (System Gain = 1000)

30

20

0

10

FULL-POWER RESPONSE – V p-p

FREQUENCY – Hz

10k1k 100k 1M

G = 1, 100

G = 500

G = 100

G = 1000

BANDWIDTH LIMITED

-

Figure 11. Large Signal Frequency
Response

VOLT NSD – nV/ Hz

0.1

100

1

10

1000

100k101 10k1k100

FREQUENCY – Hz

G = 1

G = 10

G = 100, 1000

G = 1000

Figure 14. RTI Noise Spectral
Density vs. Gain

Figure 17. Low Frequency Voltage
Noise, G = 1000 (System Gain =
100,000)

160

0

100k

40

20

10

80

60

100

120

140

10k1k100

FREQUENCY – Hz

POWER SUPPLY REJECTION – dB

G = 500

G = 100

G = 1

–VS = –15V dc+
1V p-p SINEWAVE

Figure 12. Positive PSRR vs.
Frequency

10

10k

100

1000

100k

100k10.1 10k10010

FREQUENCY – Hz

CURRENT NOISE SPECTRAL DENSITY – fA/ Hz

Figure 15. Input Current Noise

20

8 TO –8

12 TO –12

0

OUTPUT
STEP –V

4 TO –4

–4 TO 4

–8 TO 8

–12 TO 12

15105

SETTLING TIME – ␮s

1%

1%

0.1% 0.01%

0.1% 0.01%

Figure 18. Settling Time, Gain = 1