Analog Devices AD600 2 d Datasheet

Dual, Low Noise, Wideband

a

FEATURES
2 Channels with Independent Gain Control

"Linear in dB" Gain Response

2 Gain Ranges:

AD600: 0 dB to 40 dB
AD602: –10 dB to +30 dB

Accurate Absolute Gain: 0.3 dB
Low Input Noise: 1.4 nV/√Hz
Low Distortion: –60 dBc THD at 1 V Output
High Bandwidth: DC to 35 MHz (–3 dB)
Stable Group Delay: 2 ns
Low Power: 125 mW (Max) per Amplifier
Signal Gating Function for Each Amplifier
Drives High Speed A/D Converters
MIL-STD-883-Compliant and DESC Versions Available

APPLICATIONS
Ultrasound and Sonar Time-Gain Control
High Performance Audio and RF AGC Systems
Signal Measurement

GENERAL DESCRIPTION

The AD600 and AD602 dual channel, low noise, variable gain
amplifiers are optimized for use in ultrasound imaging systems,
but are applicable to any application requiring very precise gain,
low noise and distortion, and wide bandwidth. Each indepen­dent channel provides a gain of 0 dB to +40 dB in the AD600
and –10 dB to +30 dB in the AD602. The lower gain of the
AD602 results in an improved signal-to-noise ratio at the out­put. However, both products have the same 1.4 nV/√Hz input
noise spectral density. The decibel gain is directly proportional
to the control voltage, is accurately calibrated, and is supply­and temperature-stable.

To achieve the difficult performance objectives, a proprietary
circuit form—the X-AMP
nel of the X-AMP comprises a variable attenuator of 0 dB to
–42.14 dB followed by a high speed fixed gain amplifier. In this
way, the amplifier never has to cope with large inputs, and can
benefit from the use of negative feedback to precisely define the
gain and dynamics. The attenuator is realized as a seven-stage
R-2R ladder network having an input resistance of 100 Ω, laser­trimmed to ±2%. The attenuation between tap points is 6.02 dB;
the gain-control circuit provides continuous interpolation between
these taps. The resulting control function is linear in dB.

*Patented.

®

—has been developed. Each chan-

Variable Gain Amplifiers

AD600/AD602

FUNCTIONAL BLOCK DIAGRAM

GAT1

SCALING

REFERENCE

C1HI

V

G

C1LO

GAIN CONTROL

INTERFACE

A1HI

A1LO

0dB

500

–12.04dB

–6.02dB

R-2R LADDER NETWORK

The gain-control interfaces are fully differential, providing an
input resistance of ~15 MΩ and a scale factor of 32 dB/V (that
is, 31.25 mV/dB) defined by an internal voltage reference. The
response time of this interface is less than 1 µs. Each channel
also has an independent gating facility that optionally blocks
signal transmission and sets the dc output level to within a few
millivolts of the output ground. The gating control input is TTL
and CMOS compatible.

The maximum gain of the AD600 is 41.07 dB, and that of the
AD602 is 31.07 dB; the –3 dB bandwidth of both models is
nominally 35 MHz, essentially independent of the gain. The
signal-to-noise ratio (SNR) for a 1 V rms output and a 1 MHz
noise bandwidth is typically 76 dB for the AD600 and 86 dB for
the AD602. The amplitude response is flat within ±0.5 dB from
100 kHz to 10 MHz; over this frequency range the group delay
varies by less than ±2 ns at all gain settings.

Each amplifier channel can drive 100 Ω load impedances with
low distortion. For example, the peak specified output is ±2.5 V
minimum into a 500 Ω load, or ± 1 V into a 100 Ω load. For a
200 Ω load in shunt with 5 pF, the total harmonic distortion for
a ±1 V sinusoidal output at 10 MHz is typically –60 dBc.

The AD600J and AD602J are specified for operation from 0°C
to 70°C, and are available in both 16-lead plastic DIP (N) and
16-lead SOIC (R) packages. The AD600A and AD602A are
specified for operation from –40°C to +85°C and are available in
both 16-lead Cerdip (Q) and 16-lead SOIC (R) packages.

The AD600S and AD602S are specified for operation from
–55°C to +125°C, are available in a 16-lead Cerdip (Q) package,
and are MIL-STD-883 compliant. The AD600S and AD602S
are also available under DESC SMD 5962-94572.

PRECISION PASSIVE
INPUT ATTENUATOR

–22.08dB

–18.06dB

–30.1dB

–36.12dB

–42.14dB

62.5

GATING

INTERFACE

RF2

2.24k(AD600)
694(AD602)

RF1
20

FIXED-GAIN

AMPLIFIER

41.07dB(AD600)

31.07(AD602)

*

A1OP

A1CM

REV. D

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

AD600/AD602–SPECIFICATIONS

(Each amplifier section, at TA = 25C, VS = 5 V, –625 mV ≤ VG ≤

+625 mV, RL = 500 , and CL = 5 pF, unless otherwise noted. Specifications for the AD600 and AD602 are identical unless otherwise noted.)

Parameter Conditions Min Typ Max Min Typ Max Unit

AD600J/AD602J AD600A/AD602A

INPUT CHARACTERISTICS

Input Resistance Pins 2 to 3; Pins 6 to 7 98 100 102 95 100 105 Ω
Input Capacitance 22pF
Input Noise Spectral Density
Noise Figure R

1

= 50 Ω, Maximum Gain 5.3 5.3 dB

S

1.4 1.4 nV/√Hz

RS = 200 Ω, Maximum Gain 2 2 dB

Common-Mode Rejection Ratio f = 100 kHz 30 30 dB

OUTPUT CHARACTERISTICS

–3 dB Bandwidth V
Slew Rate 275 275 V/µs
Peak Output

2

= 100 mV rms 35 35 MHz

OUT

RL ≥ 500 Ω±2.5 ± 3 ±2.5 ±3V

Output Impedance f ≤ 10 MHz 2 2 Ω
Output Short-Circuit Current 50 50 mA
Group Delay Change vs. Gain f = 3 MHz; Full Gain Range ±2 ±2ns
Group Delay Change vs. Frequency VG = 0 V, f = 1 MHz to 10 MHz ±2 ±2ns
Total Harmonic Distortion RL= 200 Ω, V

= ±1 V Peak, Rpd = 1 kΩ –60 –60 dBc

OUT

ACCURACY

AD600

Gain Error 0 dB to 3 dB Gain 0 +0.5 +1 –0.5 +0.5 +1.5 dB

3 dB to 37 dB Gain –0.5 ± 0.2 +0.5 –1.0 ±0.2 +1.0 dB

37 dB to 40 dB Gain –1 –0.5 0 –1.5 –0.5 +0.5 dB
Maximum Output Offset Voltage3VG = –625 mV to +625 mV 10 50 10 65 mV
Output Offset Variation VG = –625 mV to +625 mV 10 50 10 65 mV

AD602

Gain Error –10 dB to –7 dB Gain 0 +0.5 +1 –0.5 +0.5 +1.5 dB

–7 dB to +27 dB Gain –0.5 ± 0.2 +0.5 –1.0 ±0.2 +1.0 dB

27 dB to 30 dB Gain –1 –0.5 0 –1.5 –0.5 +0.5 dB
Maximum Output Offset Voltage3VG = –625 mV to +625 mV 5 30 10 45 mV
Output Offset Variation VG = –625 mV to +625 mV 5 30 10 45 mV

GAIN CONTROL INTERFACE

Gain Scaling Factor 3 dB to 37 dB (AD600); –7 dB to +27 dB (AD602) 31.7 32 32.3 30.5 32 33.5 dB/V
Common-Mode Range –0.75 +2.5 –0.75 +2.5 V
Input Bias Current 0.35 1 0.35 1 µA
Input Offset Current 10 50 10 50 nA
Differential Input Resistance Pins 1 to 16; Pins 8 to 9 15 15 MΩ
Response Rate Full 40 dB Gain Change 40 40 dB/µs

SIGNAL GATING INTERFACE

Logic Input “LO” (Output ON) 0.8 0.8 V
Logic Input “HI” (Output OFF) 2.4 2.4 V
Response Time ON to OFF, OFF to ON 0.3 0.3 µs
Input Resistance Pins 4 to 3; Pins 5 to 6 30 30 kΩ
Output Gated OFF

Output Offset Voltage ±10 100 ± 10 400 mV
Output Noise Spectral Density 65 65 nV/√Hz
Signal Feedthrough @ 1 MHz

AD600 –80 –80 dB
AD602 –70 –70 dB

POWER SUPPLY

Specified Operating Range ±4.75 ±5.25 ±4.75 ±5.25 V
Quiescent Current 11 12.5 11 14 mA

NOTES

1

Typical open or short-circuited input; noise is lower when the system is set to maximum gain and the input is short-circuited. This figure includes the effects of both
voltage and current noise sources.

2

Using resistive loads of 500 Ω or greater, or with the addition of a 1 k Ω pull-down resistor when driving lower loads.

3

The dc gain of the main amplifier in the AD600 is ⫻113; thus an input offset of only 100 µV becomes an 11.3 mV output offset. In the AD602, the amplifier’s gain is
⫻35.7; thus, an input offset of 100 µV becomes a 3.57 mV output offset.

Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min
and max specifications guaranteed, although only those shown in boldface are tested on all production units.

Specifications subject to change without notice.

–2–

REV. D

AD600/AD602

ABSOLUTE MAXIMUM RATINGS

1

Supply Voltage ±VS . . . . . . . . . . . . . . . . . . . . . . . . . . . ±7.5 V

Input Voltages

Pins 1, 8, 9, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±V

S

Pins 2, 3, 6, 7 . . . . . . . . . . . . . . . . . . . . . . ±2 V Continuous

. . . . . . . . . . . . . . . . . . . . . . . . . ±V

Pins 4, 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± V

for 10 ms

S

S

Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . . 600 mW

Operating Temperature Range (J) . . . . . . . . . . . . 0°C to 70°C

Operating Temperature Range (A) . . . . . . . . –40°C to +85°C

Operating Temperature Range (S) . . . . . . . –55°C to +125°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

Thermal characteristics:

16-lead plastic package: θJA = 85°C/W
16-lead SOIC package: θJA = 100°C/W
16-lead Cerdip package: θJA = 120°C/W

ORDERING GUIDE

Model Gain Range Range Option

Temperature Package

1

AD600AQ 0 dB to 40 dB –40°C to +85°C Q-16
AD600AR 0 dB to 40 dB –40°C to +85°C R-16
AD600AR-REEL 0 dB to 40 dB –40°C to +85°C R-16
AD600AR-REEL7 0 dB to 40 dB –40°C to +85°C R-16
AD600ARZ
AD600ARZ-R7
AD600ARZ-RL

2

0 dB to 40 dB –40°C to +85°C R-16

2

0 dB to 40 dB –40°C to +85°C R-16

2

0 dB to 40 dB –40°C to +85°C R-16

AD600JCHIPS DIE
AD600JN 0 dB to 40 dB 0°C to 70°C N-16
AD600JR 0 dB to 40 dB 0°C to 70°C R-16
AD600JR-REEL 0 dB to 40 dB 0°C to 70°C R-16
AD600JR-REEL7 0 dB to 40 dB 0°C to 70°C R-16
AD600JRZ
AD600JRZ-R7
AD600JRZ-RL
AD600SQ/883B

2

0 dB to 40 dB 0°C to 70°C R-16

2

0 dB to 40 dB 0°C to 70°C R-16

2

0 dB to 40 dB 0°C to 70°C R-16

3

0 dB to 40 dB –55°C to +125°C Q-16
AD602AQ –10 dB to +30 dB –40°C to +85°C Q-16
AD602AR –10 dB to +30 dB –40°C to +85°C R-16
AD602AR-REEL –10 dB to +30 dB –40°C to +85°C R-16
AD602AR-REEL7 –10 dB to +30 dB –40°C to +85°C R-16
AD602JCHIPS DIE
AD602JN –10 dB to +30 dB 0°C to 70°C N-16
AD602JR –10 dB to +30 dB 0°C to 70°C R-16
AD602JR-REEL –10 dB to +30 dB 0°C to 70°C R-16
AD602JR-REEL7 –10 dB to +30 dB 0°C to 70°C R-16
AD602SQ/883B4–10 dB to +30 dB –55°C to +150°C Q-16

NOTES

1

N = plastic DIP; Q = Cerdip; R = small outline IC (SOIC).

2

Z = Pb-free part.

3

Refer to AD600/AD602 Military data sheet. Also available as 5962-9457201MEA.

4

Refer to AD600/AD602 Military data sheet. Also available as 5962-9457202MEA.

PIN FUNCTION DESCRIPTIONS

Pin Mnemonic Description

1 C1LO CH1 Gain-Control Input “LO” (Positive

Voltage Reduces CH1 Gain)

2 A1HI CH1 Signal Input “HI” (Positive Voltage

Increases CH1 Output)

3 A1LO CH1 Signal Input “LO” (Usually Taken to

CH1 Input Ground)

4 GAT1 CH1 Gating Input (A Logic “HI” Shuts Off

CH1 Signal Path)

5 GAT2 CH2 Gating Input (A Logic “HI” Shuts Off

CH2 Signal Path)

6 A2LO CH2 Signal Input “LO” (Usually Taken to

CH2 Input Ground)

7 A2HI CH2 Signal Input “HI” (Positive Voltage

Increases CH2 Output)

8 C2LO CH2 Gain-Control Input “LO” (Positive

Voltage Reduces CH2 Gain)

9 C2HI CH2 Gain-Control Input “HI” (Positive

Voltage Increases CH2 Gain)

10 A2CM CH2 Common (Usually Taken to CH2

Output Ground)
11 A2OP CH2 Output
12 VNEG Negative Supply for Both Amplifiers
13 VPOS Positive Supply for Both Amplifiers
14 A1OP CH1 Output
15 A1CM CH1 Common (Usually Taken to CH1

Output Ground)
16 C1HI CH1 Gain-Control Input “HI” (Positive

Voltage Increases CH1 Gain)

CONNECTION DIAGRAM

16-Lead Plastic DIP (N) Package

16-Lead Plastic SOIC (R) Package

16-Lead Cerdip (Q) Package

C1LO

A1HI

A1LO

GAT1

GAT2

A2LO

A2HI

C2LO

1

2

+

3

–

4

5

–

6

7

+

8

AD600 / AD602

A1

REF

A2

C1HI

16

A1CM

15

A1OP

14

VPOS

13

VNEG

12

11

A2OP

10

A2CM

9

C2HI

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD600/AD602 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

REV. D

–3–

WARNING!

ESD SENSITIVE DEVICE

AD600/AD602–Typical Performance Characteristics

0.45

0.35

0.25

0.15

0.05

–0.05

–0.15

GAIN ERROR – dB

–0.25

–0.35

–0.45

–0.5–0.7

GAIN CONTROL VOLTAGE – V

0.50.30.1–0.1–0.3

0.7

20dB

17dB

0

–45

–90

100k 1M 100M10M

FREQUENCY – Hz

10dB

7dB

0

–45

–90

100k 1M 100M10M

FREQUENCY – Hz

TPC 1. Gain Error vs. Gain Control
Voltage

10.0

9.8

9.6

9.4

9.2

9.0

8.8

8.6

GROUP DELAY – ns

8.4

8.2

8.0

GAIN CONTROL VOLTAGE – V

0.7–0.5–0.7 0.50.30.1–0.1–0.3

TPC 4. AD600 and AD602 Typical
Group Delay vs. V

102

101

100

99

98

97

96

95

INPUT IMPEDANCE – 

94

93

92

100k 1M 100M10M

FREQUENCY – Hz

C

GAIN = 40dB

GAIN = 20dB

GAIN = 0dB

TPC 2. AD600 Frequency and Phase
Response vs. Gain

VG = 0V
10dB/DIV
CENTER
FREQ 1MHz
10kHz/DIV

TPC 5. Third Order Intermodula­tion Distortion, V
RL = 500

–1

–2

OUTPUT OFFSET VOLTAGE – mV

–3

–4

Ω

6

5

4

3

2

1

0

–0.5

–0.7

GAIN CONTROL VOLTAGE – V

OUT

AD602

= 2 V p-p,

AD600

0.7

0.50.1 0.3–0.3 –0.1

TPC 3. AD602 Frequency and Phase
Response vs. Gain

–1.0

–1.2

–1.4

–1.6

–1.8

–2.0

–2.2

–2.4

–2.6

–2.8

–3.0

–3.2

NEGATIVE OUTPUT VOLTAGE LIMIT – V

–3.4

50

0

LOAD RESISTANCE – 

20001000500200100

TPC 6. Typical Output Voltage vs.
Load Resistance (Negative Output
Swing Limits First)

1µs

100

90

OUTPUTINPUT

10

0%

1V VOUT

1V VC

TPC 7. Input Impedance vs.
Frequency

TPC 8. Output Offset vs. Gain
Control Voltage (Control Channel
Feedthrough)

–4–

TPC 9. Gain Control Channel
Response Time. Top: Output Volt­age, 2 V max, Bottom: Gain Con­trol Voltage V

= ±625 mV

C

REV. D

AD600/AD602

50mV

100

90

OUTPUT

10

0%

INPUT

5V

100ns

TPC 10. Gating Feedthrough to
Output, Gating Off to On

500mV

100

90

OUTPUTINPUT

10

0%

1V

200ns

TPC 13. Input Stage Overload
Recovery Time

50mV

100

90

OUTPUTINPUT

10

0%

5V

100ns

TPC 11. Gating Feedthrough to
Output, Gating On to Off

1V

100

90

OUTPUTINPUT

10

0%

200mV

500ns

TPC 14. Output Stage Overload
Recovery Time

1V

100

90

OUTPUT

10

0%

INPUT

100mV

TPC 12. Transient Response,
Medium and High Gain

500mV

100

90

OUTPUTINPUT

10

0%

1V

TPC 15. Transient Response
Minimum Gain

500ns

500ns

10

AD600: G = 20dB

5

AD602: G = 10dB
BOTH: V

0

V
R

–5

T

–10

–15

–20

CMRR – dB

–25

–30

–35

–40

1k 10k 100k 1M 10M 100M

= 100mV RMS

CM

= 5V

S

= 500

L

= 25C

A

AD600

FREQUENCY – Hz

AD602

TPC 16. CMRR vs. Frequency

20

10

0

–10

–20

–30

–40

PSRR – dB

–50

–60

–70

–80

100k 1M 100M10M

AD600

AD602

FREQUENCY – Hz

AD600: G = 40dB
AD602: G = 30dB
BOTH: R

V
R

TPC 17. PSRR vs. Frequency

= 500

L

= 0V

IN

= 50

S

10

AD600: CH1 G = 40dB, V

0

–10

–20

–30

–40

–50

CROSSTALK – dB

–60

–70

–80

–90

100k 1M 100M10M

CH2 G = 20dB, V

AD602: CH1 G = 30dB, V

CH2 G = 0dB, V

BOTH: V

CROSSTALK = 20log

= 1V RMS1, RS = 50,

OUT

= 500

R

L

FREQUENCY – Hz

= 0

IN

= 100mV

IN

= 0

IN

= 316mV

IN

CH1 V

OUT

{}

CH2 V

IN

AD600

AD602

TPC 18. Crosstalk between A1
and A2 vs. Frequency

REV. D

–5–

AD600/AD602

THEORY OF OPERATION

The AD600 and AD602 have the same general design and
features. They comprise two fixed gain amplifiers, each pre­ceded by a voltage-controlled attenuator of 0 dB to 42.14 dB
with independent control interfaces, each having a scaling factor
of 32 dB per volt. The gain of each amplifier in the AD600 is
laser trimmed to 41.07 dB (⫻113), providing a control range
of –1.07 dB to +41.07 dB (0 dB to +40 dB with overlap). The
AD602 amplifiers have a gain of 31.07 dB (⫻35.8) and pro-
vide an overall gain of –11.07 dB to +31.07 dB (–10 dB to
+30 dB with overlap).

The advantage of this topology is that the amplifier can use
negative feedback to increase the accuracy of its gain. Also, since
the amplifier never has to handle large signals at its input, the
distortion can be very low. Another feature of this approach is
that the small-signal gain and phase response, and thus the
pulse response, are essentially independent of gain.

The following describes the AD600. Figure 1 is a simplified
schematic of one channel. The input attenuator is a seven-section
R-2R ladder network, using untrimmed resistors of nominally
R = 62.5 Ω, which results in a characteristic resistance of
125 Ω ± 20%. A shunt resistor is included at the input and laser
trimmed to establish a more exact input resistance of 100 Ω ± 2%,
which ensures accurate operation (gain and HP corner frequency)
when used in conjunction with external resistors or capacitors.

GAT1

PRECISION PASSIVE
INPUT ATTENUATOR

–22.08dB

–18.06dB

–30.1dB

–36.12dB

–42.14dB

62.5

GATING

INTERFACE

RF2

2.24k(AD600)
694(AD602)

RF1
20

FIXED-GAIN

AMPLIFIER

41.07dB(AD600)

31.07(AD602)

A1OP

A1CM

C1HI

C1LO

A1HI

A1LO

SCALING

REFERENCE

V

G

GAIN CONTROL

INTERFACE

0dB

500

–12.04dB

–6.02dB

R-2R LADDER NETWORK

Figure 1. Simplified Block Diagram of Single Channel of
the AD600 and AD602

The nominal maximum signal at input A1HI is 1 V rms (±1.4 V
peak) when using the recommended ±5 V supplies, although
operation to ±2 V peak is permissible with some increase in HF
distortion and feedthrough. Each attenuator is provided with a
separate signal “LO” connection for use in rejecting common
mode, the voltage between input and output grounds. Circuitry
is included to provide rejection of up to ±100 mV.

The signal applied at the input of the ladder network is attenu­ated by 6.02 dB by each section; thus, the attenuation to each of
the taps is progressively 0, 6.02, 12.04, 18.06, 24.08, 30.1, 36.12,
and 42.14 dB. A unique circuit technique is employed to interpo­late between these tap points, indicated by the “slider” in
Figure 1, providing continuous attenuation from 0 dB to 42.14 dB.

To understand the AD600, it helps to think in terms of a
mechanical means for moving this slider from left to right; in
fact, it is voltage controlled. The details of the control interface
are discussed later. Note that the gain is exactly determined
at all times, and a linear decibel relationship is automatically
guaranteed between the gain and the control parameter that
determines the position of the slider. In practice, the gain
deviates from the ideal law by about ±0.2 dB peak (see Figure 6).

Note that the signal inputs are not fully differential. A1LO,
A1CM (for CH1), A2LO, and A2CM (for CH2) provide
separate access to the input and output grounds. This recog­nizes that even when using a ground plane, small differences
arise in the voltages at these nodes. It is important that A1LO
and A2LO be connected directly to the input ground(s).
Significant impedance in these connections reduces the gain
accuracy. A1CM and A2CM should be connected to the load
ground(s).

Noise Performance

An important reason for using this approach is the superior
noise performance that can be achieved. The nominal resistance
seen at the inner tap points of the attenuator is 41.7 Ω (one third
of 125 Ω), which, at 27°C, exhibits a Johnson noise spectral den­sity (NSD) of 0.84 nV/√Hz (that is, √4kTR), a large fraction of
the total input noise. The first stage of the amplifier contributes
another 1.12 nV/√Hz, for a total input noise of 1.4 nV/√Hz.

The noise at the 0 dB tap depends on whether the input is
short-circuited or open-circuited. When shorted, the minimum
NSD of 1.12 nV/√Hz is achieved. When open, the resistance
of 100 Ω at the first tap generates 1.29 nV/√Hz, so the noise
increases to a total of 1.71 nV/√Hz. This last calculation would
be important if the AD600 were preceded, for example, by a
900 Ω resistor to allow operation from inputs up to ±10 V rms.
However, in most cases the low impedance of the source
limits the maximum noise resistance.

It is apparent from the foregoing that it is essential to use a low
resistance in the design of the ladder network to achieve low
noise. In some applications this may be inconvenient, requiring
the use of an external buffer or preamplifier. However, very few
amplifiers combine the needed low noise with low distortion at
maximum input levels, and the power consumption required to
achieve this performance is quite high (due to the need to maintain
very low resistance values while also coping with large inputs).
On the other hand, there is little value in providing a buffer
with high input impedance since the usual reason for this—
the minimization of loading of a high resistance source—is not
compatible with low noise.

Apart from the small variations just mentioned, the signal-to­noise (S/N) ratio at the output is essentially independent of the
attenuator setting, since the maximum undistorted output is
1Vrms and the NSD at the output of the AD600 is fixed at
113 ⫻ 1.4 nV/√Hz, or 158 nV/√Hz. Thus, in a 1 MHz band­width, the output S/N ratio would be 76 dB. The input NSD
of the AD600 and AD602 are the same, but because of the
10 dB lower gain in the AD602’s fixed amplifier, its output S/N
ratio is 10 dB better, or 86 dB in a 1 MHz bandwidth.

–6–

REV. D

AD600/AD602

The Gain-Control Interface

The attenuation is controlled through a differential, high imped­ance (15 MΩ) input, with a scaling factor that is laser trimmed to
32 dB per volt, that is, 31.25 mV/dB. Each of the two amplifiers
has its own control interface. An internal band gap reference
ensures stability of the scaling with respect to supply and tempera­ture variations, and is the only circuitry common to both channels.

When the differential input voltage V

= 0 V, the attenuator

G

slider is centered, providing an attenuation of 21.07 dB,
resulting in an overall gain of 20 dB (= –21.07 dB + 41.07 dB).
When the control input is –625 mV, the gain is lowered by
20 dB (= 0.625 × 32) to 0 dB; when set to 625 mV, the gain is
increased by 20 dB to 40 dB. When this interface is over­driven in either direction, the gain approaches either –1.07 dB
(= –42.14 dB + 41.07 dB) or 41.07 dB (= 0 + 41.07 dB),
respectively.

The gain of the AD600 can be calculated using the following
simple expression:

Gain (dB) = 32 V

where V

is in volts. For the AD602, the expression is:

G

Gain (dB) = 32 V

Operation is specified for V

+ 20 (1)

G

+ 10 (2)

G

in the range from –625 mV dc

G

to +625 mV dc. The high impedance gain-control input ensures
minimal loading when driving many amplifiers in multiple-channel
applications. The differential input configuration provides flexibil­ity in choosing the appropriate signal levels and polarities for
various control schemes.

For example, the gain-control input can be fed differentially to
the inputs, or single-ended by simply grounding the unused
input. In another example, if the gain is to be controlled by
a DAC providing a positive only ground referenced output,
the Gain Control LO pin (either C1LO or C2LO) should be
biased to a fixed offset of 625 mV to set the gain to 0 dB when
Gain Control HI (C1HI or C2HI) is at zero, and to set the
gain to 40 dB when at 1.25 V.

It is a simple matter to include a voltage divider to achieve other
scaling factors. When using an 8-bit DAC with an FS output of

2.55 V (10 mV/bit), a 1.6 divider ratio (generating 6.25 mV/bit)
results in a gain setting resolution of 0.2 dB/bit. Later in this data
sheet, cascading the two sections of an AD600 or AD602
when various options exist for gain control is explained.

Signal-Gating Inputs

Each amplifier section of the AD600 and AD602 is equipped
with a signal gating function, controlled by a TTL or CMOS
logic input (GAT1 or GAT2). The ground references for these
inputs are the signal input grounds A1LO and A2LO, respec­tively. Operation of the channel is unaffected when this input is
LO or left open-circuited. Signal transmission is blocked when
this input is HI. The dc output level of the channel is set to
within a few millivolts of the output ground (A1CM or A2CM),
and simultaneously the noise level drops significantly. The
reduction in noise and spurious signal feedthrough is useful
in ultrasound beam-forming applications, where many amplifier
outputs are summed.

Common-Mode Rejection

A special circuit technique provides rejection of voltages appear­ing between input grounds (A1LO and A2LO) and output
grounds (A1CM and A2CM). This is necessary because of the
op amp form of the amplifier, as shown in Figure 1. The
feedback voltage is developed across the resistor RF1 (which, to
achieve low noise, has a value of only 20 Ω). The voltage
developed across this resistor is referenced to the input common,
so the output voltage is also referred to that node.

For zero differential signal input between A1HI and A1LO,
the output A1OP simply follows the voltage at A1CM. Note that
the range of voltage differences that can exist between A1LO
and A1CM (or A2LO and A2CM) is limited to about ±100 mV.
TPC 16 shows typical common-mode rejection ratio versus
frequency.

ACHIEVING 80 dB GAIN RANGE

The two amplifier sections of the X-AMP can be connected
in series to achieve higher gain. In this mode, the output of
A1 (A1OP and A1CM) drives the input of A2 via a high-pass
network (usually just a capacitor) that rejects the dc offset. The
nominal gain range is now –2 dB to +82 dB for the AD600 or
–22 dB to +62 dB for the AD602.

There are several options in connecting the gain-control inputs.
The choice depends on the desired signal-to-noise ratio (SNR)
and gain error (output ripple). The following examples feature
the AD600; the arguments generally apply to the AD602, with
appropriate changes to the gain values.

Sequential Mode (Maximum S/N Ratio)

In the sequential mode of operation, the SNR is maintained at
its highest level for as much of the gain control range possible,
as shown in Figure 2. Note here that the gain range is 0 dB to
80 dB. Figure 3 shows the general connections to accomplish
this. Both gain-control inputs, C1HI and C2HI, are driven in
parallel by a positive only, ground referenced source with a
range of 0 V to 2.5 V.

85

80

75

70

65

60

55

50

S/N RATIO – dB

45

40

35

30

–0.5

0.0

V

G

3.0

2.52.01.51.00.5

Figure 2. S/N Ratio vs. Control Voltage Sequential Control
(1 MHz Bandwidth)

An auxiliary amplifier that senses the voltage difference
between input and output commons is provided to reject
this common voltage.

REV. D

–7–

AD600/AD602

A1

–40.00dB

–40.00dB

C1HI C1LO

V

G1

VO1 = 0.592V

–0.51dB

C1HI C1LO

V

G1

VO1 = 0.592V

0dB

C1HI C1LO

V

G1

VO1 = 0.592V

–0.51dB

0dB

41.07dB

41.07dB

41.07dB

1.07dB

(a)

40.56dB

(b)

41.07dB

(c)

= 1.25V

V

C

V

C

INPUT

0dB

= 0V

V

C

INPUT

0dB

INPUT

0dB

= 2.5V

Figure 3. AD600 Gain Control Input Calculations for Sequential Control Operation

The gains are offset (Figure 4) such that A2’s gain is increased
only after A1’s gain has reached its maximum value. Note that
for a differential input of –700 mV or less, the gain of a single
amplifier (A1 or A2) is at its minimum value of –1.07 dB; for a
differential input of +700 mV or more, the gain is at its maxi­mum value of 41.07 dB. Control inputs beyond these limits do
not affect the gain and can be tolerated without damage or
foldover in the response. See the Specifications section of this
data sheet for more details on the allowable voltage range. The
gain is now

Gain (dB) = 32 V

where V

is the applied control voltage.

C

+41.07dB

20dB

C

A1 A2

40.56dB

*

+38.93dB

(3)

*

+1.07dB

GAIN

(dB)

0 0.625 1.25 1.875 2.5
020406080–2.14 82.14

*

Figure 4. Explanation of Offset Calibration for
Sequential Control

–0.56dB

–1.07dB

0.592 1.908

VC (V)

GAIN OFFSET OF 1.07dB, OR 33.44mV

A2

–41.07dB

–42.14dB

C2HI C2LO

V

G2

VO2 = 1.908V

–1.07dB

–41.63dB

C2HI C2LO

V

G2

V

O2

–2.14dB

C2HI C2LO

V

G2

V

O2

41.07dB

41.07dB

= 1.908V

38.93dB

41.07dB

= 1.908V

OUTPUT
0dB

OUTPUT
40dB

OUTPUT
80dB

When VC is set to zero, VG1 = –0.592 V and the gain of A1 is

1.07 dB (recall that the gain of each amplifier section is 0 dB for
= 625 mV); meanwhile, VG2 = –1.908 V, so the gain of A2

V

G

is –1.07 dB. The overall gain is thus 0 dB (see Figure 3a).
When V
sets the gain of A1 to 40.56 dB, while V

= 1.25 V, VG1 = 1.25 V – 0.592 V = 0.658 V, which

C

= 1.25 V – 1.908 V =

G2

–0.658 V, which sets A2’s gain at –0.56 dB. The overall gain is
now 40 dB (see Figure 3b). When V

= 2.5 V, the gain of A1 is

C

41.07 dB and that of A2 is 38.93 dB, resulting in an overall gain

of 80 dB (see Figure 3c). This mode of operation is further
clarified by Figure 5, which is a plot of the separate gains of A1
and A2 and the overall gain versus the control voltage. Figure 6
is a plot of the gain error of the cascaded amplifiers versus the
control voltage.

Parallel Mode (Simplest Gain-Control Interface)

In this mode, the gain-control voltage is applied to both inputs
in parallel—C1HI and C2HI are connected to the control volt­age, and C1LO and C2LO are optionally connected to an offset
voltage of 0.625 V. The gain scaling is then doubled to 64 dB/V,
requiring only 1.25 V for an 80 dB change of gain. The ampli­tude of the gain ripple in this case is also doubled, as shown in
Figure 7, and the instantaneous signal-to-noise ratio at the
output of A2 decreases linearly as the gain is increased (Figure 8).

Low Ripple Mode (Minimum Gain Error)

As can be seen in Figures 6 and 7, the output ripple is periodic.
By offsetting the gains of A1 and A2 by half the period of the
ripple, or 3 dB, the residual gain errors of the two amplifiers
can be made to cancel. Figure 9 shows the much lower gain
ripple when configured in this manner. Figure 10 plots the
S/N ratio as a function of gain; it is very similar to that in the
Parallel Mode.

–8–

REV. D