ANALOG DEVICES AD5390, AD5391, AD5392 Service Manual

8-/16-Channel, 3 V/5 V, Serial Input, Single-

FEATURES

AD5390: 16-channel, 14-bit voltage output DAC AD5391: 16-channel, 12-bit voltage output DAC AD5392: 8-channel, 14-bit voltage output DAC Guaranteed monotonic INL: ±1 LSB max (AD5391)

±3 LSB max (AD5390-5/AD5392-5)

±4 LSB max (AD5390-3/AD5392-3) On-chip 1.25 V/2.5 V, 10 ppm/°C reference Temperature range: −40°C to +85°C Rail-to-rail output amplifier Power-down mode Package types:

64-lead LFCSP (9 mm × 9 mm) 52-lead LQFP (10 mm × 10 mm)

User interfaces:

Serial SPI

(featuring data readback)

C®-compatible interface

®-, QSPI™-, MICROWIRE™-, and DSP-compatible

Supply, 12-/14-Bit Voltage Output DACs

AD5390/AD5391/AD5392

INTEGRATED FUNCTIONS

Channel monitor Simultaneous output update via

Clear function to user-programmable code Amplifier boost mode to optimize slew rate User-programmable offset and gain adjust Toggle mode enables square wave generation Thermal monitor

APPLICATIONS

Instrumentation and industrial control Power amplifier control Level setting (ATE) Control systems Microelectromechanical systems (MEMs) Variable optical attenuators (VOAs) Optical transceivers (MSA 300, XFP)

FUNCTIONAL BLOCK DIAGRAM

LDAC

REFOUT/REFIN SIGNAL_GND (×2)REF_GNDDAC_GND (×2)AGND (×2)AVDD (×2)DGND (×2)DVDD (×2)

AD5390

SPI/I2C

DCEN/AD1

DIN/SDA SCLK/SCL SYNC/AD0

SDO

BUSY

CLR

RESET

MON_IN1

MON_IN2

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

INTERFACE

CONTROL

LOGIC

MACHINE

CONTROL

POWER-ON

RESET

VIN0 VIN15

MUX

MON_OUT

STATE

AND

LOGIC

INPUT

1414

REG

14 14

INPUT

1414

REG

14 14

INPUT

1414

REG

14 14

INPUT

1414

REG

14 14

m REG0

c REG0

m REG1

c REG1

m REG6

c REG6

m REG7

c REG7

Figure 1.

1.25V/2.5V

REFERENCE

DAC

1414

REG

DAC REG

LDAC

DAC 0

1414

DAC 1

1414

DAC 6

1414

DAC 7

VOUT 0

VOUT 1 VOUT 2 VOUT 3 VOUT 4 VOUT 5 VOUT 6

VOUT 7 VOUT 8

VOUT 15

www.analog.com

03773-0-001

AD5390/AD5391/AD5392

TABLE OF CONTENTS

General Description......................................................................... 3

AD5390-5/AD5391-5/AD5392-5 Specifications.......................... 4

AD5390-5/AD5391-5/AD5392-5 AC Characteristics................. 6

AD5390-3/AD5391-3/AD5392-3 Specifications.......................... 7

AD5390-3/AD5391-3/AD5392-3 AC Characteristics................. 9

Timing Characteristics: Serial SPI-, QSPI-, Microwire-, and DSP-Compatible Interface

Timing Characteristics: I2C Serial Interface................................ 13

Absolute Maximum Ratings.......................................................... 14

ESD Caution................................................................................ 14

Pin Configuraton and Function Descriptions ............................ 15

Te r m in o l o g y .................................................................................... 18

Typical Performance Characteristics........................................... 19

Functional Description ..................................................................23

DAC Architecture—General..................................................... 23

Data Decoding—AD5390/AD5392......................................... 24

Data Decoding—AD5391 .........................................................24

Interfaces ..........................................................................................25

DSP-, SPI-, and MICROWIRE-Compatible S eria l Interface 25

I2C Serial Interface.......................................................................... 27

I2C Data Transfer ........................................................................ 27

START and STOP Conditions .................................................. 27

Repeated START Condition...................................................... 27

............................................................. 10

I2C Write Operation ....................................................................... 28

4-Byte Mode................................................................................ 28

3-Byte Mode................................................................................ 29

2-Byte Mode................................................................................ 30

AD539x On-Chip Special Function Registers........................ 31

Control Register Write............................................................... 33

Hardware Functions ....................................................................... 35

Reset Function ............................................................................ 35

Asynchronous Clear Function.................................................. 35

and

BUSY

Power-On Reset .......................................................................... 35

Power-Down ............................................................................... 35

Microprocessor Interfacing....................................................... 35

Application Information................................................................ 37

Power Supply Decoupling ......................................................... 37

Typical Configuration Circuit .................................................. 37

AD539x Monitor Function ....................................................... 38

Toggle Mode Function............................................................... 38

Thermal Monitor Function....................................................... 38

Outline Dimensions....................................................................... 40

Ordering Guide .......................................................................... 41

Functions...................................................... 35

LDAC

Acknowledge Bit (ACK) ............................................................ 27

REVISION HISTORY

10/04: Data Sheet Changed from Rev. 0 to Rev. A

Changes to Features.......................................................................... 1

Changes to Table 1............................................................................ 3

Changes to Table 2............................................................................ 4

Changes to Table 3............................................................................ 6

Changes to Table 4............................................................................ 7

Changes to Figure 36...................................................................... 35

Rev. A | Page 2 of 44

Changes to Figure 37...................................................................... 36

Changes to Figure 38...................................................................... 36

Changes to Ordering Guide.......................................................... 41

4/04—Revision 0: Initial Version

AD5390/AD5391/AD5392

GENERAL DESCRIPTION

The AD5390/AD5391 are complete single-supply, 16-channel, 14-bit and 12-bit DACs, respectively. The AD5392 is a complete single-supply, 8-channel, 14-bit DAC. Devices are available both in 64-lead LFCSP and 52-lead LQFP packages. All channels have an on-chip output amplifier with rail-to-rail operation. All devices include an internal 1.25/2.5 V, 10 ppm/°C reference, an on-chip channel monitor function that multiplexes the analog outputs to a common MON_OUT pin for external monitoring, and an output amplifier boost mode that optimizes the output amplifier slew rate.

The AD5390/AD5391/AD5392 contain a 3-wire serial interface with interface speeds in excess of 30 MHz that are compatible

Table 1. Additional High Channel Count, Low Voltage, Single-Supply DACs in Portfolio

Model

AD5380BST-5 14 Bits 4.5 V to 5.5 V 40 ±4 100-Lead LQFP ST-100 AD5380BST-3 14 Bits 2.7 V to 3.6 V 40 ±4 100-Lead LQFP ST-100 AD5384BBC-5 14 Bits 4.5 V to 5.5 V 40 ±4 100-Lead CSPBGA BC-100 AD5384BBC-3 14 Bits 2.7 V to 3.6 V 40 ±4 100-Lead CSPBGA BC-100 AD5381BST-5 12 Bits 4.5 V to 5.5 V 40 ±1 100-Lead LQFP ST-100 AD5381BST-3 12 Bits 2.7 V to 3.6 V 40 ±1 100-Lead LQFP ST-100 AD5382BST-5 14 Bits 4.5 V to 5.5 V 32 ±4 100-Lead LQFP ST-100 AD5382BST-3 14 Bits 2.7 V to 3.6 V 32 ±4 100-Lead LQFP ST-100 AD5383BST-5 12 Bits 4.5 V to 5.5 V 32 ±1 100-Lead LQFP ST-100 AD5383BST-3 12 Bits 2.7 V to 3.6 V 32 ±1 100-Lead LQFP ST-100

Resolution AVD D Ra nge

Output Channels

with SPI, QSPI, MICROWIRE, and DSP interface standards

and an I

C-compatible interface supporting a 400 kHz data

transfer rate.

An input register followed by a DAC register provides doublebuffering, allowing DAC outputs to be updated independently or simultaneously using the

input. Each channel has a

LDAC

programmable gain and offset adjust register, letting the user fully calibrate any DAC channel.

Power consumption is typically 0.25 mA per channel.

Linearity Error (LSB) Package Description Package Option

Rev. A | Page 3 of 44

AD5390/AD5391/AD5392

AD5390-5/AD5391-5/AD5392-5 SPECIFICATIONS

AVDD = 4.5 V to 5.5 V; DV All specifications T

MIN

Table 2.

Parameter

ACCURACY

Resolution 14 12 Bits Relative Accuracy ±3 ±1 LSB max Differential Nonlinearity −1/+2 ±1 LSB max Guaranteed monotonic over temperature. Zero-Scale Error 4 4 mV max Offset Error ±4 ±4 mV max Measured at code 32 in the linear region. Offset Error TC ±5 ±5 µV/°C typ Gain Error ±0.024 ± 0.024 % FSR max At 25°C T

±0.06 ±0.06 % FSR max

Gain Temperature Coefficient DC Crosstalk2 0.5 0.5 LSB max

REFERENCE INPUT/OUTPUT

Reference Input2

Reference Input Voltage 2.5 2.5 V

DC Input Impedance 1 1 MΩ min Typically 100 MΩ. Input Current ±1 ±1 µA max Typically ±30 nA. Reference Range

Reference Output

Output Voltage 2.495/2.505 2.495/2.505 V min/max At ambient, optimized for 2.5 V operation.

1.22/1.28 1.22/1.28 V min/max At ambient when 1.25 V reference is selected. Reference TC ±10 ±10 ppm max Temperature range: 25°C to 85°C.

±15 ±15 ppm max Temperature range: −40°C to +85°C.

Output Impedance 2.2 2.2 kΩ typ

OUTPUT CHARACTERISTICS2

Output Voltage Range4 0/AV Short-Circuit Current 40 40 mA max Load Current ±1 ±1 mA max Capacitive Load Stability

RL = ∞ 200 200 pF max RL = 5 kΩ 1,000 1,000 pF max

DC Output Impedance 0.5 0.5 Ω max

MONITOR OUTPUT PIN

Output Impedance 500 500 Ω typ Three-State Leakage Current 100 100 nA typ LOGIC INPUTS2 DVDD = 2.7 V to 5.5 V. VIH, Input High Voltage 2 2 V min VIL, Input Low Voltage 0.8 0.8 V max Input Current ±10 ±10 µA max Total for all pins. TA = T Pin Capacitance 10 10 pF max

= 2.7 V to 5.5 V; AGND = DGND = 0 V; REFIN = 2.5 V external.

to T

, unless other wise noted.

MAX

AD5390-51 AD5392-5

2 2 ppm FSR/°C typ

1 V to

AD5391-5

1 V to AV

Unit

/2 V min/max

0/AV

V min/max

Test Conditions/Comments

to T

MAX

MIN

±1% for specified performance, AV

= 2 × REFIN + 50 mV.

Enabled via internal/external bit in control register. REF select bit in control register selects the reference voltage.

to T

MAX

MIN

Rev. A | Page 4 of 44

AD5390/AD5391/AD5392

Parameter

AD5390-51 AD5392-5

AD5391-5

Unit

Test Conditions/Comments

LOGIC INPUTS (SCL, SDA Only)

VIH, Input High Voltage 0.7 DV VIL, Input Low Voltage 0.3 DV

0.7 DV

0.3 DV

V min SMBus-compatible at DVDD < 3.6 V.

V max SMBus-compatible at DVDD < 3.6 V. IIN, Input Leakage Current ±1 ±1 µA max V

, Input Hysteresis 0.05 DV

HYST

0.05 DV

V min CIN, Input Capacitance 8 8 pF typ Glitch Rejection 50 50 ns max

Input filtering suppresses noise spikes of <50 ns.

LOGIC OUTPUTS (BUSY, SDO)2

Output Low Voltage 0.4 0.4 V max DVDD = 5 V ± 10%, sinking 200 µA. Output High Voltage DVDD − 1 DVDD − 1 V min

= 5 V ± 10%, SDO only, sourcing

200 µA. Output Low Voltage 0.4 0.4 V max DVDD = 2.7 V to 3.6 V, sinking 200 µA. Output High Voltage DVDD − 0.5 DVDD − 0.5 V min

= 2.7 V to 3.6 V SDO only, sourcing

200 µA. High Impedance Leakage Current ±1 ±1 µA max High Impedance Output

5 5 pF typ

Capacitance

LOGIC OUTPUT (SDA)2

VOL, Output Low Voltage 0.4 0.4 V max I

0.6 0.6 V max I

= 3 mA.

SINK

= 6 mA.

SINK

Three-State Leakage Current ±1 ±1 µA max Three-State Output Capacitance 8 8 pF typ

POWER REQUIREMENTS

AV DV

4.5/5.5 4.5/5.5 V min/max

2.7/5.5 2.7/5.5 V min/max Power Supply Sensitivity2 ∆Midscale/∆AVDD −85 −85 dB typ AI

0.375 0.375

0.475 0.475

mA/channel max

Outputs unloaded; boost off;

0.25 mA/channel typ. Outputs unloaded; boost on;

0.325 mA/channel typ.

1 1 mA max VIH = DVDD, VIL = DGND. AIDD (Power-Down) 1 1 µA max Typically 200 nA. DIDD (Power-Down) 20 20 µA max Typically 3 µA. Power Dissipation 35 35 mW max

20 20 mW max

AD5390/AD5391 with outputs unloaded;

= DVDD = 5 V; boost off.

AD5392 with outputs unloaded;

= DVDD = 5 V, boost off.

AD539x-5 products are calibrated with a 2.5 V reference. Temperature range for all versions: −40°C to +85°C.

Guaranteed by characterization, not production tested.

Programmable either to 1.25 V typ or 2.5 V typ via the AD539x control register. Operating the AD539x-5 products with a reference of 1.25 V leads to a degradation in

performance accuracy.

Accuracy guaranteed from VOUT = 10 mV to AVDD − 50 mV.

Rev. A | Page 5 of 44

AD5390/AD5391/AD5392

AD5390-5/AD5391-5/AD5392-5 AC CHARACTERISTICS

AVDD = 4.5 V to 5.5 V; DVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V.

Table 3. AD5390-5/AD5391-5/AD5392-5 AC Characteristics

Parameter All1 Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

Output Voltage Settling Time

AD5390/AD5392 8 µs typ ¼ scale to ¾ scale change settling to ±1 LSB.

10 µs max

AD5391 6 µs typ ¼ scale to ¾ scale change settling to ±1 LSB. 8 µs max Slew rate

3 V/µs typ Boost mode on.

2 V/µs typ Boost mode off.

Digital-to-Analog Glitch Energy 12 nV-s typ Glitch Impulse Peak Amplitude 15 mV typ Channel-to-Channel Isolation 100 dB typ See Terminology section. DAC-to-DAC Crosstalk 1 nV-s typ See Terminology section. Digital Crosstalk 0.8 nV-s typ Digital Feedthrough 0.1 nV-s typ Effect of input bus activity on DAC output under test.

Output Noise (0.1 Hz to 10 Hz)

15 40

µV p-p typ µV p-p typ

Output Noise Spectral Density

@ 1 kHz 150 nV/(Hz) @ 10 kHz 100 nV/(Hz)

Guaranteed by characterization, not production tested.

The slew rate can be adjusted via the current boost control bit in the DAC control register.

1/2

typ

1/2

typ

External reference midscale loaded to DAC. Internal reference midscale loaded to DAC.

Rev. A | Page 6 of 44

AD5390/AD5391/AD5392

AD5390-3/AD5391-3/AD5392-3 SPECIFICATIONS

AVDD = 2.7 V to 3.6 V; DVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V; REFIN = 1.25 V external. All specifications T otherwise noted.

Table 4.

Parameter

AD5390-31 AD5392-3

AD5391-3

Unit

Test Conditions/Comments

ACCURACY

Resolution 14 12 Bits Relative Accuracy ±4 ±1 LSB max Differential Nonlinearity −1/+2 ±1 LSB max Guaranteed monotonic over temperature. Zero-Scale Error 4 4 mV max Offset Error ±4 ±4 mV max Measured at code 64 in the linear region. Offset Error TC ±5 ±5 µV/°C typ Gain Error ±0.024 ±0.024 % FSR max At 25°C. ±0.1 ±0.1 % FSR max T

MIN

to T

MAX

. Gain Temperature Coefficient2 2 2 ppm FSR/°C typ DC Crosstalk 0.5 0.5 mV max

REFERENCE INPUT/OUTPUT

Reference Input

Reference Input Voltage 1.25 1.25 V ±1% for specified performance. DC Input Impedance 1 1 MΩ min Typically 100 MΩ. Input Current ±1 ±1 µA max Typically ±30 nA. Reference Range 1 V to AVDD/2 1 V to AVDD/2 V min/max

Reference Output

Enabled via internal/external bit in control register. REF select bit in control register selects the reference voltage.

Output Voltage 1.245/1.255 1.245/1.255 V min/max At ambient. Optimized for 1.25 V operation.

2.47/2.53 2.47/2.53 V min/max At ambient when 2.5 V reference is selected. Reference TC ±10 ±10 ppm max Temperature range: 25°C to 85°C.

±15 ±15 ppm max Temperature range: −40°C to +85°C.

Output Impedance 2.2 2.2 kΩ typ

OUTPUT CHARACTERISTICS2

Output Voltage Range

0/AV

V min/max Short-Circuit Current 40 40 mA max Load Current ±1 ±1 mA max Capacitive Load Stability

RL = ∞ 200 200 pF max RL = 5 kΩ 1,000 1,000 pF max

DC Output Impedance 0.5 0.5 Ω max

MONITOR OUTPUT PIN2

Output Impedance 500 500 Ω typ Three-State Leakage Current 100 100 nA typ

LOGIC INPUTS2 DV

= 2.7 V to 5.5 V.

VIH, Input High Voltage 2 2 V min VIL, Input Low Voltage 0.8 0.8 V max Input Current ±10 ±10 µA max Total for all pins. TA = T Pin Capacitance 10 10 pF max Logic Inputs (SCL, SDA Only)

VIH, Input High Voltage 0.7 DV VIL, Input Low Voltage 0.3 DV

0.7 DV

0.3 DV

V min SMBus-compatible at DVDD < 3.6 V.

V max SMBus-compatible at DVDD < 3.6 V.

IIN, Input Leakage Current ±1 ±1 µA max V

, Input Hysteresis 0.05 DV

HYST

0.05 DV

V min

MIN

to T

MAX

, unless

Rev. A | Page 7 of 44

AD5390/AD5391/AD5392

Parameter

AD5390-31 AD5392-3

AD5391-3

Unit

Test Conditions/Comments

Glitch Rejection 50 50 ns max Input filtering suppresses noise spikes <50 ns. Logic Outputs (BUSY, SDO)2

Output Low Voltage 0.4 0.4 V max DVDD = 2.7 V to 5.5 V, sinking 200 µA. Output High Voltage DVDD − 0.5 DVDD − 0.5 V min

= 2.7 V to 3.6 V, SDO only,

sourcing 200 µA.

DVDD − 0.1 DVDD − 0.1 V min

= 4.5 V to 5.5 V, SDO only,

sourcing 200 µA.

High Impedance Leakage

±1 ±1 µA max

Current High Impedance Output

5 5 pF typ

Capacitance

Logic Output (SDA)2

VOL, Output Low Voltage 0.4 0.4 V max I

0.6 0.6 V max I

= 3 mA.

SINK

= 6 mA.

SINK

Three-State Leakage Current ±1 ±1 µA max Three-State Output

8 8 pF typ

Capacitance

POWER REQUIREMENTS

AV DV

2.7/3.6 2.7/3.6 V min/max

2.7/5.5 2.7/5.5 V min/max Power Supply Sensitivity2 ∆Midscale/∆AVDD −85 −85 dB typ AI

0.375 0.375

0.475 0.475

mA/channel max

Outputs unloaded; boost off;

0.25 mA/channel typ. Outputs unloaded; boost on;

0.325 mA/channel typ.

1 1 mA max VIH = DVDD, VIL = DGND. AIDD (Power-Down) 1 1 µA max DIDD (Power-Down) 20 20 µA max Power Dissipation 21 21 mW max

AD5390/AD5391 with outputs unloaded;

= DVDD = 3 V; boost off.

12 12 mW max

AD5392 with outputs unloaded;

= DVDD = 3 V; boost off.

AD539x-3 products are calibrated with a 1.25 V reference. Temperature range for all versions: −40°C to +85°C.

Guaranteed by characterization, not production tested.

Programmable either to 1.25 V typ or 2.5 V typ via the AD539x control register. Operating the AD539x-3 products with a reference of 2.5 V leads to a degradation in

performance accuracy.

Accuracy guaranteed from VOUT = 39 mV to AVDD − 50 mV.

Rev. A | Page 8 of 44

AD5390/AD5391/AD5392

AD5390-3/AD5391-3/AD5392-3 AC CHARACTERISTICS

AVDD = 2.7 V to 3.6 V; DVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V; CL = 200 pF to AGND.

Table 5.

AD5390-3/AD5391-3/AD5392-3 AC Characteristics

Parameter All Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

Output Voltage Settling Time

AD5390/AD5392 8 µs typ ¼ scale to ¾ scale change settling to ±1 LSB.

10 µs max

AD5391 6 µs typ ¼ scale to ¾ scale change settling to ±1 LSB. 8 µs max Slew Rate

3 V/µs typ Boost mode on. 2 V/µs typ Boost mode off. Digital-to-Analog Glitch Energy 12 nV-s typ Glitch Impulse Peak Amplitude 15 mV typ Channel-to-Channel Isolation 100 dB typ See Terminology section. DAC-to-DAC Crosstalk 1 nV-s typ See Terminology section. Digital Crosstalk 0.8 nV-s typ Digital Feedthrough 0.1 nV-s typ Effect of input bus activity on DAC output under test.

OUTPUT NOISE (0.1 Hz to 10 Hz) 15 µV p-p typ External reference midscale loaded to DAC.

40 µV p-p typ Internal reference midscale loaded to DAC. Output Noise Spectral Density

@ 1 kHz 150 nV/(Hz) @ 10 kHz 100 nV/(Hz)

Guaranteed by design and characterization, not production tested.

The slew rate can be programmed via the current boost control bit in the AD539x control registers.

1/2

typ

1/2

typ

Rev. A | Page 9 of 44

AD5390/AD5391/AD5392

TIMING CHARACTERISTICS: SERIAL SPI-, QSPI-, MICROWIRE-, AND DSP-COMPATIBLE INTERFACE

DVDD = 2 V to 5.5 V; AVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V. All specifications T

Table 6. 3-Wire Serial Interface

Parameter

33 ns min

20 ns min

5 ns min

8 ns min

2, 3

Limit at T

33 ns min SCLK cycle time 13 ns min SCLK high time 13 ns min SCLK low time 13 ns min 13 ns min

10 ns min 50 ns min 5 ns min Data setup time

4.5 ns min Data hold time 30 ns max

670 ns max

20 ns min 100 ns max 0 ns min 100 ns min 8 µs typ DAC output settling time, AD5390/AD5392

6 µs typ DAC output settling time, AD5391 20 ns min 12 µs max

20 ns max SCLK rising edge to SDO valid

20 ns min

MIN

, T

MAX

Unit Description

SYNC falling edge to SCLK falling edge setup time

SCLK falling edge to SYNC falling edge

24 Minimum Minimum Minimum

SYNC low time SYNC high time SYNC high time in readback mode

SCLK falling edge to BUSY falling edge

BUSY pulse width low (single channel update)

SCLK falling edge to LDAC falling edge

24 LDAC pulse width low BUSY rising edge to DAC output response time BUSY rising edge to LDAC falling edge LDAC falling edge to DAC output response time

CLR pulse width low CLR pulse activation time

SCLK falling edge to SYNC rising edge to SCLK rising edge SYNC rising edge to LDAC falling edge

MIN

to T

, unless otherwise noted.

MAX

SYNC rising edge

Guaranteed by design and characterization, not production tested.

All input signals are specified with tr = tf = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.2 V.

See , F , and . Figure 2 igure 3 Figure 4, Figure 5

Standalone mode only.

Daisy-chain mode only.

Rev. A | Page 10 of 44

AD5390/AD5391/AD5392

SCLK

SYNC

DIN

SDO

LDAC

UNDEFINED

DB23 DB0 DB23

INPUT WORD FOR DAC N INPUT WORD FOR DAC N+1

24 48

DB23

INPUT WORD FOR DAC N

DB0

03773-0-002

Figure 2. Serial Interface Timing Diagram (Daisy-Chain Mode)

24 24

Rev. A | Page 11 of 44

AD5390/AD5391/AD5392

SCLK

SYNC

DIN

SDO

DB23

INPUT WORD SPECIFIES

UNDEFINED

DB0

DB23' DB0

NOP CONDITION

DB23 DB0

SELECTED REGISTER DATA

CLOCKED OUT

03773-0-006

Figure 4. Serial Interface Timing Diagram (Data Readback Mode)

200µA

OUTPUT

50pF

200µA

Figure 5. Load Circuit for Digital Output Timing

OH (MIN)

OL (MAX)

03773-0-003

Rev. A | Page 12 of 44

AD5390/AD5391/AD5392

TIMING CHARACTERISTICS: I2C SERIAL INTERFACE

Guaranteed by design and characterization, not production tested. DVDD = 2.7 V to 5.5 V; AVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V.

to T

All specifications T

MIN

Table 7.

Parameter

SCL

0 µs min tHD, t

0 ns min tR, rise time of SCL and SDA when receiving (CMOS-compatible) t

0 ns min tF, fall time of SDA when receiving (CMOS-compatible) 300 ns max tF, fall time of SCL and SDA when receiving 20 + 0.1 C

See F . igure 6

A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH MIN of the SCL signal)

to bridge the undefined region of SCL’s falling edge.

CB is the total capacitance of one bus line in pF; tR and tF measured between 0.3 DVDD and 0.7 DVDD.

, unless other wise noted.

MAX

Limit at T

MIN

, T

MAX

Unit Description

400 kHz max SCL clock frequency

2.5 µs min SCL cycle time

0.6 µs min t

1.3 µs min t

0.6 µs min tHD, 100 ns min tSU,

0.9 µs max tHD,

0.6 µs min tSU,

1.3 µs min t

, SCL high time

HIGH

, SCL low time

LOW

, start/repeated start condition hold time

STA

, data setup time

DAT

data hold time

DAT

data hold time

DAT

setup time for repeated start

STA

stop condition setup time

STO

, bus free time between a stop and a start condition

BUF

300 ns max tF, fall time of SDA when transmitting

ns min tF, fall time of SCL and SDA when transmitting

400 pF max Capacitive load for each bus line

SCL

START

CONDITION

Figure 6. I

C Interface Timing Diagram

REPEATED

START

CONDITION

STOP

CONDITION

03773-0-007

Rev. A | Page 13 of 44

AD5390/AD5391/AD5392

ABSOLUTE MAXIMUM RATINGS

Transient currents of up to 100 mA do not cause SCR latch-up.

= 25°C, unless otherwise noted.

Table 8.

Parameter Rating

AVDD to AGND −0.3 V to +7 V DVDD to DGND −0.3 V to +7 V Digital Inputs to DGND −0.3 V to DVDD + 0.3 V Digital Outputs to DGND −0.3 V to DVDD + 0.3 V VREF to AGND −0.3 V to +7 V REFOUT to AGND −0.3 V to +7 V AGND to DGND −0.3 V to +0.3 V VOUTX to AGND −0.3 V to AVDD + 0.3 V Operating Temperature Range

Commercial (B Version) −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature (TJ max) 150°C

64-Lead LFCSP Package, θ

52-lLad LQFP Package, θ Reflow Soldering Peak

Temperature

22°C/W 38°C/W 230°C

Stresses above absolute maximum ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. A | Page 14 of 44

AD5390/AD5391/AD5392

PIN CONFIGURATON AND FUNCTION DESCRIPTIONS

NC NC NC NC NC NC

REF_GND REFOUT/REFIN SIGNAL_GND 1

DAC_GND 1

VOUT 0 VOUT 1 VOUT 2 VOUT 3 VOUT 4

NC = NO CONNECT

Figure 7. AD5390/AD5391 LFCSP Pin Configuration

NC NC NC NC NC NC

REF_GND

REFOUT/REFIN

IGNAL_GND 1

DAC_GND 1

NC = NO CONNECT

VOUT 0 VOUT 1 VOUT 2 VOUT 3 VOUT 4

SDO

DVDDDGND

DGND

AD5390/ AD5391

TOP VIEW

VOUT 7 22

MON_IN 1 23

MON_IN 2 24

MON_OUT 25

SDO

DVDDDGND

DGND

AD5392

TOP VIEW

VOUT 7 22

MON_IN 1 23

MON_IN 2 24

MON_OUT 25

DGNDPDDCEN/AD1

54 DV

55 DV

VOUT 8 26

VOUT 9 27

VOUT 10 28

DGNDPDDCEN/AD1

55 DV

54 DV

NC 26

NC 27

NC 28

SPI/I

VOUT 11 29

SPI/I

NC 29

VOUT 12 30

NC 30

DAC_GND 2 31

SYNC/AD0

DGND

SCLK/SCL

DIN/SDA

CLR 64636261605958575653525150

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

PIN 1 INDICATOR

(Not to Scale)

NC 18

NC 19

VOUT 5 20

VOUT 6 21

AGND 1 17

SYNC/AD0

DGND

SCLK/SCL

DIN/SDA

CLR 64636261605958575653525150

PIN 1 INDICATOR

(Not to Scale)

NC 18

NC 19

VOUT 5 20

VOUT 6 21

AGND 1 17

Figure 8. AD5392 LFCSP Pin Configuration

DAC_GND 2 31

LDAC 49

SIGNAL_GND 2 32

LDAC 49

SIGNAL_GND 2 32

48 NC 47 BUSY 46 RESET 45 NC 44 NC 43 NC 42 NC 41 NC 40 NC 39 NC 38 NC 37 AV

36 AGND 2 35 VOUT 15 34 VOUT 14 33 VOUT 13

48 NC 47 BUSY 46 RESET 45 NC 44 NC 43 NC 42 NC 41 NC 40 NC 39 NC 38 NC 37 NC 36 NC 35 NC 34 NC 33 NC

03773-0-008

03773-0-009

CLR

NC NC

REF_GND REFOUT/REFIN SIGNAL_GND 1

DAC_GND 1

VOUT 0 VOUT 1 VOUT 2 VOUT 3 VOUT 4

NC = NO CONNECT

Figure 9. AD5390/AD5391 LQFP Pin Configuration

CLR

NC NC

REF_GND REFOUT/REFIN SIGNAL_GND 1

DAC_GND 1

NC = NO CONNECT

VOUT 0 VOUT 1 VOUT 2 VOUT 3 VOUT 4

SYNC/AD0

DGND

DIN/SDA

SCLK/SCL

SDO

DVDDDGND

AD5390/

AD5391

TOP VIEW

MON_IN 1

MON_IN 2

MON_OUT

SDO

DVDDDGND

AD5392

TOP VIEW

MON_IN 1

MON_IN 2

MON_OUT

DVDDDVDDDGND

VOUT 8

DVDDDVDDDGND

NCNCNCNCNC

52 51 50 49 48 43 42 41 4047 46 45 44

1 2

PIN 1

INDICATOR

4 5 6 7 8

9 10 11 12 13

14 15 16 17 18 19 20 21 22 23 24 25 26

AGND 1

DGND

52 51 50 49 48 43 42 41 4047 46 45 44

1 2 3 4 5 6 7 8

9 10 11 12 13

14 15 16 17 18 19 20 21 22 23 24 25 26

AGND 1

VOUT 5

VOUT 6

VOUT 7

SYNC/AD0

DIN/SDA

SCLK/SCL

PIN 1 INDICATOR

(Not to Scale)

VOUT 5

VOUT 6

VOUT 7

(Not to Scale)

SPI/I

VOUT 9

VOUT 10

VOUT 11

VOUT 12

SPI/I

Figure 10. AD5392 LQFP Pin Configuration

DCEN/AD1

39 38 37 36 35 34 33 32 31 30 29 28 27

DAC_GND 2

DCEN/AD1

LDAC

BUSY

RESET

SIGNAL_GND 2

DAC_GND 2

LDAC BUSY RESET NC NC NC NC AV

AGND 2 VOUT 15 VOUT 14 VOUT 13 SIGNAL_GND 2

03773-0-011

03773-0-010

Rev. A | Page 15 of 44

AD5390/AD5391/AD5392

Table 9. Pin Function Descriptions

Mnemonic Function

VOUTX

SIGNAL_GND (1,

2) DAC_GND (1, 2)

AGND (1, 2)

AVDD (1, 2)

DGND Ground for All Digital Circuitry. DV

REF_GND Ground Reference Point for the Internal Reference. Connect to AGND. REFOUT/REFIN

MON_OUT

MON_IN (1, 2)

SYNC/AD0 Serial Interface Pin.This is the frame synchronization input signal for the serial interface. When taken low, the internal

DCEN/AD1

SDO

BUSY Digital CMOS Output. BUSY goes low during internal calculations of the data (x2) loaded to the DAC data register. During

LDAC Load DAC Logic Input (active low). If LDAC is taken low while BUSY is inactive (high), the contents of the input registers

CLR Asynchronous Clear Input. The CLR input is falling edge sensitive. While CLR is low, all LDAC pulses are ignored. When

RESET Asynchronous Digital Reset Input (falling edge sensitive). The function of this pin is equivalent to that of the power-on

Buffered Analog Outputs for Channel X. Each analog output is driven by a rail-to-rail output amplifier operating at a gain of 2. Each output is capable of driving an output load of 5 kΩ to ground. Typical output impedance is 0.5 Ω.

Analog Ground Reference Points for each group of eight output channels. All SIGNAL_GND pins are tied together internally and should be connected to the AGND plane as close as possible to the AD539x.

Each group of eight channels contains a DAC_GND pin. This is the ground reference point for the internal 14-bit DACs. These pins should be connected to the AGND plane.

Analog Ground Reference Point. Each group of eight channels contains an AGND pin. All AGND pins should be connected externally to the AGND plane.

Analog Supply Pins. Each group of eight channels has a separate AV ceramic capacitors and 10 µF tantalum capacitors. Operating range is 5 V ± 10%.

Logic Power Supply. Guaranteed operating range is 2.7 V to 5.5 V. Recommended that these pins be decoupled with

0.1 µF ceramic capacitors and 10 µF tantalum capacitors to DGND.

The AD539x contains a common REFOUT/REFIN pin. When the internal reference is selected, this pin is the reference output. If the application necessitates the use of an external reference, it can be applied to this pin and the internal reference disabled via the control register. The default for this pin is a reference input.

Analog Output Pin. When the monitor function is enabled on the AD5390/AD5391, the MON_OUT acts as the output of a 16-to-1 channel multiplexer, which can be programmed to multiplex any channel output to the MON_OUT pin. When the monitor function is enabled on the AD5392, the MON_OUT acts as the output of an 8-to-1 channel multiplexer that can be programmed to multiplex any channel output to the MON_OUT pin. The MON_OUT pin output impedance is typically 500 Ω and is intended to drive a high input impedance such as that exhibited by SAR ADC inputs.

Monitor Input Pins. The AD539x contains two monitor input pins to which the user can connect input signals (within the maximum ratings of the device) for monitoring purposes. Any of the signals applied to the MON_IN pins along with the output channels can be switched to the MON_OUT pin via software. An external ADC, for example, can be used to monitor these signals.

counter is enabled to count the required number of clocks before the addressed register is updated.

In I

C mode, AD0 acts as a hardware address pin.

Interface Control Pin. Operation is determined by the interface select bit SPI/ Serial Interface Mode: Daisy-Chain Select Input (level-sensitive, active high). When high, this pin enables daisy-chain

operation to allow a number of devices to be cascaded together. I2C Mode: This pin acts as a hardware address pin used in conjunction with AD0 to determine the software address for this device on the I

Serial Data Output. Three-statable CMOS output. SDO can be used for daisy-chaining a number of devices together. Data is clocked out on SDO on the rising edge of SCLK and is valid on the falling edge of SCLK.

this time, the user can continue writing new data to further the x1, c, and m registers (these are stored in a FIFO), but no further updates to the DAC registers and DAC outputs can take place. If

BUSY also goes low during power-on reset and when the RESET pin is low. During this time the interface is

stored. disabled and any events on

are transferred to the DAC registers and the DAC outputs are updated. If internal calculations are taking place, the inactive. However, any events on

CLR is activated, all channels are updated with the data contained in the CLR code register. BUSY is low for a duration of 20 µs (AD5390/91) and 15 µs (AD5392) while all channels are being updated with the

reset generator. When this pin is taken low, the state machine initiates a reset sequence to digitally reset the x1, m, c, and x2 registers to their default power-on values. This sequence takes 270 µs max. This falling edge of RESET process and interfaces are disabled and all and the status of the RESET pin is ignored until the next falling edge is detected.

C bus.

LDAC are ignored. A CLR operation also brings BUSY low.

LDAC event is stored and the DAC registers are updated when BUSY goes

LDAC during power-on reset or RESET are ignored.

BUSY goes low for the duration, returning high when RESET is complete. While BUSY is low, all

LDAC pulses are ignored. When BUSY returns high, the part resumes normal operation

pin. These pins should be decoupled with 0.1 uF

I2C.

LDAC is taken low while BUSY is low this event is

LDAC is taken low while BUSY is active and

CLR code.

RESET initiates the

Rev. A | Page 16 of 44

AD5390/AD5391/AD5392

Mnemonic Function

SPI/I2C SCLK/SCL

DIN/SDA Interface Data Input Pin.

Power-Down (level-sensitive, active high). Used to place the device in low power mode, in which the device consumes 1 µA analog current and 20 µA digital current. In power-down mode, all internal analog circuitry is placed in low power mode; the analog output is configured as high impedance outputs or provides a 100 kΩ load to ground, depending on how the power-down mode is configured. The serial interface remains active during power-down.

Interface Select Input Pin. When this input is low, I2C mode is selected. When this input is high, SPI mode is selected. Interface CLOCK Input Pin. In SPI-compatible serial interface mode, this pin acts as a serial clock input. It operates at

clock speeds up to 50 MHz.

C mode: In I2C mode, this pin performs the SCL function, clocking data into the device. Data transfer rate in I2C mode is

I compatible with both 100 kHz and 400 kHz operating modes.

SPI/I2C = 1: This pin acts as the serial data input. Data must be valid on the falling edge of SCLK.

I2C = 0, I2C mode: In I2C mode, this pin is the serial data pin (SDA) operating as an open drain input/output.

SPI/

Rev. A | Page 17 of 44

AD5390/AD5391/AD5392

TERMINOLOGY

Relative Accuracy

Relative accuracy or endpoint linearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero-scale error and full-scale error and is expressed in least significant bits (LSBs).

Differential Nonlinearity

Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity.

Zero-Scale Error

Zero-scale error is the error in the DAC output voltage when all 0s are loaded into the DAC register. Ideally, with all 0s loaded to the DAC and m = all 1s, c = 2

n−1

, VOUT

(Zero Scale)

= 0 V.

Output Voltage Settling Time

This is the amount of time it takes for the output of a DAC to settle to a specified level for a 1/4 to 3/4 full-scale input change and measured from the rising edge of

BUSY

Digital-to-Analog Glitch Energy

This is the amount of energy injected into the analog output at the major code transition. It is specified as the area of the glitch in nV-s. It is measured by toggling the DAC register data between 0x1FFF and 0x2000.

DAC-to-DAC C rosstalk

DAC-to-DAC crosstalk is defined as the glitch impulse that appears at the output of one DAC due to both the digital change and subsequent analog output change at another DAC. The victim channel is loaded with midscale, and DAC-to-DAC crosstalk is specified in nV-s.

Zero-scale error is a measure of the difference between VOUT (actual) and VOUT (ideal) expressed in mV. It is mainly caused by offsets in the output amplifier.

Offset Error

Offset error is a measure of the difference between VOUT (actual) and VOUT (ideal) expressed in mV in the linear region of the transfer function. Offset error is measured on the AD539x-5 with code 32 loaded in the DAC register and with code 64 loaded in the DAC register on the AD539x-3.

Gain Error

Gain error is specified in the linear region of the output range between V

= 10 mV and V

OUT

= AVDD − 50 mV. It is the

OUT

deviation in slope of the DAC transfer characteristic from ideal and is expressed in % FSR with the DAC output unloaded.

DC Crosstalk

This is the dc change in the output level of one DAC at midscale in response to a full-scale code (all 0s to all 1s and vice versa) and the output change of all other DACs. It is expressed in LSBs.

DC Output Impedance

This is the effective output source resistance. It is dominated by package lead resistance.

Digital Crosstalk

The glitch impulse transferred to the output of one converter due to a change in the DAC register code of another converter is defined as the digital crosstalk and is specified in nV-s.

Digital Feedthrough

When the device is not selected, high frequency logic activity on the device’s digital inputs can be capacitively coupled both across and through the device to show up as noise on the VOUT pins. It can also be coupled along the supply and ground lines. This noise is digital feedthrough.

Output Noise Spectral Density

This is a measure of internally generated random noise. Random noise is characterized as a spectral density (voltage per √Hz). It is measured by loading all DACs to midscale and

1/2

measuring noise at the output. It is measured in nV/(Hz)

a 1 Hz bandwidth at 10 kHz.

Rev. A | Page 18 of 44

AD5390/AD5391/AD5392

TYPICAL PERFORMANCE CHARACTERISTICS

2.0

1.5

1.0

0.5

–0.5

INL ERROR (LSB)

–1.0

–1.5

–2.0

INPUT CODE

AVDD = DVDD = 5.5V VREF = 2.5V

= 25°C

163840 4096 8192 12288

03773-0-040

Figure 11. AD5390-5/AD5392-5 Typical INL Plot

2.0

1.5

1.0

0.5

–0.5

INL ERROR (LSB)

–1.0

–1.5

–2.0

INPUT CODE

AVDD = DVDD = 3V VREF = 1.25V TA = 25°C

163840 4096 8192 12288

03773-0-041

1.00

0.75

0.50

0.25

–0.25

INL ERROR (LSB)

–0.50

–0.75

–1.00

0 512 1024 1536 2048 2560 3072 3584 4096

INPUT CODE

Figure 14. Typical AD5391-5 INL Plot

1.00

0.75

0.50

0.25

–0.25

INL ERROR (LSB)

–0.50

–0.75

–1.00

0 512 1024 1536 2048 2560 3072 3584 4096

INPUT CODE

03773-0-043

03773-0-044

Figure 12. AD5390-3/AD5392-5 INL Plot

NUMBER OF UNITS

–2–1012

INL ERROR DISTRIBUTION (LSB)

AV REFIN = 2.5V T

Figure 13. AD5390/AD5392 INL Histogram Plot

= 25°C

= 5.5V

03773-0-042

Rev. A | Page 19 of 44

Figure 15. Typical AD5391-3 INL Plot

AVDD = 5V REFOUT = 2.5V TEMP. RANGE = 25°C TO 85°C

SAMPLE SIZE = 162

FREQUENCY

0 –5.0

–4.0

–1.0 3.0–3.0 1.00 4.0 5.0

–2.0 2.0

–1.5 2.5–3.5–4.5

REFERENCE DRIFT (ppm/°C)

0.5–0.5 3.5–2.5 1.5

Figure 16. AD539x REFOUT Temperature Coefficient

4.5

03773-0-045

AD5390/AD5391/AD5392

BUSY

AVDD = DVDD = 5V VREF = 2.5V

= 25°C

EXITS SOFT PD TO MIDSCALE

VOUT

Figure 17. AD539x 14ETEMC /InlineShape

03773-0-046

Rev. A | Page 20 of 44

AD5390/AD5391/AD5392

1.254

1.253

1.252

1.251

1.250

1.249

1.248

AMPLITUDE (V)

1.247

1.246

1.245

AVDD = DVDD = 3V VREF = 1.25V T

= 25°C

14ns/SAMPLE NUMBER 1 LSB CHANGE AROUND MIDSCALE GLITCH IMPULSE = 5nV-s

SAMPLE NUMBER

Figure 23. AD539x-3 Glitch Impulse

NUMBER OF UNITS

5500 100 150 200 250 30050 350 400 500450

03773-0-052

0.4 0.5 0.6 0.7 0.8 0.9 DIDD (mA)

Figure 26. AD539x DIDD Histogram

DVDD = 5.5V VIH = DV

VIL = DGND T

= 25°C

03773-0-055

Figure 24. AD539x Slew Rate Boost O ff

AVDD = DVDD = 5V VREF = 2.5V

= 25°C

VOUT

AVDD = DVDD = 5V VREF = 2.5V

= 25°C

VOUT

03773-0-053

03773-0-054

2.456

2.455

2.454

2.453

2.452

AMPLITUDE (V)

2.451

2.450

2.449

OUTPUT NOISE (nV/ Hz)

SAMPLE NUMBER

Figure 27. AD539x Adjacent Channel Crosstalk

600

500

400

300

200

100

REFOUT = 1.25V

REFOUT = 2.5V

FREQUENCY (Hz)

AVDD = DVDD = 5V VREF = 2.5V T

= 25°C

14ns/SAMPLE NUMBER

AVDD = 5V T

= 25°C

REFOUT DECOUPLED WITH 100nF CAPACITOR

5500 100 150 200 250 30050 350 400 500450

03773-0-056

100k100 1k 10k

03773-0-057

Figure 25. AD539x Slew Rate Boost On

Figure 28. AD539x REFOUT Noise Spectral Density

Rev. A | Page 21 of 44

AD5390/AD5391/AD5392

AVDD = DVDD = 5V TA = 25°C DAC LOADED WITH MIDSCALE EXTERNAL REFERENCE Y AXIS = 5µV/DIV X AXIS = 100ms/DIV

Figure 29. 0.1 Hz to 10 Hz Output Noise Plot

AVDD = DVDD= 3V VREF = 1.25V

= 25°C

03773-0-058

MIDSCALE

VOUT (V)

–1

–40 –20 –10 –5 –2 0 2 5 10 20 40

Figure 30. AD539x-3 Source and Sink Current Capability

3/4 SCALE

ZERO SCALE

1/4 SCALE

CURRENT (mA)

FULL SCALE

03773-0-059

Rev. A | Page 22 of 44

AD5390/AD5391/AD5392

(

)

FUNCTIONAL DESCRIPTION

DAC ARCHITECTURE—GENERAL

The AD5390/AD5391 are complete single-supply, 16-channel, voltage output DACs offering a resolution of 14 bits and 12 bits, respectively. The AD5392 is a complete single-supply, 8-channel, voltage output DAC offering 14-bit resolution. All devices are available in 64-lead LFCSP and 52-lead LQFP packages and feature serial interfaces. This family includes an internal selectable 1.25 V/2.5 V, 10 ppm/°C reference that can be used to drive the buffered reference inputs (alternatively, an external reference can be used to drive these inputs). All channels have an onchip output amplifier with rail-to-rail output capable of driving a 5 kΩ in parallel with a 200 pF load.

The architecture of a single DAC channel consists of a 12-bit and 14-bit resistor-string DAC followed by an output buffer amplifier operating at a gain of 2. This resistor-string architecture guarantees DAC monotonicity. The 12-bit and 14-bit binary digital code loaded to the DAC register deter-mines at what node on the string the voltage is tapped off before being fed to the output amplifier. Each channel on these devices contains independent offset and gain control registers, allowing the user to digitally trim offset and gain.

VREF

AVDD

The digital input transfer function for each DAC can be represented as

−

)

212/)2(2

−+×+=

cxmx

where:

x2 is the data-word loaded to the resistor-string DAC.

x1 is the 12-bit and 14-bit data-word written to the DAC input

m is the 12-bit and 14-bit gain coefficient (default is all 0x3FFE on the AD5390/AD5392 and 0xFFE on the AD5391). The LSB of the gain coefficient is zero.

n = DAC resolution (n = 14 for the AD5390/AD5392 and n = 12 for the AD5391).

c is the 12-bit and 14-bit offset coefficient (default is 0x2000 on

the AD5390/AD5392 and 0x800 on the AD5391).

The complete transfer function for these devices can be represented as

xVREFVOUT 2/22 ××=

x1 INPUT

INPUT

DATA

REG

m REG

c REG

Figure 31. AD5390/92 Single-Channel Architecture

DAC

REG

14-BIT DAC

VOUT

03773-0-018

These registers let the user calibrate out errors in the complete signal chain including the DAC using the internal m and c registers, which hold the correction factors. All channels are double-buffered, allowing synchronous updating of all channels using the

pin. Figure 31 shows a block diagram of a

LDAC

single channel on the AD5390/AD5391/AD5392.

where:

x2 is the data-word loaded to the resistor-string DAC.

is the reference voltage applied to the REFIN/REFOUT pin

REF

on the DAC when an external reference is used, 2.5 V for specified performance on the AD539x-5 products and 1.25 V on the AD539x-3 products.

Rev. A | Page 23 of 44

AD5390/AD5391/AD5392

DATA DECODING—AD5390/AD5392

The AD5390/AD5392 contain an internal 14-bit data bus. The input data is decoded depending on the data loaded to the REG1 and REG0 bits of the input serial register. This is shown in Table 10.

Data from the serial input register is loaded into the addressed DAC input register, offset (c) register, or gain (m) register. The format data, and the offset (c) and gain (m) register contents are shown in Table 11 to Table 13.

Table 10. Register Selection

REG1 REG0 Register Selected 1 1 Input data register (x1) 1 0 Offset register (c) 0 1 Gain register (m) 0 0 Special function registers (SFRs)

Table 11. AD5390/AD5392 DAC Data Format (REG1 = 1, REG0 = 1)

DB13 to DB0 DAC Output (V)

11 1111 1111 1111 2 V 11 1111 1111 1110 2 V 10 0000 0000 0001 2 V 10 0000 0000 0000 2 V 01 1111 1111 1111 2 V 00 0000 0000 0001 2 V 00 0000 0000 0000 0

Table 12. AD5390/AD5392 Offset Data Format (REG1 = 1, REG0 = 0)

DB13 to DB0 Offset (LSB)

111111 1111 1111 +8192 111111 1111 1110 +8191 100000 0000 0001 +1 100000 0000 0000 +0 011111 1111 1111 –1 000000 0000 0001 –8191 000000 0000 0000 –8192

Table 13. AD5390/AD5392 Gain Data Format (REG1 = 0, REG0 = 1)

DB13 to DB0 Gain Factor

11 1111 1111 1110 1 10 1111 1111 1110 0.75 01 1111 1111 1110 0.5 00 1111 1111 1110 0.25 00 0000 0000 0000 0

× (16383/16384)

REF

× (16382/16384)

REF

× (8193/16384)

REF

× (8192/16384)

REF

× (8191/16384)

REF

× (1/16384)V

REF

DATA DECODING—AD5391

The AD5391contains an internal 12-bit data bus. The input data is decoded depending on the value loaded to the REG1 and REG0 bits of the input serial register. The input data from the serial input register is loaded into the addressed DAC input register, offset (c) register, or gain (m) register. The format data and the offset (c) and gain (m) register contents are shown in Table 14 to Table 16.

Table 14. AD5391 DAC Data Format (REG1 = 1, REG0 = 1)

DB11 to DB0 DAC Output (V)

1111 1111 1111 2 V 1111 1111 1110 2 V 1000 0000 0001 2 V 1000 0000 0000 2 V 0111 1111 1111 2 V 0000 0000 0001 2 V 0000 0000 0000 0

Table 15. AD5391 Offset Data Format (REG1 = 1, REG0 = 0)

DB11 to DB0 Offset (LSB)

1111 1111 1111 +2048 1111 1111 1110 +2047 1000 0000 0001 +1 1000 0000 0000 +0 0111 1111 1111 –1 0000 0000 0001 –2047 0000 0000 0000 –2048

Table 16. AD5391 Gain Data Format (REG1 = 0, REG0 = 1)

DB11 to DB0 Gain Factor

1111 1111 1110 1 1011 1111 1110 0.75 0111 1111 1110 0.5 0011 1111 1110 0.25 0000 0000 0000 0

× (4095/4096)

REF

× (4094/4096)

REF

× (2049/4096)

REF

× (2048/4096)

REF

× (2047/4096)

REF

× (1/4096)

REF

Rev. A | Page 24 of 44

AD5390/AD5391/AD5392

INTERFACES

The AD5390/AD5391/AD5392 contain a serial interface that can be programmed to be either DSP-, SPI-, and MICROWIREcompatible, or I

C-compatible. The SPI/

pin is used to select

I2C

the interface mode.

To minimize both the power consumption of the device and the on-chip digital noise, the interface powers up fully only when the device is being written to—that is, on the falling

SYNC

edge of

DSP-, SPI-, AND MICROWIRE-COMPATIBLE SERIAL INTERFACE

The serial interface can be operated with a minimum of three wires in standalone mode or four wires in daisy-chain mode. Daisy-chaining allows many devices to be cascaded together to increase system channel count. The SPI/

Table 18. AD5390 16-Channel, 14-Bit DAC Serial Input Register Configuration

MSB LSB

pin is tied to a

I2C

Logic 1 pin to configure this mode of operation. The serial interface control pins are described in Table 17.

Table 17. Serial Interface Control Pins

Pin Description

SYNC, DIN, SCLK DCEN

SDO Data out pin for daisy-chain mode.

Standard 3-wire interface pins. Selects standalone mode or daisy-chain

mode.

Figure 2 to Figure 4 show timing diagrams for a serial write to the AD5390/AD5391/AD5392 in both standalone and daisychain mode. The 24-bit data-word format for the serial interface is shown in Table 18 to Table 20. Descriptions of the bits follow in Table 21.

/B R/

0 0 A3 A2 A1 A0 REG1 REG0 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Table 19. AD5391 16-Channel, 12-Bit DAC Serial Input Register Configuration

MSB LSB

/B R/

0 0 A3 A2 A1 A0 REG1 REG0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X X

Table 20. AD5392 8-Channel, 14-Bit DAC Serial Input Register Configuration

MSB

/B R/

0 0 0 A2 A1 A0 REG1 REG0 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

LSB

Table 21. Serial Input Register Configuration Bit Descriptions

Bit Description

A/B When toggle mode is enabled, this bit selects whether the data write is to the A or B register. With toggle mode

disabled, this bit should be set to zero to select the A data register. R/W A3 to A0 Used to address the input channels. REG1 and REG0 Select the register to which data is written, as outlined in Table 10. DB13 to DB0 Contain the input data-word. X Don’t care condition.

The read or write control bit.

Rev. A | Page 25 of 44

AD5390/AD5391/AD5392

Standalone Mode

By connecting the daisy-chain enable (DCEN) pin low, standalone mode is enabled. The serial interface works with both a continuous and a noncontinuous serial clock. The first falling edge of

starts the write cycle and resets a counter

SYNC

that counts the number of serial clocks to ensure that the correct number of bits is shifted into the serial shift register. Any further edges on

except for a falling edge are

SYNC

ignored until 24 bits are clocked in. Once 24 bits have been shifted in, the SCLK is ignored. For another serial transfer to take place, the counter must be reset by the falling edge of

SYNC

Daisy-Chain Mode

For systems that contain several devices, the SDO pin can be used to daisy-chain the devices together. This daisy-chain mode can be useful in system diagnostics and for reducing the number of serial interface lines.

By connecting the DCEN pin high, daisy-chain mode is enabled. The first falling edge of

starts the write cycle.

SYNC The SCLK is continuously applied to the input shift register when

is low. If more than 24 clock pulses are applied,

SYNC the data ripples out of the shift register and appears on the SDO line. This data is clocked out on the rising edge of SCLK and is valid on the falling edge. By connecting the SDO of the first device to the DIN input on the next device in the chain, a multidevice interface is constructed. For each device in the system, 24 clock pulses are required. Therefore, the total number of clock cycles must equal 24N where N is the total

number of AD539x devices in the chain.

When the serial transfer to all devices is complete,

SYNC

taken high. This latches the input data in each device in the daisy chain and prevents any further data from being clocked into the input shift register.

is taken high before 24 clocks are clocked into the part,

SYNC

it is considered a bad frame and the data is discarded.

The serial clock can be either a continuous or a gated clock. A continuous SCLK source can be used only if the

SYNC

can be

held low for the correct number of clock cycles. In gated clock mode, a burst clock containing the exact number of clock cycles must be used and

taken high after the final clock to latch

SYNC

the data.

Readback Mode

Readback mode is invoked by setting the R/W bit = 1 in the serial input register write sequence. With R/

= 1, Bits A3 to A0

in association with Bits REG1 and REG0 select the register to be read. The remaining data bits in the write sequence are don’t care bits. During the next SPI write, the data appearing on the SDO output contains the data from the previously addressed register. For a read of a single register, the NOP command can be used in clocking out the data from the selected register on SDO.

The readback diagram in Figure 32 shows the readback sequence. For example, to read back the m register of Channel 0 on the AD539x, the following sequence should be implemented. First, write 0x404XXX to the AD539x input register. This configures the AD539x for read mode with the m register of Channel 0 selected. Note that all Data Bits DB13 to DB0 are don’t care bits. Follow this with a second write, a NOP condition, and 0x000000. During this write, the data from the m register is clocked out on the DOUT line—that is, data clocked out contains the data from the m register in Bits DB13 to DB0, and the top 10 bits contain the address information as previously written. In readback mode, the

SYNC

signal must

frame the data. Data is clocked out on the rising edge of SCLK and is valid on the falling edge of the SCLK signal. If the SCLK idles high between the write and read operations of a readback, then the first bit of data is clocked out on the falling edge of

SYNC

SCLK

SYNC

DIN

SDO

24 48

DB23 DB0 DB0DB23

UNDEFINED SELECTED REGISTER DATA CLOCKED OUT

Figure 32. AD539x Readback Operation

Rev. A | Page 26 of 44

NOP CONDITIONINPUT WORD SPECIFIES REGISTER TO BE READ

03773-0-022

AD5390/AD5391/AD5392

I2C SERIAL INTERFACE

The AD5390/AD5391/AD5392 products feature an I2Ccompatible 2-wire interface consisting of a serial data line (SDA) and a serial clock line (SCL). SDA and SCL facilitate communication between the DACs and the master at rates up to 400 kHz. Figure 4 shows the 2-wire interface timing diagram.

When selecting the I

pin to Logic 0, the device is connected to the I2C bus

SPI/

I2C

as a slave device (that is, no clock is generated by the device). The AD5390/AD5391/AD5392 have a 7-bit slave address 1010 1(AD1)(AD0). The five MSBs are hard-coded and the two LSBs are determined by the state of the AD1 and AD0 pins. The hardware configuration facility for the AD1 and AD0 pins allows four of these devices to be configured on the bus.

C operating mode by configuring the

I2C DATA TRANSFER

One data bit is transferred during each SCL clock cycle. The data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA while SCL is high are control signals that configure START and STOP Conditions. Both SDA and SCL are pulled high by the external pull-up resistors when

C bus is not busy.

the I

START AND STOP CONDITIONS

A master device initiates communication by issuing a START condition. A START condition is a high-to-low transition on SDA with SCL high. A STOP condition is a low-to-high transition on SDA, while SCL is high. A START condition from the master signals the beginning of a transmission to the AD539x. The STOP condition frees the bus. If a repeated START condition (Sr) is generated instead of a STOP condition, the bus remains active.

REPEATED START CONDITION

A repeated START (Sr) condition may indicate a change of data direction on the bus. Sr may be used when the bus master is writing to several I control of the bus.

C devices and does not want to relinquish

ACKNOWLEDGE BIT (ACK)

The acknowledge bit (ACK) is the ninth bit attached to any 8-bit data-word. An ACK is always generated by the receiving device. The AD539x devices generate an ACK when receiving an address or data by pulling SDA low during the ninth clock period.

Monitoring the ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master should reattempt communication.

AD539x SLAVE ADDRESSES

A bus master initiates communication with a slave device by issuing a START condition followed by the 7-bit slave address. When idle, the AD539x device waits for a START condition followed by its slave address. The LSB of the address word is the read/write (R/

only, and R/

receiving the proper address 1010 1(AD1) (AD0), the AD539x issues an ACK by pulling SDA low for one clock cycle. The AD539x has four user-programmable addresses determined by the AD1 and AD0 bits.

) bit. The AD539x devices are receive devices

= 0 when communicating with them. After

Rev. A | Page 27 of 44

AD5390/AD5391/AD5392

I2C WRITE OPERATION

There are three specific modes in which data can be written to the AD539x family of DACs.

4-BYTE MODE

When writing to the AD539x DACs, begin with an address byte (R/W = 0), after which the DAC acknowledges that it is prepared to receive data by pulling SDA low. The address byte is followed by the pointer byte; this addresses the specific channel

SCL

in the DAC to be addressed and is also acknowledged by the DAC. Address Bits A3 to A0 address all channels on the AD5390/AD5391. Address Bits A2 to A0 address all channels on the AD5392. Address Bit A3 is a zero on the AD5392. Two bytes of data then are written to the DAC, as shown in Figure 33. A STOP condition follows. This lets the user update a single channel within the AD539x at any time and requires four bytes of data to be transferred from the master.

SDA

SCL

SDA

START

CONDITION

MASTER

10 0

ADDRESS BYTE POINTER BYTE

REG0 MSB MSBLSB LSBREG1

MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE

AD1 AD0 R/W

CONVERTER

0 0 0 0 A3 A2 A1 A0

MSB

ACK

Figure 33. The 4-Byte Mode I2C Write Operation

ACK

CONVERTER

ACK

CONVERTER

STOP

CONDITION

MASTER

03773-0-023

Rev. A | Page 28 of 44

AD5390/AD5391/AD5392

3-BYTE MODE

The 3-byte mode lets the user update more than one channel in a write sequence without having to write the device address byte each time. The device address byte is required only once and subsequent channel updates require the pointer byte and the data bytes. In 3-byte mode, the user begins with an address byte

= 0) after which the DAC acknowledges that it is

(R/

W prepared to receive data by pulling SDA low. The address byte is followed by the pointer byte; this addresses the specific channel in the DAC to be addressed and is also acknowledged by the DAC. Address Bits A3 to A0 address all channels on the

AD5390/AD5391. Address Bits A2 to A0 address all channels on the AD5392. Address Bit A3 is a zero on the AD5392. This is then followed by the two data bytes. REG1 and REG0 determine the register to be updated.

If a STOP condition is not sent following the data bytes, another channel can be updated by sending a new pointer byte followed by the data bytes. This mode requires only three bytes to be sent to update any channel once the device has been addressed initially and reduces the software overhead in updating the AD539x channels. A STOP condition at any time exits this mode. Figure 34 shows a typical configuration.

SCL

SDA

CONDITION

SCL

SDA

SCL

SDA

SCL

10 0 0 0 00A3A2A1A01 1 AD1 AD0 R/W

START

MASTER

REG0 MSB MSBLSB LSBREG1

0 0 0 0 A3 A2 A1 A0

MSB

POINTER BYTE FOR CHANNEL NEXT CHANNEL

ADDRESS BYTE POINTER BYTE FOR CHANNEL N

MOST SIGNIFICANT DATA BYTE

ACK

MSB

CONVERTER

ACK

CONVERTER

DATA FOR CHANNEL N

ACK

CONVERTER

LEAST SIGNIFICANT DATA BYTE

ACK

CONVERTER

ACK

CONVERTER

SDA

REG0 MSB MSBLSB LSBREG1

MOST SIGNIFICANT DATA BYTE

ACK

CONVERTER

DATA FOR CHANNEL NEXT CHANNEL

Figure 34. The 3-Byte Mode I

LEAST SIGNIFICANT DATA BYTE

C Write Operation

ACK

CONVERTER

STOP

CONDITION

MASTER

03773-0-024

Rev. A | Page 29 of 44

AD5390/AD5391/AD5392

2-BYTE MODE

The 2-byte mode lets the user update channels sequentially following initialization of this mode. The device address byte is required only once and the address pointer is configured for autoincrement or burst mode.

The user must begin wi

Rev. A | Page 30 of 44

AD5390/AD5391/AD5392

AD539x ON-CHIP SPECIAL FUNCTION REGISTERS

The AD539x family of parts contains a number of special function registers (SFRs) as shown in Table 22. SFRs are addressed with REG1 = 0 and REG0 = 0 and are decoded using Address Bits A3–A0.

Table 22. SFR Register Functions (REG1 = 0, REG0 = 0)

X 0 0 0 0 NOP (no operation) 0 0 0 0 1 Write CLR code 0 0 0 1 0 Soft CLR 0 1 0 0 0 Soft power-down 0 1 0 0 1 Soft power-up 0 1 1 0 0 Control register write 1 1 1 0 0 Control register read 0 1 0 1 0 Monitor channel 0 1 1 1 1 Soft reset

SFR Commands NOP (No Operation)

REG1 = REG0 = 0, A3–A0 = 0000

Performs no operation, but is useful in readback mode to clock out data on SDO for diagnostic purposes.

during a NOP operation.

Writ e C LR C od e

REG1 = REG0 = 0, A3–A0 = 0001 DB13–DB0 = Contain the CLR data.

Bringing the

loads the contents of the DAC registers with the data contained in the user-configurable CLR register and sets VOUT0 to VOUT15, accordingly. This can be very useful not only for setting up a specific output voltage in a clear condition but for calibration purposes. For calibration, the user can load full scale or zero scale to the clear code register and then issue a hardware or software clear to load this code to all DACs, removing the need for individual writes to all DACs. Default on power-up is all zeros.

Soft CLR

REG1 = REG0 = 0, A3–A0 = 0010 DB13–DB0 = Don’t Care.

Executing this instruction performs the CLR, which is functionally the same as that provided by the external CLR pin. The DAC outputs are loaded with the data in the CLR code register. The time taken to execute fully the SOFT CLR is 20 µs on the AD5390/AD5391 and 15 µs on the AD5392, and is indicated by the

A3 A2 A1 A0 Function

line low or exercising the soft clear function

CLR

low time.

BUSY

outputs a low

BUSY

Soft Power-Down

REG1 = REG0 = 0, A3–A0 =1000 DB13–DB0 = Don’t Care.

Executing this instruction performs a global power-down, which puts all channels into a low power mode, reducing analog current to 1 µA maximum and digital power consumption to 20 µA maximum. In power-down mode, the output amplifier can be configured as a high impedance output or can provide a 100 kΩ load to ground. The contents of all internal registers are retained in power-down mode.

Soft Power-Up

REG1 = REG0 = 0, A3–A0 =1001 DB13–DB0 = Don’t Care.

This instruction is used to power up the output amplifiers and the internal references. The time to exit power-down mode is 8 µs. The hardware power-down and software functions are internally combined in a digital OR function.

Soft Reset

REG1 = REG0 = 0, A5–A0 = 001111 DB13–DB0 = Don’t Care.

This instruction is used to implement a software reset. All internal registers are reset to their default values, which correspond to m at full scale and c at zero scale. The contents of the DAC registers are cleared, setting all analog outputs to 0 V. The soft reset activation time is 135 µs maximum.

Monitor Channel

REG1 = REG0 = 0, A3–A0 = 01010 DB13–DB8 = Contain data to address the channel to be monitored.

A monitor function is provided on all devices. This feature, consisting of a multiplexer addressed via the interface, allows any channel output to be routed to the MON_OUT pin for monitoring using an external ADC. In addition to monitoring all output channels, two external inputs are also provided, allowing the user to monitor signals external to the AD539x. The channel monitor function must be enabled in the control register before any channels are routed to the MON_OUT pin. On the AD5390 and AD5392 14-bit parts, DB13 to DB8 contain the channel address for the monitored channel. On the AD5391 12-bit part, DB11 to DB6 contain the channel address for the channel to be monitored. Selecting Address 63 three-states the MON_OUT pin.

The channel monitor decoding for the AD5390/AD5392 is shown in Table 23 and the monitor decoding for the AD5391 is shown in Table 24.

Rev. A | Page 31 of 44

AD5390/AD5391/AD5392

Table 23. AD5390/AD5392 Channel Monitor Decoding

REG1 REG0 A3 A2 A1 A0 DB13 DB12 DB11 DB10

0 0 1 0 1 0 0 0 0 0 0 0 X VOUT 0 VOUT 0 0 0 1 0 1 0 0 0 0 0 0 1 X VOUT 1 VOUT 1 0 0 1 0 1 0 0 0 0 0 1 0 X VOUT 2 VOUT 2 0 0 1 0 1 0 0 0 0 0 1 1 X VOUT 3 VOUT 3 0 0 1 0 1 0 0 0 0 1 0 0 X VOUT 4 VOUT 4 0 0 1 0 1 0 0 0 0 1 0 1 X VOUT 5 VOUT 5 0 0 1 0 1 0 0 0 0 1 1 0 X VOUT 6 VOUT 6 0 0 1 0 1 0 0 0 0 1 1 1 X VOUT 7 VOUT 7 0 0 1 0 1 0 0 0 1 0 0 0 X VOUT 8 0 0 1 0 1 0 0 0 1 0 0 1 X VOUT 9 0 0 1 0 1 0 0 0 1 0 1 0 X VOUT 10 0 0 1 0 1 0 0 0 1 0 1 1 X VOUT 11 0 0 1 0 1 0 0 0 1 1 0 0 X VOUT 12 0 0 1 0 1 0 0 0 1 1 0 1 X VOUT 13 0 0 1 0 1 0 0 0 1 1 1 0 X VOUT 14 0 0 1 0 1 0 0 0 1 1 1 1 X VOUT 15 0 0 1 0 1 0 1 0 0 1 0 0 X MON_IN1 MON_IN1 0 0 1 0 1 0 1 0 0 1 0 1 X MON_IN2 MON_IN2 0 0 1 0 1 0 1 1 1 1 1 1 X Three-state Three-state

DB9

DB8 DB7 to DB0

MON_OUT (AD5390)

MON_OUT (AD5392)

Table 24. AD5391 Channel Monitor Decoding

REG1 REG0 A3 A2 A1 A0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 to DB0

0 0 1 0 1 0 0 0 0 0 0 0 X VOUT 0 0 0 1 0 1 0 0 0 0 0 0 1 X VOUT 1 0 0 1 0 1 0 0 0 0 0 1 0 X VOUT 2 0 0 1 0 1 0 0 0 0 0 1 1 X VOUT 3 0 0 1 0 1 0 0 0 0 1 0 0 X VOUT 4 0 0 1 0 1 0 0 0 0 1 0 1 X VOUT 5 0 0 1 0 1 0 0 0 0 1 1 0 X VOUT 6 0 0 1 0 1 0 0 0 0 1 1 1 X VOUT 7 0 0 1 0 1 0 0 0 1 0 0 0 X VOUT 8 0 0 1 0 1 0 0 0 1 0 0 1 X VOUT 9 0 0 1 0 1 0 0 0 1 0 1 0 X VOUT 10 0 0 1 0 1 0 0 0 1 0 1 1 X VOUT 11 0 0 1 0 1 0 0 0 1 1 0 0 X VOUT 12 0 0 1 0 1 0 0 0 1 1 0 1 X VOUT 13 0 0 1 0 1 0 0 0 1 1 1 0 X VOUT 14 0 0 1 0 1 0 0 0 1 1 1 1 X VOUT 15 0 0 1 0 1 0 1 0 0 1 0 0 X MON_IN1 0 0 1 0 1 0 1 0 0 1 0 1 X MON_IN2 0 0 1 0 1 0 1 1 0 1 1 0 X Undefined

0 0 1 0 1 0 1 1 . . . . X Undefined

0 0 1 0 1 0 1 1 1 1 1 0 X Undefined 0 0 1 0 1 0 1 1 1 1 1 1 X Three-state

MON_OUT (AD5391)

Rev. A | Page 32 of 44

AD5390/AD5391/AD5392

CONTROL REGISTER WRITE

Table 25 shows the control register contents for the AD5390 and the AD5392. Table 26 provides bit descriptions. Note that REG1 = REG0 = 0, A3–A0 = 1100, and DB13–DB0 contain the control register data.

Table 25. AD5390/AD5392 Control Register Contents

MSB LSB

CR13 CR12 CR11 CR10 CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0

Table 26. AD5390 and AD5392 Bit Descriptions

Bit Description

CR13 Power-Down Status. This bit is used to configure the output amplifier state in power–down mode.

CR13 = 1: Amplifier output is high impedance (default on power-up). CR13 = 0: Amplifier output is 100 kΩ to ground.

CR12 REF Select. This bit selects the operating internal reference for the AD539x. CR12 is programmed as follows:

CR12 = 1: Internal reference is 2.5 V (AD5390/AD5392-5 default). Recommended operating reference for AD539x-5. CR12 = 0: Internal reference is 1.25 V (AD5390/AD5392-3 default). Recommended operating reference for AD5390-3 and AD5392-3.

CR11

CR10 Internal/External Reference. This bit determines if the DAC uses its internal reference or an external reference.

CR9 Channel Monitor Enable (see Table 23).

CR8

Current Boost Control. This bit is used to boost the current in the output amplifier, thus altering its slew rate and is configured as follows:

CR11 = 1: Boost mode on. This maximizes the bias current in the output amplifier, optimizing its slew rate but increasing the power dissipation. CR11 = 0: Boost mode off (default on power-up). This reduces the bias current in the output amplifier and reduces the overall power consumption.

CR10 = 1: Internal reference enabled. Reference output depends on data loaded to CR12. CR10 = 0: External reference selected (default on power-up).

CR9 = 1: Monitor enabled. This enables the channel monitor function. Following a write to the monitor channel in the SFR register, the selected channel output is routed to the MON_OUT pin. CR9 = 0: Monitor disabled (default on power-up). When monitor is disabled, the MON_OUT pin is three-stated.

Thermal Monitor Function. This function is used to monitor the internal die temperature of the AD5390/AD5392, when enabled. The thermal monitor powers down the output amplif

Rev. A | Page 33 of 44

AD5390/AD5391/AD5392

Table 27 shows the control register contents of the AD5391. Table 28 provides bit descriptions. Note that REG1 = REG0 = 0, A3–A0 = 1100, and DB13–DB0 contain the control register data.

Table 27. AD5391 Control Register Contents

MSB

CR11 CR10 CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0

LSB

Table 28. AD5391 Bit Descriptions

Bit Description

CR11 Power-Down Status. This bit is used to configure the output amplifier state in power-down mode.

CR11 = 1: Amplifier output is high impedance (default on power-up). CR11 = 0: Amplifier output is 100 kΩ to ground.

CR10 REF Select. This bit selects the operating internal reference for the AD5391. CR10 is programmed as follows:

CR10 = 1: Internal reference is 2.5 V (AD5391-5 default). Recommended operating reference for AD5391-5. CR10 = 0: Internal reference is 1.25 V (AD5391-3 default). Recommended operating reference for AD5391-3.

CR9

CR8 Internal/External Reference. This bits determines if the DAC uses its internal reference or an external reference.

CR7 Channel Monitor Enable (see Table 24).

CR6

CR5 to CR2 Don’t care. CR1 to CR0

Current Boost Control. This bit is used to boost the current in the output amplifier, thus altering its slew rate. This bit is configured as follows:

CR9 = 1: Boost mode on. This maximizes the bias current in the output amplifier, optimizing its slew rate but increasing the power dissipation. CR9 = 0: Boost mode off (default on power-up). This reduces the bias current in the output amplifier and reduces the overall power consumption.

CR8 = 1: Internal reference enabled. Reference output depends on data loaded to CR10. CR8 = 0: External reference selected (default on power-up).

CR7 = 1: Monitor enabled. This enables the channel monitor function. Following a write to the monitor channel in the SFR register, the selected channel output is routed to the MON_OUT pin. CR7 = 0: Monitor disabled (default on power-up). When monitor is disabled, the MON_OUT pin is three-stated.

Thermal Monitor Function. This function is used to monitor the internal die temperature of the AD5391, when enabled. The thermal monitor powers down the output amplifiers when the temperature exceeds 130°C. This function can be used to protect the device in cases where the power dissipation of the device may be exceeded, if a number of output channels are simultaneously short circuited. A soft power-up re-enables the output amplifiers if the die temperature has dropped below 130°C.

CR6 = 1: Thermal monitor enabled. CR6 = 0: Thermal monitor disabled (default on power-up).

Toggle Function Enable. This function lets the user toggle the output between two codes loaded to the A and B register for each DAC. Control Register Bits CR3 and CR2 are used to enable individual groups of eight channels for operation in toggle mode on the AD5391, as follows:

CR1 Group 1 Channels 8-15 CR0 Group 0 Channels 0 to 7

Logic 1 written to any bit enables a group of channels, and Logic 0 disables a group. the two registers.

LDAC is used to toggle between

Rev. A | Page 34 of 44

AD5390/AD5391/AD5392

HARDWARE FUNCTIONS

RESET FUNCTION

Bringing the

registers to their power-on reset state.

sensitive input. The default corresponds to m at full scale and c at zero scale. The contents of all DAC registers are cleared setting the outputs to 0 V. This sequence takes 270 µs maximum. The falling edge of

low for the duration, returning high when While

BUSY pulses are ignored. When

normal operation, and the status of the

until the next falling edge is detected.

line low resets the contents of all internal

RESET

is a negative edge-

RESET

initiates the reset process.

RESET

is complete.

RESET

is low, all interfaces are disabled and all

returns high, the part resumes

BUSY

pin is ignored

RESET

BUSY

LDAC

goes

ASYNCHRONOUS CLEAR FUNCTION

is negative-edge-triggered and

CLR duration of the

execution. Bringing the

CLR

the contents of the DAC registers to the data contained in the user-configurable

CLR

accordingly. This function can be used in system calibration to load zero scale and full scale to all channels together. The execution time for a

is 20 µs on the AD5390/AD5391 and

CLR

15 µs on the AD5392.

AND

BUSY

is a digital CMOS output indicating the status of the

BUSY AD539x devices.

of x2 data. If

LDAC

is stored. The user can hold the

FUNCTIONS

LDAC

goes low during internal calculations

BUSY

is taken low while

LDAC and, in this case, the DAC outputs update immediately after BUSY

goes high.

also goes low during a power-on reset

BUSY and when a falling edge is detected on the

this time, all interfaces are disabled and any events on

are ignored.

The AD539x products contain an extra feature whereby a DAC register is not updated unless its x2 register has been written to since the last time

is brought low, the DAC registers are filled with the

LDAC

was brought low. Normally, when

LDAC

contents of the x2 registers. However, these devices update the DAC register only if the x2 data has changed, thereby removing unnecessary digital crosstalk.

goes low for the

BUSY

line low clears

CLR

is low, this event

BUSY

input permanently low

pin. During

RESET

LDAC

POWER-ON RESET

The AD539x products contain a power-on reset generator and state machine. The power-on reset resets all registers to a predefined state, and the analog outputs are configured as high impedance outputs. The

pin goes low during the power-

BUSY

on reset sequence, preventing data writes to the device.

POWER-DOWN

The AD539x products contain a global power-down feature that puts all channels into a low power mode, reducing the analog power consumption to 1 µA maximum and the digital power consumption to 20 µA maximum. In power-down mode, the output amplifier can be configured as a high impedance output or provide a 100 kΩ load to ground. The contents of all internal registers are retained in power-down mode. When exiting power-down, the settling time of the amplifier elapses before the outputs settle to their correct value.

MICROPROCESSOR INTERFACING

AD539x to MC68HC11

The serial peripheral interface (SPI) on the MC68HC11 is configured for master mode (MSTR = 1), clock polarity bit (CPOL) = 0, and the clock phase bit (CPHA) = 1. The SPI is configured by writing to the SPI control register (SPCR)—see the 68HC11 User Manual. SCK of the MC68HC11 drives the SCLK of the AD539x, the MOSI output drives the serial data line (DIN) of the AD539x, and the MISO input is driven from

. The

OUT

data is being transmitted to the AD539x, the

low (PC7). Data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the MC8HC11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle.

signal is derived from a port line (PC7). When

SYNC

AD539x

MC68HC11

MISO

MOSI

SCK

PC7

Figure 36. AD539x-MC68HC11 Interface

SER/PAR RESET

SDO

DIN

SCLK SYNC

SPI/12C

line is taken

03773-0-026

Rev. A | Page 35 of 44

AD5390/AD5391/AD5392

AD539x to PIC16C6x/7x

The PIC16C6x/7x synchronous serial port (SSP) is configured as an SPI master with the clock polarity bit = 0. This is done by writing to the synchronous serial port control register (SSPCON). See the PIC16/17 Microcontroller User Manual. In Figure 27, I/O port RA1 is used to pulse

SYNC

and enable

the serial port of the AD539x. This microcontroller transfers only eight bits of data during each serial transfer operation; therefore, three consecutive read/write operations are needed, depending on the mode. Figure 37 shows the connection diagram.

PIC16C6x/7x

SDI/RC4

SDO/RC5

SCK/RC3

RA1

AD539x

SER/PAR RESET SPI/12C

SDO

DIN

SCLK

SYNC

03773-0-027

Figure 37. AD539x to PIC16C6X/7X Interface

AD539x to 8051

The AD539x requires a clock synchronized to the serial data. The 8051 serial interface must, therefore, be operated in mode 0. In this mode, serial data enters and exits through RxD and a shift clock is output on TxD. Figure 38 shows how the 8051 is connected to the AD539x. Because the AD539x shifts data out on the rising edge of the shift clock and latches data in on the falling edge, the shift clock must be inverted. The AD539x requires its data with the MSB first. Because the 8051 outputs the LSB first, the transmit routine must take this into account.

8xC51

RxD

TxD

P1.1

AD539x

SER/PAR RESET

SPI/12C

SDO

DIN

SCLK

SYNC

03773-0-028

Figure 38. AD539x to 8051 Interface

AD539x to ADSP2101/ADSP2103

Figure 39 shows a serial interface between the AD539x and the ADSP2101/ADSP2103. The ADSP2101/ADSP2103 should be set up to operate in the SPORT transmit alternate framing mode. The ADSP2101/ADSP2103 SPORT is programmed through the SPORT control register and should be configured as follows: internal clock operation, active low framing, and 16-bit word length. Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled.

ADSP2101/

ADSP2103

TFS RFS

AD539x

RESET SPI/I2C

SDODR DINDT SCLKSCK

SYNC

03773-0-029

Figure 39. AD539x to ADSP2101/ADSP2103 Interface

Rev. A | Page 36 of 44

AD5390/AD5391/AD5392

APPLICATION INFORMATION

POWER SUPPLY DECOUPLING

In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD539x is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD539x is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the device.

For supplies with multiple pins (AV mended to tie those pins together. The AD539x should have ample supply bypassing of 10 µF in parallel with 0.1 µF on each supply located as close to the package as possible—ideally right up against the device. The 10 µF capacitors are the tantalum bead type. The 0.1 µF capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), such as the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching.

The power supply lines of the AD539x should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. A ground line routed between the DIN and SCLK lines helps reduce crosstalk between them (not required on a multilayer board, because there is a separate ground plane, but separating the lines helps).

, AVCC), it is recom-

reference. The reference should be decoupled at the REFOUT/REFIN pin of the device with a 0.1 µF capacitor.

0.1µF

10µF 0.1µF

REFOUT/REFIN

0.1µF REF_GND

Figure 40. Typical Configuration with External Reference

AD539x

SIGNAL_GNDDAC_GND DGND

AGND

VOUT 0

VOUT 31

03773-0-060

Figure 41 shows a typical configuration when using the internal reference. On power-up, the AD539x defaults to an external reference; therefore, the internal reference needs to be configured and turned on via a write to the AD539x control register. On the AD5390/AD5392 Control Register Bit CR12 lets the user choose the reference voltage; Bit CR10 is used to select the internal reference. It is recommended to use the 2.5 V reference when AV

= 5 V, and the 1.25 V reference when AVDD = 3 V. On

the AD5391, Control Regist

Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best, but not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground plane, while signal traces are placed on the soldered side.

TYPICAL CONFIGURATION CIRCUIT

Figure 40 shows a typical configuration for the AD539x-5 when configured for use with an external reference. In the circuit shown, all AGND, SIGNAL_GND, and DAC_GND pins are tied together to a common AGND. AGND and DGND are connected together at the AD539x device. On power-up, the AD539x defaults to external reference operation. All AV are connected together and driven from the same 5 V source. It is recommended to decouple close to the device with a 0.1 µF ceramic and a 10 µF tantalum capacitor. In this application, the reference for the AD539x-5 is provided externally from either an ADR421 or ADR431 2.5 V reference. Suitable external references for the AD539x-3 include the ADR280 1.2 V

lines

Rev. A | Page 37 of 44

AD5390/AD5391/AD5392

Digital connections have been omitted for clarity. The AD539x contains an internal power-on reset circuit with a 10 ms brownout time. If the power supply ramp rate exceeds 10 ms, the user should reset the AD539x as part of the initialization process to ensure the calibration data is loaded correctly into the device.

AD539x MONITOR FUNCTION

The AD5390 contains a channel monitor function consisting of a multiplexer addressed via the interface, allowing any channel output to be routed to this pin for monitoring using an external ADC. The channel monitor function must be enabled in the control register before any channels are routed to the MON_OUT pin.

Table 23 and Table 24 contain the decoding information required to route any channel on the AD5390, AD5391, and AD5392 to the MON_OUT pin. Selecting Channel Address 63 three-states the MON_OUT pin. The AD539x family also contains two monitor input pins called MON_IN1 and MON_IN2. The user can connect external signals to these pins, which under software control can be multiplexed to MON_OUT for monitoring purposes. Figure 42 shows a typical monitoring circuit implemented using a 12-bit SAR ADC in a 6-lead SOT package. The external reference input is connected to MON_IN1 to allow it to be easily monitored. The controller output port selects the channel to be monitored, and the input port reads the converted data from the ADC.

AD5390

SYNC

SCLK

MON_OUT

AGND

DIN

AD7476

SCLK

VIN

SDATA

GND

OUTPUT PORT

INPUT PORT

CONTROLLER

AD780/

ADR431

VOUT 0

VOUT 15

REFOUT/REFIN

MON_IN1

DAC_GND SIGNAL GND

Figure 42. Typical Channel Monitoring Circuit

TOGGLE MODE FUNCTION

The toggle mode function allows an output signal to be generated using the LDAC control signal that switches between two DAC data registers. This function is configured using the SFR control register, as follows. A write with REG1 = REG0 = 0, A3–A0 = 1100 specifies a control register write. The toggle mode function is enabled in groups of eight channels using Bits CR3 and CR2 in the AD5390/AD5392 control register and using Bits CR1 and CR0 in the AD5391 control register. (See the Control Register Write section.) Figure 43 shows a block diagram of the toggle mode implementation. Each DAC channel on the AD539x contains an A and a B data register. Note that the B registers can be loaded only when toggle mode is enabled.

03773-0-030

To configure the AD539x for toggle mode of operation, the sequence of events is as follows:

1. Enable toggle mode for the required channels via the

control register.

2. Load data to A registers.

3. Load data to B registers.

4. Apply

The

LDAC

determining the analog output. The first

LDAC

is used to switch between the A and B registers in

configures the

LDAC

output to reflect the data in the A registers. This mode offers significant advantages, if the user wants to generate a square wave at the output on all channels as might be required to drive a liquid-crystal-based, variable optical attenuator. Configuring the AD5390, for example, the user writes to the control register and sets CR3 = 1 and CR2 = 1, enabling the two groups of eight for toggle mode operation. The user must then load data to all 16 A registers and B registers. Toggling the

LDAC

sets the out-

put values to reflect the data in the A and B registers, and the frequency of the

wave output. The first

determines the frequency of the square

LDAC

loads the contents of the A regis-

LDAC ters to the DAC registers. Toggle mode is disabled via the control register; the first

following the disabling of the

LDAC toggle mode updates the outputs with the data contained in the A registers.

THERMAL MONITOR FUNCTION

The AD539x family has a temperature shutdown function to protect the chip in case multiple outputs are shorted. The shortcircuit current of each output amplifier is typically 40 mA. Operating the AD539x at 5 V leads to a power dissipation of 200 mW/shorted amplifier. With five channels shorted, this leads to an extra watt of power dissipation. For the 52-lead LQFP, the θ

The thermal monitor is enabled by the user using CR8 in the AD5390/AD5392 control register and by CR6 in the AD5391 control register. The output amplifiers on the AD539x are automatically powered down if the die temperature exceeds approximately 130°C. After a thermal shutdown has occurred, the user can re-enable the part by executing a soft power-up if the temperature has dropped below 130°C or by turning off the thermal monitor function via the control register.

INPUT

DATA

A/B

is typically 44°C/W.

INPUT

DATA

DAC

14-BIT DAC

Figure 43. Toggle Mode Function

VOUT

LDAC CONTROL INPUT

03773-0-031

Rev. A | Page 38 of 44

AD5390/AD5391/AD5392

Power Amplifier Control

Multistage power amplifier designs require a large number of setpoints in the operation and control of the output stage. The AD539x are ideal for these applications because of their small size (LFCSP package) and the integration of 8 and 16 channels, offering 12- and 14-bit resolution. Figure 44 shows a typical transmitter architecture, in which the AD539x DACs can be used in the following control circuits: I power control (APC), peak power control (PPC), transmit gain control (TGC), and audio level control (ALC). DACs are also required for variable voltage attenuators, phase shifter control, and dc-setpoint control in the overall amplifier design.

control, average

BIAS

03773-0-032

Rev. A | Page 39 of 44

AD5390/AD5391/AD5392

OUTLINE DIMENSIONS

9.00

BSC SQ

PIN 1 INDICATOR

0.60 MAX

0.30

0.25

0.18

PIN 1

INDICATOR

1.00

0.85

0.80

12° MAX

SEATING PLANE

TOP

VIEW

0.80 MAX

0.65 TYP

0.50 BSC

COMPLIANT TO JEDEC STANDARDS MO-220-VMMD

EXCEPT FOR EXPOSED PAD DIMENSION

8.75

BSC SQ

0.20 REF

0.45

0.40

0.35

0.05 MAX

0.02 NOM

Figure 47. 64-Lead Lead Frame Chip Scale Package [LFCSP]

9 mm x 9 mm Body (CP-64-2)

(Dimensions shown in millimeters)

0.75

0.60

0.45

SEATING

PLANE

1.60 MAX

12.00 BSC

PIN 1

BOTTOM

VIEW

7.50 REF

6.35

6.20 SQ*

6.05

1.45

1.40

1.35

0.15

0.05

10°

6° 2°

SEATING PLANE

ROTATED 90° CCW

VIEW A

0.10 MAX COPLANARITY

Figure 48. 52-Lead Low Profile Quad Flat Package [LQFP]

0.20

0.09 7°

3.5° 0°

COMPLIANT TO JEDEC STANDARDS MS-026BCC

VIEW A

0.65 BSC

(ST-52)

(Dimensions shown in millimeters)

Rev. A | Page 40 of 44

TOP VIEW

(PINS DOWN)

0.38

0.32

0.22

10.00

BSC SQ

AD5390/AD5391/AD5392

ORDERING GUIDE

Model

AD5390BCP-3 AD5390BCP-3-REEL AD5390BCP-3-REEL7 AD5390BCP-5 AD5390BCP-5-REEL AD5390BCP-5-REEL7 AD5390BST-3 AD5390BST-3-REEL AD5390BST-5 AD5390BST-5-REEL AD5391BCP-3 AD5391BCP-3-REEL AD5391BCP-3-REEL7 AD5391BCP-5 AD5391BCP-5-REEL AD5391BCP-5-REEL7 AD5391BST-3 AD5391BST-3-REEL AD5391BST-5 AD5391BST-5-REEL AD5392BCP-3 AD5392BCP-3-REEL AD5392BCP-3-REEL7 AD5392BCP-5 AD5392BCP-5-REEL AD5392BCP-5-REEL7 AD5392BST-3 AD5392BST-3-REEL AD5392BST-5 AD5392BST-5-REEL Eval–AD5390EB

Eval–AD5391EB

Eval–AD5392EB

Temperature Range

−40°C to +85°C

Resolution AV

14-bit 2.7 V to 3.6 V 16 ±4 64-lead LFCSP CP-64-2 14-bit 2.7 V to 3.6 V 16 ±4 64-lead LFCSP CP-64-2 14-bit 2.7 V to 3.6 V 16 ±4 64-lead LFCSP CP-64-2 14-bit 4.5 V to 5.5 V 16 ±3 64-lead LFCSP CP-64-2 14-bit 4.5 V to 5.5 V 16 ±3 64-lead LFCSP CP-64-2 14-bit 4.5 V to 5.5 V 16 ±3 64-lead LFCSP CP-64-2 14-bit 2.7 V to 3.6 V 16 ±4 52-lead LQFP ST-52 14-bit 2.7 V to 3.6 V 16 ±4 52-lead LQFP ST-52 14-bit 4.5 V to 5.5 V 16 ±3 52-lead LQFP ST-52 14-bit 4.5 V to 5.5 V 16 ±3 52-lead LQFP ST-52 12-bit 2.7 V to 3.6 V 16 ±1 64-lead LFCSP CP-64-2 12-bit 2.7 V to 3.6 V 16 ±1 64-lead LFCSP CP-64-2 12-bit 2.7 V to 3.6 V 16 ±1 64-lead LFCSP CP-64-2 12-bit 4.5 V to 5.5 V 16 ±1 64-lead LFCSP CP-64-2 12-bit 4.5 V to 5.5 V 16 ±1 64-lead LFCSP CP-64-2 12-bit 4.5 V to 5.5 V 16 ±1 64-lead LFCSP CP-64-2 12-bit 2.7 V to 3.6 V 16 ±1 52-lead LQFP ST-52 12-bit 2.7 V to 3.6 V 16 ±1 52-lead LQFP ST-52 12-bit 4.5 V to 5.5 V 16 ±1 52-lead LQFP ST-52 12-bit 4.5 V to 5.5 V 16 ±1 52-lead LQFP ST-52 14-bit 2.7 V to 3.6 V 8 ±4 64-lead LFCSP CP-64-2 14-bit 2.7 V to 3.6 V 8 ±4 64-lead LFCSP CP-64-2 14-bit 2.7 V to 3.6 V 8 ±4 64-lead LFCSP CP-64-2 14-bit 4.5 V to 5.5 V 8 ±3 64-lead LFCSP CP-64-2 14-bit 4.5 V to 5.5 V 8 ±3 64-lead LFCSP CP-64-2 14-bit 4.5 V to 5.5 V 8 ±3 64-lead LFCSP CP-64-2 14-bit 2.7 V to 3.6 V 8 ±4 52-lead LQFP ST-52 14-bit 2.7 V to 3.6 V 8 ±4 52-lead LQFP ST-52 14-bit 4.5 V to 5.5 V 8 ±3 52-lead LQFP ST-52 14-bit 4.5 V to 5.5 V 8 ±3 52-lead LQFP ST-52

Output Channels

Linearity Error (LSBs)

Package Description

AD5390 Evaluation Board

AD5391 Evaluation Board

AD5392 Evaluation Board

Package Option

Rev. A | Page 41 of 44

AD5390/AD5391/AD5392

NOTES

Rev. A | Page 42 of 44

AD5390/AD5391/AD5392

NOTES

Rev. A | Page 43 of 44

AD5390/AD5391/AD5392

NOTES

Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I

C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.

D03773-0--10/04(A)

Rev. A | Page 44 of 44

ANALOG DEVICES AD5390, AD5391, AD5392 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

INTEGRATED FUNCTIONS

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

AD5390-5/AD5391-5/AD5392-5 SPECIFICATIONS

AD5390-3/AD5391-3/AD5392-3 SPECIFICATIONS

AD5390-3/AD5391-3/AD5392-3 AC CHARACTERISTICS

TIMING CHARACTERISTICS: I2C SERIAL INTERFACE

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATON AND FUNCTION DESCRIPTIONS

TERMINOLOGY

TYPICAL PERFORMANCE CHARACTERISTICS

FUNCTIONAL DESCRIPTION

DAC ARCHITECTURE—GENERAL

DATA DECODING—AD5390/AD5392

DATA DECODING—AD5391

INTERFACES

DSP-, SPI-, AND MICROWIRE-COMPATIBLE SERIAL INTERFACE

Standalone Mode

Daisy-Chain Mode

Readback Mode

I2C SERIAL INTERFACE

I2C DATA TRANSFER

START AND STOP CONDITIONS

REPEATED START CONDITION

ACKNOWLEDGE BIT (ACK)

I2C WRITE OPERATION

4-BYTE MODE

3-BYTE MODE

2-BYTE MODE

AD539x ON-CHIP SPECIAL FUNCTION REGISTERS

CONTROL REGISTER WRITE

HARDWARE FUNCTIONS

RESET FUNCTION

ASYNCHRONOUS CLEAR FUNCTION

POWER-ON RESET

POWER-DOWN

MICROPROCESSOR INTERFACING

AD539x to MC68HC11

AD539x to PIC16C6x/7x

AD539x to 8051

AD539x to ADSP2101/ADSP2103

APPLICATION INFORMATION

POWER SUPPLY DECOUPLING

TYPICAL CONFIGURATION CIRCUIT

AD539x MONITOR FUNCTION

TOGGLE MODE FUNCTION

THERMAL MONITOR FUNCTION

Power Amplifier Control

OUTLINE DIMENSIONS

ORDERING GUIDE