ANALOG DEVICES AD5390, AD5391, AD5392 Service Manual

8-/16-Channel, 3 V/5 V, Serial Input, Single-

FEATURES

AD5390: 16-channel, 14-bit voltage output DAC
AD5391: 16-channel, 12-bit voltage output DAC
AD5392: 8-channel, 14-bit voltage output DAC
Guaranteed monotonic
INL: ±1 LSB max (AD5391)

±3 LSB max (AD5390-5/AD5392-5)

±4 LSB max (AD5390-3/AD5392-3)
On-chip 1.25 V/2.5 V, 10 ppm/°C reference
Temperature range: −40°C to +85°C
Rail-to-rail output amplifier
Power-down mode
Package types:

64-lead LFCSP (9 mm × 9 mm)
52-lead LQFP (10 mm × 10 mm)

User interfaces:

Serial SPI

(featuring data readback)

2

C®-compatible interface

I

®-, QSPI™-, MICROWIRE™-, and DSP-compatible

Supply, 12-/14-Bit Voltage Output DACs

AD5390/AD5391/AD5392

INTEGRATED FUNCTIONS

Channel monitor
Simultaneous output update via

Clear function to user-programmable code
Amplifier boost mode to optimize slew rate
User-programmable offset and gain adjust
Toggle mode enables square wave generation
Thermal monitor

APPLICATIONS

Instrumentation and industrial control
Power amplifier control
Level setting (ATE)
Control systems
Microelectromechanical systems (MEMs)
Variable optical attenuators (VOAs)
Optical transceivers (MSA 300, XFP)

FUNCTIONAL BLOCK DIAGRAM

LDAC

REFOUT/REFIN SIGNAL_GND (×2)REF_GNDDAC_GND (×2)AGND (×2)AVDD (×2)DGND (×2)DVDD (×2)

AD5390

SPI/I2C

DCEN/AD1

DIN/SDA
SCLK/SCL
SYNC/AD0

SDO

BUSY

PD

CLR

RESET

MON_IN1

MON_IN2

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

INTERFACE

CONTROL

LOGIC

MACHINE

CONTROL

POWER-ON

RESET

VIN0 VIN15

MUX

MON_OUT

STATE

AND

LOGIC

INPUT

1414

REG

0

14
14

INPUT

1414

REG

1

14
14

INPUT

1414

REG

6

14
14

INPUT

1414

REG

7

14
14

m REG0

c REG0

m REG1

c REG1

m REG6

c REG6

m REG7

c REG7

Figure 1.

1.25V/2.5V

REFERENCE

DAC

1414

REG

0

DAC
REG

1

DAC
REG

6

DAC
REG

7

×

2

LDAC

DAC 0

R

R

1414

DAC 1

R

R

1414

DAC 6

R

R

1414

DAC 7

R

R

VOUT 0

VOUT 1
VOUT 2
VOUT 3
VOUT 4
VOUT 5
VOUT 6

VOUT 7
VOUT 8

VOUT 15

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

www.analog.com

03773-0-001

AD5390/AD5391/AD5392

TABLE OF CONTENTS

General Description......................................................................... 3

AD5390-5/AD5391-5/AD5392-5 Specifications.......................... 4

AD5390-5/AD5391-5/AD5392-5 AC Characteristics................. 6

AD5390-3/AD5391-3/AD5392-3 Specifications.......................... 7

AD5390-3/AD5391-3/AD5392-3 AC Characteristics................. 9

Timing Characteristics: Serial SPI-, QSPI-, Microwire-, and
DSP-Compatible Interface

Timing Characteristics: I2C Serial Interface................................ 13

Absolute Maximum Ratings.......................................................... 14

ESD Caution................................................................................ 14

Pin Configuraton and Function Descriptions ............................ 15

Te r m in o l o g y .................................................................................... 18

Typical Performance Characteristics........................................... 19

Functional Description ..................................................................23

DAC Architecture—General..................................................... 23

Data Decoding—AD5390/AD5392......................................... 24

Data Decoding—AD5391 .........................................................24

Interfaces ..........................................................................................25

DSP-, SPI-, and MICROWIRE-Compatible S eria l Interface 25

I2C Serial Interface.......................................................................... 27

I2C Data Transfer ........................................................................ 27

START and STOP Conditions .................................................. 27

Repeated START Condition...................................................... 27

............................................................. 10

I2C Write Operation ....................................................................... 28

4-Byte Mode................................................................................ 28

3-Byte Mode................................................................................ 29

2-Byte Mode................................................................................ 30

AD539x On-Chip Special Function Registers........................ 31

Control Register Write............................................................... 33

Hardware Functions ....................................................................... 35

Reset Function ............................................................................ 35

Asynchronous Clear Function.................................................. 35

and

BUSY

Power-On Reset .......................................................................... 35

Power-Down ............................................................................... 35

Microprocessor Interfacing....................................................... 35

Application Information................................................................ 37

Power Supply Decoupling ......................................................... 37

Typical Configuration Circuit .................................................. 37

AD539x Monitor Function ....................................................... 38

Toggle Mode Function............................................................... 38

Thermal Monitor Function....................................................... 38

Outline Dimensions....................................................................... 40

Ordering Guide .......................................................................... 41

Functions...................................................... 35

LDAC

Acknowledge Bit (ACK) ............................................................ 27

REVISION HISTORY

10/04: Data Sheet Changed from Rev. 0 to Rev. A

Changes to Features.......................................................................... 1

Changes to Table 1............................................................................ 3

Changes to Table 2............................................................................ 4

Changes to Table 3............................................................................ 6

Changes to Table 4............................................................................ 7

Changes to Figure 36...................................................................... 35

Rev. A | Page 2 of 44

Changes to Figure 37...................................................................... 36

Changes to Figure 38...................................................................... 36

Changes to Ordering Guide.......................................................... 41

4/04—Revision 0: Initial Version

AD5390/AD5391/AD5392

GENERAL DESCRIPTION

The AD5390/AD5391 are complete single-supply, 16-channel,
14-bit and 12-bit DACs, respectively. The AD5392 is a complete
single-supply, 8-channel, 14-bit DAC. Devices are available both
in 64-lead LFCSP and 52-lead LQFP packages. All channels
have an on-chip output amplifier with rail-to-rail operation. All
devices include an internal 1.25/2.5 V, 10 ppm/°C reference, an
on-chip channel monitor function that multiplexes the analog
outputs to a common MON_OUT pin for external monitoring,
and an output amplifier boost mode that optimizes the output
amplifier slew rate.

The AD5390/AD5391/AD5392 contain a 3-wire serial interface
with interface speeds in excess of 30 MHz that are compatible

Table 1. Additional High Channel Count, Low Voltage, Single-Supply DACs in Portfolio

Model

AD5380BST-5 14 Bits 4.5 V to 5.5 V 40 ±4 100-Lead LQFP ST-100
AD5380BST-3 14 Bits 2.7 V to 3.6 V 40 ±4 100-Lead LQFP ST-100
AD5384BBC-5 14 Bits 4.5 V to 5.5 V 40 ±4 100-Lead CSPBGA BC-100
AD5384BBC-3 14 Bits 2.7 V to 3.6 V 40 ±4 100-Lead CSPBGA BC-100
AD5381BST-5 12 Bits 4.5 V to 5.5 V 40 ±1 100-Lead LQFP ST-100
AD5381BST-3 12 Bits 2.7 V to 3.6 V 40 ±1 100-Lead LQFP ST-100
AD5382BST-5 14 Bits 4.5 V to 5.5 V 32 ±4 100-Lead LQFP ST-100
AD5382BST-3 14 Bits 2.7 V to 3.6 V 32 ±4 100-Lead LQFP ST-100
AD5383BST-5 12 Bits 4.5 V to 5.5 V 32 ±1 100-Lead LQFP ST-100
AD5383BST-3 12 Bits 2.7 V to 3.6 V 32 ±1 100-Lead LQFP ST-100

Resolution AVD D Ra nge

Output
Channels

with SPI, QSPI, MICROWIRE, and DSP interface standards

2

and an I

C-compatible interface supporting a 400 kHz data

transfer rate.

An input register followed by a DAC register provides double­buffering, allowing DAC outputs to be updated independently
or simultaneously using the

input. Each channel has a

LDAC

programmable gain and offset adjust register, letting the user
fully calibrate any DAC channel.

Power consumption is typically 0.25 mA per channel.

Linearity
Error (LSB) Package Description Package Option

Rev. A | Page 3 of 44

AD5390/AD5391/AD5392

AD5390-5/AD5391-5/AD5392-5 SPECIFICATIONS

AVDD = 4.5 V to 5.5 V; DV
All specifications T

MIN

Table 2.

Parameter

ACCURACY

Resolution 14 12 Bits
Relative Accuracy ±3 ±1 LSB max
Differential Nonlinearity −1/+2 ±1 LSB max Guaranteed monotonic over temperature.
Zero-Scale Error 4 4 mV max
Offset Error ±4 ±4 mV max Measured at code 32 in the linear region.
Offset Error TC ±5 ±5 µV/°C typ
Gain Error ±0.024 ± 0.024 % FSR max At 25°C T

±0.06 ±0.06 % FSR max

Gain Temperature Coefficient
DC Crosstalk2 0.5 0.5 LSB max

REFERENCE INPUT/OUTPUT

Reference Input2

Reference Input Voltage 2.5 2.5 V

DC Input Impedance 1 1 MΩ min Typically 100 MΩ.
Input Current ±1 ±1 µA max Typically ±30 nA.
Reference Range

Reference Output

3

Output Voltage 2.495/2.505 2.495/2.505 V min/max At ambient, optimized for 2.5 V operation.

1.22/1.28 1.22/1.28 V min/max At ambient when 1.25 V reference is selected.
Reference TC ±10 ±10 ppm max Temperature range: 25°C to 85°C.

±15 ±15 ppm max Temperature range: −40°C to +85°C.

Output Impedance 2.2 2.2 kΩ typ

OUTPUT CHARACTERISTICS2

Output Voltage Range4 0/AV
Short-Circuit Current 40 40 mA max
Load Current ±1 ±1 mA max
Capacitive Load Stability

RL = ∞ 200 200 pF max
RL = 5 kΩ 1,000 1,000 pF max

DC Output Impedance 0.5 0.5 Ω max

MONITOR OUTPUT PIN

Output Impedance 500 500 Ω typ
Three-State Leakage Current 100 100 nA typ
LOGIC INPUTS2 DVDD = 2.7 V to 5.5 V.
VIH, Input High Voltage 2 2 V min
VIL, Input Low Voltage 0.8 0.8 V max
Input Current ±10 ±10 µA max Total for all pins. TA = T
Pin Capacitance 10 10 pF max

= 2.7 V to 5.5 V; AGND = DGND = 0 V; REFIN = 2.5 V external.

DD

to T

, unless other wise noted.

MAX

AD5390-51
AD5392-5

2

2 2 ppm FSR/°C typ

1 V to

/2

AV

DD

AD5391-5

1

1 V to AV

1

Unit

/2 V min/max

DD

DD

0/AV

DD

V min/max

Test Conditions/Comments

to T

MAX

.

MIN

±1% for specified performance,
AV

= 2 × REFIN + 50 mV.

DD

Enabled via internal/external bit in control
register. REF select bit in control register
selects the reference voltage.

to T

MAX

.

MIN

Rev. A | Page 4 of 44

AD5390/AD5391/AD5392

Parameter

AD5390-51
AD5392-5

AD5391-5

1

1

Unit

Test Conditions/Comments

LOGIC INPUTS (SCL, SDA Only)

VIH, Input High Voltage 0.7 DV
VIL, Input Low Voltage 0.3 DV

DD

DD

0.7 DV

0.3 DV

DD

DD

V min SMBus-compatible at DVDD < 3.6 V.

V max SMBus-compatible at DVDD < 3.6 V.
IIN, Input Leakage Current ±1 ±1 µA max
V

, Input Hysteresis 0.05 DV

HYST

0.05 DV

DD

DD

V min
CIN, Input Capacitance 8 8 pF typ
Glitch Rejection 50 50 ns max

Input filtering suppresses noise spikes of
<50 ns.

LOGIC OUTPUTS (BUSY, SDO)2

Output Low Voltage 0.4 0.4 V max DVDD = 5 V ± 10%, sinking 200 µA.
Output High Voltage DVDD − 1 DVDD − 1 V min

= 5 V ± 10%, SDO only, sourcing

DV

DD

200 µA.
Output Low Voltage 0.4 0.4 V max DVDD = 2.7 V to 3.6 V, sinking 200 µA.
Output High Voltage DVDD − 0.5 DVDD − 0.5 V min

= 2.7 V to 3.6 V SDO only, sourcing

DV

DD

200 µA.
High Impedance Leakage Current ±1 ±1 µA max
High Impedance Output

5 5 pF typ

Capacitance

LOGIC OUTPUT (SDA)2

VOL, Output Low Voltage 0.4 0.4 V max I

0.6 0.6 V max I

= 3 mA.

SINK

= 6 mA.

SINK

Three-State Leakage Current ±1 ±1 µA max
Three-State Output Capacitance 8 8 pF typ

POWER REQUIREMENTS

AV
DV

DD

DD

4.5/5.5 4.5/5.5 V min/max

2.7/5.5 2.7/5.5 V min/max
Power Supply Sensitivity2
∆Midscale/∆AVDD −85 −85 dB typ
AI

AI

DI

DD

DD

DD

0.375 0.375

0.475 0.475

mA/channel
max

mA/channel
max

Outputs unloaded; boost off;

0.25 mA/channel typ.
Outputs unloaded; boost on;

0.325 mA/channel typ.

1 1 mA max VIH = DVDD, VIL = DGND.
AIDD (Power-Down) 1 1 µA max Typically 200 nA.
DIDD (Power-Down) 20 20 µA max Typically 3 µA.
Power Dissipation 35 35 mW max

20 20 mW max

AD5390/AD5391 with outputs unloaded;

= DVDD = 5 V; boost off.

AV

DD

AD5392 with outputs unloaded;

= DVDD = 5 V, boost off.

AV

DD

1

AD539x-5 products are calibrated with a 2.5 V reference. Temperature range for all versions: −40°C to +85°C.

2

Guaranteed by characterization, not production tested.

3

Programmable either to 1.25 V typ or 2.5 V typ via the AD539x control register. Operating the AD539x-5 products with a reference of 1.25 V leads to a degradation in

performance accuracy.

4

Accuracy guaranteed from VOUT = 10 mV to AVDD − 50 mV.

Rev. A | Page 5 of 44

AD5390/AD5391/AD5392

AD5390-5/AD5391-5/AD5392-5 AC CHARACTERISTICS

AVDD = 4.5 V to 5.5 V; DVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V.

Table 3. AD5390-5/AD5391-5/AD5392-5 AC Characteristics

Parameter All1 Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

Output Voltage Settling Time

AD5390/AD5392 8 µs typ ¼ scale to ¾ scale change settling to ±1 LSB.

10 µs max

AD5391 6 µs typ ¼ scale to ¾ scale change settling to ±1 LSB.
8 µs max
Slew rate

2

3 V/µs typ Boost mode on.

2 V/µs typ Boost mode off.

Digital-to-Analog Glitch Energy 12 nV-s typ
Glitch Impulse Peak Amplitude 15 mV typ
Channel-to-Channel Isolation 100 dB typ See Terminology section.
DAC-to-DAC Crosstalk 1 nV-s typ See Terminology section.
Digital Crosstalk 0.8 nV-s typ
Digital Feedthrough 0.1 nV-s typ Effect of input bus activity on DAC output under test.

Output Noise (0.1 Hz to 10 Hz)

15
40

µV p-p typ
µV p-p typ

Output Noise Spectral Density

@ 1 kHz 150 nV/(Hz)
@ 10 kHz 100 nV/(Hz)

1

Guaranteed by characterization, not production tested.

2

The slew rate can be adjusted via the current boost control bit in the DAC control register.

1

1/2

typ

1/2

typ

External reference midscale loaded to DAC.
Internal reference midscale loaded to DAC.

Rev. A | Page 6 of 44

AD5390/AD5391/AD5392

AD5390-3/AD5391-3/AD5392-3 SPECIFICATIONS

AVDD = 2.7 V to 3.6 V; DVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V; REFIN = 1.25 V external. All specifications T
otherwise noted.

Table 4.

Parameter

AD5390-31
AD5392-3

1

AD5391-3

1

Unit

Test Conditions/Comments

ACCURACY

Resolution 14 12 Bits
Relative Accuracy ±4 ±1 LSB max
Differential Nonlinearity −1/+2 ±1 LSB max Guaranteed monotonic over temperature.
Zero-Scale Error 4 4 mV max
Offset Error ±4 ±4 mV max Measured at code 64 in the linear region.
Offset Error TC ±5 ±5 µV/°C typ
Gain Error ±0.024 ±0.024 % FSR max At 25°C.
±0.1 ±0.1 % FSR max T

MIN

to T

MAX

.
Gain Temperature Coefficient2 2 2 ppm FSR/°C typ
DC Crosstalk 0.5 0.5 mV max

REFERENCE INPUT/OUTPUT

Reference Input

2

Reference Input Voltage 1.25 1.25 V ±1% for specified performance.
DC Input Impedance 1 1 MΩ min Typically 100 MΩ.
Input Current ±1 ±1 µA max Typically ±30 nA.
Reference Range 1 V to AVDD/2 1 V to AVDD/2 V min/max

Reference Output

3

Enabled via internal/external bit in control
register. REF select bit in control register
selects the reference voltage.

Output Voltage 1.245/1.255 1.245/1.255 V min/max At ambient. Optimized for 1.25 V operation.

2.47/2.53 2.47/2.53 V min/max At ambient when 2.5 V reference is selected.
Reference TC ±10 ±10 ppm max Temperature range: 25°C to 85°C.

±15 ±15 ppm max Temperature range: −40°C to +85°C.

Output Impedance 2.2 2.2 kΩ typ

OUTPUT CHARACTERISTICS2

Output Voltage Range

4

0/AV

DD

0/AV

DD

V min/max
Short-Circuit Current 40 40 mA max
Load Current ±1 ±1 mA max
Capacitive Load Stability

RL = ∞ 200 200 pF max
RL = 5 kΩ 1,000 1,000 pF max

DC Output Impedance 0.5 0.5 Ω max

MONITOR OUTPUT PIN2

Output Impedance 500 500 Ω typ
Three-State Leakage Current 100 100 nA typ

LOGIC INPUTS2 DV

= 2.7 V to 5.5 V.

DD

VIH, Input High Voltage 2 2 V min
VIL, Input Low Voltage 0.8 0.8 V max
Input Current ±10 ±10 µA max Total for all pins. TA = T
Pin Capacitance 10 10 pF max
Logic Inputs (SCL, SDA Only)

VIH, Input High Voltage 0.7 DV
VIL, Input Low Voltage 0.3 DV

DD

DD

0.7 DV

0.3 DV

DD

DD

V min SMBus-compatible at DVDD < 3.6 V.

V max SMBus-compatible at DVDD < 3.6 V.

IIN, Input Leakage Current ±1 ±1 µA max
V

, Input Hysteresis 0.05 DV

HYST

DD

0.05 DV

DD

V min

MIN

MIN

to T

to T

MAX

MAX

.

, unless

Rev. A | Page 7 of 44

AD5390/AD5391/AD5392

Parameter

AD5390-31
AD5392-3

1

AD5391-3

1

Unit

Test Conditions/Comments

Glitch Rejection 50 50 ns max Input filtering suppresses noise spikes <50 ns.
Logic Outputs (BUSY, SDO)2

Output Low Voltage 0.4 0.4 V max DVDD = 2.7 V to 5.5 V, sinking 200 µA.
Output High Voltage DVDD − 0.5 DVDD − 0.5 V min

= 2.7 V to 3.6 V, SDO only,

DV

DD

sourcing 200 µA.

DVDD − 0.1 DVDD − 0.1 V min

= 4.5 V to 5.5 V, SDO only,

DV

DD

sourcing 200 µA.

High Impedance Leakage

±1 ±1 µA max

Current
High Impedance Output

5 5 pF typ

Capacitance

Logic Output (SDA)2

VOL, Output Low Voltage 0.4 0.4 V max I

0.6 0.6 V max I

= 3 mA.

SINK

= 6 mA.

SINK

Three-State Leakage Current ±1 ±1 µA max
Three-State Output

8 8 pF typ

Capacitance

POWER REQUIREMENTS

AV
DV

DD

DD

2.7/3.6 2.7/3.6 V min/max

2.7/5.5 2.7/5.5 V min/max
Power Supply Sensitivity2
∆Midscale/∆AVDD −85 −85 dB typ
AI

AI

DI

DD

DD

DD

0.375 0.375

0.475 0.475

mA/channel
max

mA/channel
max

Outputs unloaded; boost off;

0.25 mA/channel typ.
Outputs unloaded; boost on;

0.325 mA/channel typ.

1 1 mA max VIH = DVDD, VIL = DGND.
AIDD (Power-Down) 1 1 µA max
DIDD (Power-Down) 20 20 µA max
Power Dissipation 21 21 mW max

AD5390/AD5391 with outputs unloaded;

= DVDD = 3 V; boost off.

AV

DD

12 12 mW max

AD5392 with outputs unloaded;

= DVDD = 3 V; boost off.

AV

DD

1

AD539x-3 products are calibrated with a 1.25 V reference. Temperature range for all versions: −40°C to +85°C.

2

Guaranteed by characterization, not production tested.

3

Programmable either to 1.25 V typ or 2.5 V typ via the AD539x control register. Operating the AD539x-3 products with a reference of 2.5 V leads to a degradation in

performance accuracy.

4

Accuracy guaranteed from VOUT = 39 mV to AVDD − 50 mV.

Rev. A | Page 8 of 44

AD5390/AD5391/AD5392

AD5390-3/AD5391-3/AD5392-3 AC CHARACTERISTICS

AVDD = 2.7 V to 3.6 V; DVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V; CL = 200 pF to AGND.

Table 5.

AD5390-3/AD5391-3/AD5392-3 AC Characteristics

Parameter All Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

Output Voltage Settling Time

AD5390/AD5392 8 µs typ ¼ scale to ¾ scale change settling to ±1 LSB.

10 µs max

AD5391 6 µs typ ¼ scale to ¾ scale change settling to ±1 LSB.
8 µs max
Slew Rate

2

3 V/µs typ Boost mode on.
2 V/µs typ Boost mode off.
Digital-to-Analog Glitch Energy 12 nV-s typ
Glitch Impulse Peak Amplitude 15 mV typ
Channel-to-Channel Isolation 100 dB typ See Terminology section.
DAC-to-DAC Crosstalk 1 nV-s typ See Terminology section.
Digital Crosstalk 0.8 nV-s typ
Digital Feedthrough 0.1 nV-s typ Effect of input bus activity on DAC output under test.

OUTPUT NOISE (0.1 Hz to 10 Hz) 15 µV p-p typ External reference midscale loaded to DAC.

40 µV p-p typ Internal reference midscale loaded to DAC.
Output Noise Spectral Density

@ 1 kHz 150 nV/(Hz)
@ 10 kHz 100 nV/(Hz)

1

Guaranteed by design and characterization, not production tested.

2

The slew rate can be programmed via the current boost control bit in the AD539x control registers.

1

1/2

typ

1/2

typ

Rev. A | Page 9 of 44

AD5390/AD5391/AD5392

TIMING CHARACTERISTICS:
SERIAL SPI-, QSPI-, MICROWIRE-, AND DSP-COMPATIBLE INTERFACE

DVDD = 2 V to 5.5 V; AVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V. All specifications T

Table 6. 3-Wire Serial Interface

Parameter

t

1

t

2

t

3

t

4

4

t

5

4

t

33 ns min

6

t

7

t

7A

t

8

t

9

4

t

10

t

11

4

t

20 ns min

12

t

13

t

14

t

15

t

16

t

17

t

17

t

18

t

19

5

t

20

4

t

5 ns min

21

4

t

8 ns min

22

4

t

23

2, 3

Limit at T

33 ns min SCLK cycle time
13 ns min SCLK high time
13 ns min SCLK low time
13 ns min
13 ns min

10 ns min
50 ns min
5 ns min Data setup time

4.5 ns min Data hold time
30 ns max

670 ns max

20 ns min
100 ns max
0 ns min
100 ns min
8 µs typ DAC output settling time, AD5390/AD5392

6 µs typ DAC output settling time, AD5391
20 ns min
12 µs max

20 ns max SCLK rising edge to SDO valid

20 ns min

1

MIN

, T

MAX

Unit Description

SYNC falling edge to SCLK falling edge setup time

th

SCLK falling edge to SYNC falling edge

24
Minimum
Minimum
Minimum

24

SYNC low time
SYNC high time
SYNC high time in readback mode

th

SCLK falling edge to BUSY falling edge

BUSY pulse width low (single channel update)

th

SCLK falling edge to LDAC falling edge

24
LDAC pulse width low
BUSY rising edge to DAC output response time
BUSY rising edge to LDAC falling edge
LDAC falling edge to DAC output response time

CLR pulse width low
CLR pulse activation time

SCLK falling edge to
SYNC rising edge to SCLK rising edge
SYNC rising edge to LDAC falling edge

MIN

to T

, unless otherwise noted.

MAX

SYNC rising edge

1

Guaranteed by design and characterization, not production tested.

2

All input signals are specified with tr = tf = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.2 V.

3

See , F , and . Figure 2 igure 3 Figure 4, Figure 5

4

Standalone mode only.

5

Daisy-chain mode only.

Rev. A | Page 10 of 44

AD5390/AD5391/AD5392

t

1

SCLK

SYNC

DIN

SDO

LDAC

t

t

9

UNDEFINED

3

t

7

t

4

t

8

DB23 DB0 DB23

INPUT WORD FOR DAC N INPUT WORD FOR DAC N+1

24 48

t

2

t

20

DB23

INPUT WORD FOR DAC N

t

DB0

DB0

22

t

23

t

13

03773-0-002

t

21

Figure 2. Serial Interface Timing Diagram (Daisy-Chain Mode)

t

1

1

2

t

4

t

7

t

t

3

t

6

8

t

9

24 24

t

2

t

5

Rev. A | Page 11 of 44

AD5390/AD5391/AD5392

SCLK

SYNC

24

t

7A

48

DIN

SDO

DB23

INPUT WORD SPECIFIES

REGISTER TO BE READ

UNDEFINED

DB0

DB23' DB0

NOP CONDITION

DB23 DB0

SELECTED REGISTER DATA

CLOCKED OUT

03773-0-006

Figure 4. Serial Interface Timing Diagram (Data Readback Mode)

200µA

TO

OUTPUT

PIN

C

L

50pF

200µA

Figure 5. Load Circuit for Digital Output Timing

I

OL

V

OR

OH (MIN)

V

OL (MAX)

I

OH

03773-0-003

Rev. A | Page 12 of 44

AD5390/AD5391/AD5392

A

TIMING CHARACTERISTICS: I2C SERIAL INTERFACE

Guaranteed by design and characterization, not production tested. DVDD = 2.7 V to 5.5 V; AVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V.

to T

All specifications T

MIN

Table 7.

Parameter

F

SCL

t

1

t

2

t

3

t

4

t

5

2

t

6

1

0 µs min tHD,
t

7

t

8

t

9

t

10

0 ns min tR, rise time of SCL and SDA when receiving (CMOS-compatible)
t

11

0 ns min tF, fall time of SDA when receiving (CMOS-compatible)
300 ns max tF, fall time of SCL and SDA when receiving
20 + 0.1 C

3

C

B

1

See F . igure 6

2

A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH MIN of the SCL signal)

to bridge the undefined region of SCL’s falling edge.

3

CB is the total capacitance of one bus line in pF; tR and tF measured between 0.3 DVDD and 0.7 DVDD.

, unless other wise noted.

MAX

Limit at T

MIN

, T

MAX

Unit Description

400 kHz max SCL clock frequency

2.5 µs min SCL cycle time

0.6 µs min t

1.3 µs min t

0.6 µs min tHD,
100 ns min tSU,

0.9 µs max tHD,

0.6 µs min tSU,

0.6 µs min tSU,

1.3 µs min t

, SCL high time

HIGH

, SCL low time

LOW

, start/repeated start condition hold time

STA

, data setup time

DAT

data hold time

DAT

data hold time

DAT

setup time for repeated start

STA

stop condition setup time

STO

, bus free time between a stop and a start condition

BUF

300 ns max tF, fall time of SDA when transmitting

300 ns max tF, fall time of SDA when transmitting

B

ns min tF, fall time of SCL and SDA when transmitting

400 pF max Capacitive load for each bus line

SD

t

SCL

9

START

CONDITION

t

3

t

4

t

10

t

6

t

11

Figure 6. I

t

2

2

C Interface Timing Diagram

t

t

5

7

t

4

REPEATED

START

CONDITION

t

1

t

8

STOP

CONDITION

03773-0-007

Rev. A | Page 13 of 44

AD5390/AD5391/AD5392

ABSOLUTE MAXIMUM RATINGS

Transient currents of up to 100 mA do not cause SCR latch-up.

= 25°C, unless otherwise noted.

T

A

Table 8.

Parameter Rating

AVDD to AGND −0.3 V to +7 V
DVDD to DGND −0.3 V to +7 V
Digital Inputs to DGND −0.3 V to DVDD + 0.3 V
Digital Outputs to DGND −0.3 V to DVDD + 0.3 V
VREF to AGND −0.3 V to +7 V
REFOUT to AGND −0.3 V to +7 V
AGND to DGND −0.3 V to +0.3 V
VOUTX to AGND −0.3 V to AVDD + 0.3 V
Operating Temperature Range

Commercial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ max) 150°C

64-Lead LFCSP Package, θ

52-lLad LQFP Package, θ
Reflow Soldering Peak

Temperature

JA

JA

22°C/W
38°C/W
230°C

Stresses above absolute maximum ratings may cause permanent
damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above
those listed in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. A | Page 14 of 44