ANALOG DEVICES AD5360 Service Manual

16-Channel, 16-/14-Bit,

VDDV

www.BDTIC.com/ADI

FEATURES

16-channel DAC in 52-lead LQFP and 56-lead LFCSP

packages Guaranteed monotonic to 16/14 bits Nominal output voltage range of −10 V to +10 V Multiple output spans available Temperature monitoring function Channel monitoring multiplexer GPIO function System calibration function allowing user-programmable

offset and gain Channel grouping and addressing features Data error checking feature

FUNCTIONAL BLOCK DIAGRAM

8

TO MUX 2s

n

A/B

n

8

n

MUX

n

·

n

·

n

TO MUX 2s

n

·

n

A/B MUX

·

TEMP_OUT

PEC

MON_IN0

MON_IN1

MON_OUT

GPIO

BIN/2S COMP

SYNC

SDI

SCLK

SDO

BUSY

RESET

CLR

DV

TEMP

SENSOR

CONTROL REGISTER

VOUT0 TO VOUT15

MUX

GPIO

REGISTER

SERIAL

INTERFACE

STATE

MACHINE

AD5360/

AD5361

CC

8

6

2

n

AGND DGND LDAC

SS

n = 16 FOR AD5360 n = 14 FOR AD5361

8

A/B SELECT

REGISTER

n

X1 REGISTER

n

M REGISTER

n

C REGIST ER

·

n

X1 REGISTER

n

M REGISTER

n

C REGIST ER

8

A/B SELECT

REGISTER

n

X1 REGISTER

n

M REGISTER

n

C REGIST ER

·

n

X1 REGISTER

n

M REGISTER

n

C REGIST ER

X2A REGISTER

X2B REGISTER

·

X2A REGISTER

X2B REGISTER

X2A REGISTER

X2B REGISTER

·

X2A REGISTER

X2B REGISTER

Figure 1.

Serial Input, Voltage-Output DAC

AD5360/AD5361

SPI-compatible serial interface

2.5 V to 5.5 V digital interface

OFS0

DAC 0

·

DAC 7

OFS1

DAC 0

·

DAC 7

RESET

14

n

OFFSET

DAC 0

·

DAC 7

OFFSET

DAC 1

DAC 0

·

DAC 7

)

VREF0

VOUT0

VOUT1

VOUT2

VOUT3

VOUT4

VOUT5

VOUT6

VOUT7

SIGGND0

VREF1

VOUT8

VOUT9

VOUT10

VOUT11

VOUT12

VOUT13

VOUT14

VOUT15

SIGGND1

05761-007

BUFFER

GROUP 0

OUTPUT BUFFER

AND POWER-

DOWN CONTROL

·

OUTPUT BUFFER

AND POWER-

DOWN CONTROL

GROUP 1

OUTPUT BUFFER

AND POWER-

DOWN CONTROL

·

OUTPUT BUFFER

AND POWER-

DOWN CONTROL

Digital reset ( Clear function to user-defined SIGGNDx Simultaneous update of DAC outputs

APPLICATIONS

Instrumentation Industrial control systems Level setting in automatic test equipment (ATE) Variable optical attenuators (VOA) Optical line cards

14

REGISTER

n

MUX

REGISTER

2

·

n

MUX

2

REGISTER

14

REGISTER

n

MUX

REGISTER

2

·

n

MUX

REGISTER

2

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD5360/AD5361

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REVISION HISTORY

2/08—Rev. 0 to Rev. A

Added LFCSP Package ....................................................... Universal

Change to DC Crosstalk Parameter ............................................... 4

Change to Power Dissipation Unloaded (P) Parameter .............. 5

Added t

Change to Figure 4 ........................................................................... 7

Change to Table 5 Summary ........................................................... 9

Added Figure 8 ................................................................................ 10

Changes to Table 6 .......................................................................... 10

Changes to Calibration Section .................................................... 18

Changes to Reset Function Section .............................................. 19

Added Packet Error Checking Section ........................................ 22

Updated Outline Dimensions ....................................................... 27

Changes to Ordering Guide .......................................................... 27

10/07—Revision 0: Initial Version

Parameter ......................................................................... 6

23

Rev. A | Page 2 of 28

AD5360/AD5361

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GENERAL DESCRIPTION

The AD5360/AD5361 contain sixteen, 16-/14-bit DACs in a single 52-lead LQFP or 56-lead LFCSP package. They provide buffered voltage outputs with a span four times the reference voltage. The gain and offset of each DAC can be independently trimmed to remove errors. For even greater flexibility, the device is divided into two groups of eight DACs, and the output range of each group can be independently adjusted by an offset DAC.

The AD5360/AD5361 offer guaranteed operation over a wide supply range with V +8 V to +16.5 V. The output amplifier headroom requirement is 1.4 V.

from −4.5 V to −16.5 V and VDD from

SS

The AD5360/AD5361 have a high speed 4-wire serial interface, which is compatible with SPI, QSPI™, MICROWIRE™, and DSP

interface standards and can handle clock speeds of up to 50 MHz. All the outputs can be updated simultaneously by taking the gain register and an offset adjust register.

Each DAC output is amplified and buffered on-chip with respect to an external SIGGNDx input. The DAC outputs can also be switched to SIGGNDx via the

LDAC

input low. Each channel has a programmable

CLR

pin.

Rev. A | Page 3 of 28

AD5360/AD5361

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SPECIFICATIONS

DVCC = 2.5 V to 5.5 V; VDD = 9 V to 16.5 V; VSS = −16.5 V to −4.5 V; V gain (M), offset (C), and DAC offset registers at default value; all specifications T

Table 1.

Parameter B Version1Unit Test Conditions/Comments

ACCURACY

Resolution

AD5360 16 Bits AD5361 14 Bits

Relative Accuracy

AD5360 ±4 LSB max

AD5361 ±1 LSB max Differential Nonlinearity ±1 LSB max Guaranteed monotonic by design over temperature Zero-Scale Error ±15 mV max Before calibration Full-Scale Error ±20 mV max Before calibration Gain Error 0.1 % FSR Before calibration Zero-Scale Error Full-Scale Error Span Error of Offset DAC ±75 mV max VOUTx3 Temperature Coefficient 5 ppm FSR/°C typ Includes linearity, offset, and gain drift DC Crosstalk4 180 μV max Typically 20 μV; measured channel at midscale, full-scale

REFERENCE INPUTS (VREF0, VREF1)

VREF Input Current ±10 μA max Per input; typically ±30 nA VREF Range

SIGGND INPUT (SIGGND0 to SIGGND1)4

DC Input Impedance 50 kΩ min Typically 55 kΩ Input Range ±0.5 V max SIGGND Gain 0.995/1.005 Min/max

OUTPUT CHARACTERISTICS

Output Voltage Range VSS + 1.4 V min I V Nominal Output Voltage Range −10 to +10 V nominal Short-Circuit Current 15 mA max VOUTx3 to DVCC, VDD, or VSS Load Current ±1 mA max Capacitive Load 2200 pF max DC Output Impedance 0.5 Ω max

MONITOR PIN (MON_OUT)

Output Impedance

DAC Output at Positive Full-Scale 1000 Ω typ

DAC Output at Negative Full-Scale 500 Ω typ Three-State Leakage Current 100 nA typ Continuous Current Limit 2 mA max

DIGITAL INPUTS JEDEC compliant

Input High Voltage 1.7 V min DVCC = 2.5 V to 3.6 V

2.0 V min DV Input Low Voltage 0.8 V max DVCC = 2.5 V to 5.5 V Input Current ±1 μA max ±20 μA max

Input Capacitance

2

1 LSB typ After calibration

2

2/5 V min/max ±2% for specified operation

2

4

1 LSB typ After calibration

− 1.4 V max I

DD

10 pF max

= 5 V; AGND = DGND = SIGGND = 0 V; RL = open circuit;

REF

to T

MIN

See the

, unless otherwise noted.

MAX

Offset DACS section for details

change on any other channel

= 1 mA

LOAD

= 1 mA

LOAD

= 3.6 V to 5.5 V

CC

RESET

SYNC

,

, SDI, and SCLK pins

CLR

BIN

,

/2SCOMP, and GPIO pins

Rev. A | Page 4 of 28

AD5360/AD5361

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Parameter B Version1Unit Test Conditions/Comments

DIGITAL OUTPUTS (SDO,

BUSY

, GPIO,

PEC

Output Low Voltage 0.5 V max Sinking 200 μA Output High Voltage (SDO) DVCC − 0.5 V min Sourcing 200 μA High Impedance Leakage Current ±5 μA max SDO only High Impedance Output Capacitance

TEMPERATURE SENSOR (TEMP_OUT)

4

Accuracy ±1 °C typ @ 25°C ±5 °C typ −40°C < T < +85°C Output Voltage at 25°C 1.46 V typ Output Voltage Scale Factor 4.4 mV/°C typ Output Load Current 200 μA max Current source only Power-On Time 10 ms typ To within ±5°C

POWER REQUIREMENTS

DVCC 2.5/5.5 V min/max VDD 8/16.5 V min/max VSS −4.5/−16.5 V min/max Power Supply Sensitivity

4

∆ Full Scale/∆ VDD −75 dB typ ∆ Full Scale/∆ VSS −75 dB typ

∆ Full Scale/∆ DVCC −90 dB typ DICC 2 mA max VCC = 5.5 V, VIH = DVCC, VIL = GND IDD 10 mA max Outputs unloaded ISS 10 mA max Outputs unloaded Power-Down Mode Bit 0 in the Control Register is 1

DICC 5 μA typ

IDD 35 μA typ

ISS −35 μA typ Power Dissipation

Power Dissipation Unloaded (P) 245 mW max VSS = −12 V, VDD = +12 V, DVCC = 2.5 V

Junction Temperature 130 °C max TJ = TA + P

1

Temperature range for B version: −40°C to +85°C. Typical specifications are at 25°C.

2

Specifications are guaranteed for a 5 V reference only.

3

VOUTx refers to any of VOUT0 to VOUT15.

4

Guaranteed by design and characterization, not production tested.

)

10 pF typ

TOTAL

× θJA

AC CHARACTERISTICS

DVCC = 2.5 V; VDD = 15 V; VSS = −15 V; V DAC offset registers at default value; all specifications T

Table 2.

Parameter B Version1Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

1

Output Voltage Settling Time 20 μs typ Full-scale change 30 μs max DAC latch contents alternately loaded with all 0s and all 1s Slew Rate 1 V/μs typ Digital-to-Analog Glitch Energy 5 nV-s typ Glitch Impulse Peak Amplitude 10 mV max Channel-to-Channel Isolation 100 dB typ VREF0, VREF1 = 2 V p-p, 1 kHz DAC-to-DAC Crosstalk 10 nV-s typ Digital Crosstalk 0.2 nV-s typ Digital Feedthrough 0.02 nV-s typ Effect of input bus activity on DAC output under test Output Noise Spectral Density @ 10 kHz 250 nV/√Hz typ VREF0 = VREF1 = 0 V

1

Guaranteed by design and characterization, not production tested.

= 5 V; AGND = DGND = SIGGND = 0 V; CL = 200 pF; RL = 10 kΩ; gain (M), offset (C), and

REF

MIN

to T

, unless otherwise noted.

MAX

Rev. A | Page 5 of 28

AD5360/AD5361

T

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TIMING CHARACTERISTICS

DVCC = 2.5 V to 5.5 V; VDD = 9 V to 16.5 V; VSS = −8 V to −16.5 V; V R

= open circuit; gain (M), offset (C), and DAC offset registers at default values; all specifications T

L

= 5 V; AGND = DGND = SIGGND = 0 V; CL = 200 pF to GND;

REF

MIN

to T

, unless otherwise noted.

MAX

Table 3. SPI Interface (See Figure 4 and Figure 5)

1, 2

Parameter

t

1

Limit at T

MIN

, T

Unit Description

MAX

20 ns min SCLK cycle time t2 8 ns min SCLK high time t3 8 ns min SCLK low time t4 11 ns min t

5

20 ns min t6 10 ns min t

7

5 ns min Data setup time

falling edge to SCLK falling edge setup time

SYNC Minimum SYNC 24th SCLK falling edge to SYNC

high time

rising edge

t8 5 ns min Data hold time

3

t

9

t

1/1.5 μs typ/max

10

42 ns max

rising edge to BUSY falling edge

SYNC

pulse width low (single-channel update); see Table 8

BUSY t11 600 ns max Single-channel update cycle time t12 20 ns min t13 10 ns min t14 3 μs max t15 0 ns min t16 3 μs max

rising edge to LDAC falling edge

SYNC

pulse width low

LDAC

rising edge to DAC output response time

BUSY

rising edge to LDAC falling edge

BUSY

falling edge to DAC output response time

LDAC t17 20/30 μs typ/max DAC output settling time t18 140 ns max t19 30 ns min t20 400 μs max t21 270 ns min

4

t

22

25 ns max SCLK rising edge to SDO valid

t23 80 ns max

1

Guaranteed by design and characterization, not production tested.

2

All input signals are specified with tr = tf = 2 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.

3

This is measured with the load circuit shown in Figure 2.

4

This is measured with the load circuit shown in Figure 3.

/RESET pulse activation time

CLR

pulse width low

RESET

time indicated by BUSY low

RESET

Minimum SYNC

rising edge to BUSY falling edge

RESET

high time in readback mode

200µA I

DV

CC

R

L

2.2k

TO

OUTPUT

Figure 2. Load Circuit for

Ω

C

L

50pF

BUSY

Timing Diagram

V

OL

05761-008

Rev. A | Page 6 of 28

O OUTPUT

C

L

50pF

200µA I

Figure 3. Load Circuit for SDO Timing Diagram

OL

OH

VOH (MIN) – VOL (MAX)

2

5761-009

AD5360/AD5361

V

www.BDTIC.com/ADI

t

1

SCLK

SYNC

BUSY

LDAC

OUTx

LDAC

OUTx

SDI

1

2

1

2

t

3

t

4

t

5

t

7

t

8

DB23

24

t

2

t

6

DB0

t

9

t

1

t

11

t

10

12

t

13

24

t

17

t

14

t

15

t

13

t

17

t

16

CLR

VOUTx

RESET

VOUTx

BUSY

1

LDAC ACTIVE DURING BUSY.

2

LDAC ACTIVE AFTER BUSY.

t

18

t

19

t

18

t

20

t

23

05761-010

Figure 4. SPI Write Timing

Rev. A | Page 7 of 28

AD5360/AD5361

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SCLK

SYNC

SDI

INPUT WORD SPECIFIES

REGISTER TO BE READ

SDO

t

22

DB0 DB23DB23

LSB FRO M PREVIOUS W RITE

t

21

NOP CONDITI ON

DB0

DB23 DB15

SELECTED REG ISTER DATA CLOCKED OUT

48

DB0

05761-011

Figure 5. SPI Read Timing

OUTPUT

VOLTAGE

VMAX

ACTUAL TRANSFER FUNCTION

IDEAL TRANSFER FUNCTION

FULL-SCAL E ERROR + ZERO-SCALE ERROR

N

– 1

2

n = 16 FOR AD5360 n = 14 FOR AD5361

05761-001

VMIN

0

DAC CODE

ZERO-SCALE ERROR

Figure 6. DAC Transfer Function

Rev. A | Page 8 of 28

AD5360/AD5361

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. Transient currents of up to 60 mA do not cause SCR latch-up.

Table 4.

Parameter Rating

VDD to AGND −0.3 V to +17 V VSS to AGND −17 V to +0.3 V DVCC to DGND −0.3 V to +7 V Digital Inputs to DGND −0.3 V to DVCC + 0.3 V Digital Outputs to DGND −0.3 V to DVCC + 0.3 V VREF0, VREF1 to AGND −0.3 V to +5.5 V VOUT0 to VOUT15 to AGND VSS − 0.3 V to VDD + 0.3 V SIGGND0, SIGGND1 to AGND −1 V to +1 V AGND to DGND −0.3 V to +0.3 V MON_IN0, MON_IN1, MON_OUT to AGND VSS − 0.3 V to VDD + 0.3 V Operating Temperature (TA)

Industrial (B Version) −40°C to +85°C Storage −65°C to +150°C Junction (TJ max) 130°C

θJA Thermal Impedance

52-Lead LQFP 38°C/W 56-Lead LFCSP 25°C/W

Reflow Soldering

Peak Temperature 230°C Time at Peak Temperature 10 sec to 40 sec

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. A | Page 9 of 28

ANALOG DEVICES AD5360 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

FUNCTIONAL BLOCK DIAGRAM

APPLICATIONS

TABLE OF CONTENTS

REVISION HISTORY

GENERAL DESCRIPTION

SPECIFICATIONS

AC CHARACTERISTICS

TIMING CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION