ANALOG DEVICES AD5170 Service Manual

256-Position, Two-Time Programmable,

A

www.BDTIC.com/ADI

FEATURES

256-position digital potentiometer
Two-time programmable (TTP) set-and-forget resistance

setting allows second-chance permanent programming

Unlimited adjustments prior to one-time programming

(OTP) activation

OTP overwrite allows dynamic adjustments with user-

defined preset
End-to-end resistance: 2.5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Compact 10-lead MSOP (3 mm × 4.9 mm) package
Fast settling time: t
Full read/write of wiper register
Power-on preset to midscale
Extra package address decode pins: AD0 and AD1
Single supply: 2.7 V to 5.5 V
Low temperature coefficient: 35 ppm/°C
Low power: I
Wide operating temperature: −40°C to +125°C
Evaluation board and software are available
Software replaces μC in factory programming applications

APPLICATIONS

Systems calibration
Electronics level setting
Mechanical trimmers replacement in new designs
Permanent factory PCB settings
Transducer adjustment of pressure, temperature, position,

chemical, and optical sensors
RF amplifier biasing
Automotive electronics adjustments
Gain control and offset adjustments

GENERAL DESCRIPTION

The AD5170 is a 256-position, two-time programmable, digital
potentiometer
two opportunities to permanently program the resistance setting.
For users who do not need to program the digital potentiometer
setting in memory more than once, the OTP feature is a cost­effective alternative to EEMEM. The AD5170 performs the
same electronic adjustment function as mechanical potentiometers
or variable resistors with enhanced resolution, solid-state reliability,
and superior low temperature coefficient performance.

1

The terms digital potentiometer, VR, and RDAC are used interchangeably.

= 5 μs typical in power-up

S

= 6 μA maximum

DD

1

that employs fuse link technology, giving users

I2C Digital Potentiometer

AD5170

FUNCTIONAL BLOCK DIAGRAM

B

W

V

DD

GND

AD0

AD1

SDA

SCL

12

ADDRESS

DECODE

The AD5170 is programmed using a 2-wire, I2C®-compatible
digital interface. Unlimited adjustments are allowed before
permanently setting the resistance value, and there are two
opportunities for permanent programming. During OTP
activation, a permanent blow fuse command freezes the wiper
position (analogous to placing epoxy on a mechanical trimmer).

Unlike traditional OTP digital potentiometers, the AD5170 has
a unique temporary OTP overwrite feature that allows for new
adjustments even after the fuse is blown. However, the OTP setting
is restored during subsequent power-up conditions. This feature
allows users to treat these digital potentiometers as volatile
potentiometers with a programmable preset.

For applications that program the AD5170 at the factory, Analog
Devices, Inc., offers device programming software that runs on
Windows NT®, Windows® 2000, and Windows XP operating
systems. This software effectively replaces any external I
controllers, thus enhancing the time-to-market of the systems
of the user.

FUSE

LINKS

RDAC

REGISTER

SERIAL INPUT

REGIS TER

Figure 1.

8

04104-0-001

2

C

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2003–2008 Analog Devices, Inc. All rights reserved.

AD5170

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TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Electrical Characteristics: 2.5 kΩ ............................................... 3

Electrical Characteristics: 10 kΩ, 50 kΩ, and 100 kΩ ............. 4

Timing Characteristics: 2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ ... 6

Absolute Maximum Ratings ............................................................ 7

ESD Caution .................................................................................. 7

Pin Configuration and Function Descriptions ............................. 8

Typical Performance Characteristics ............................................. 9

Test Circuits ..................................................................................... 13

Theory of Operation ...................................................................... 14

One-Time Programming (OTP) .............................................. 14

Programming the Variable Resistor and Voltage—

Rheostat Operation .................................................................... 14

Programming the Potentiometer Divider—

Voltage Output Operation......................................................... 15

ESD Protection ........................................................................... 16

Terminal Voltage Operating Range ......................................... 16

Power-Up Sequence ................................................................... 16

Power Supply Considerations ................................................... 16

Layout Considerations ............................................................... 17

Controlling the AD5170 ................................................................ 18

Software Programming ............................................................. 18

Device Programming ................................................................. 18

I2C Controller Programming .................................................... 19

I2C-Compatible, 2-Wire Serial Bus .......................................... 19

Level Shifting for Different Voltage Operation ...................... 20

Outline Dimensions ....................................................................... 21

Ordering Guide .......................................................................... 21





REVISION HISTORY

7/08—Rev. C to Rev. D

Changes to Power Supplies Parameter in Table 1 and Table 2...3

Updated Fuse Blow Condition to 400 ms Throughout ............... 5

1/08—Rev. B to Rev. C

Updated Format .................................................................. Universal

Changes to Table 1 ............................................................................ 3

Changes to Table 2 ............................................................................ 4

Changes to Table 3 ............................................................................ 6

Changes to Table 5 ............................................................................ 8

Inserted Figure 25 ........................................................................... 12

Changes to One-Time Programming (OTP) Section ................ 14

Changes to Power Supply Considerations Section ..................... 16

Deleted Figure 38 and Figure 39 ................................................... 17

Updated Outline Dimensions ....................................................... 21

Changes to Ordering Guide .......................................................... 21

5/05—Rev. A to Rev. B

Changes to Table 1 ............................................................................ 3

Changes to Table 2 ............................................................................ 5

Changes to Pin Function Descriptions .......................................... 9

Changes to Figure 28 ...................................................................... 14

Changes to Power Supply Considerations Section .................... 17

Changes to I2C-Compatible 2-Wire Serial Bus Section ............ 21

Added Level Shifting for Different Voltage Operation Section 23

Added Figure 48 ............................................................................. 23

Updated Outline Dimensions ....................................................... 24

Changes to Ordering Guide .......................................................... 24

11/04—Rev. 0 to Rev. A

Changes to Electrical Characteristics Table 1 ................................ 3

Changes to Electrical Characteristics Table 2 ................................ 4

Changes to One-Time Programming ......................................... 12

Changes to Figure 37, Figure 38, and Figure 39 ........................ 14

Changes to Power Supply Considerations .................................. 14

Changes to Figure 40 ...................................................................... 15

Changes to Layout Considerations .............................................. 15

11/03—Revision 0: Initial Version

Rev. D | Page 2 of 24

AD5170

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SPECIFICATIONS

ELECTRICAL CHARACTERISTICS: 2.5 kΩ

VDD = 5 V ± 10% or 3 V ± 10%, VA = VDD, VB = 0 V, −40°C < TA < +125°C, unless otherwise noted.

Table 1.

Parameter Symbol Conditions Min Typ1Max Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resistor Differential Nonlinearity

Resistor Integral Nonlinearity

Nominal Resistor Tolerance

Resistance Temperature Coefficient (∆RAB/RAB)/∆T 35 ppm/°C

RWB (Wiper Resistance) RWB Code = 0x00, VDD = 5 V 160 200 Ω

DC CHARACTERISTICS—POTENTIOMETER DIVIDER

MODE (SPECIFICATIONS APPLY TO ALL VRs)

Differential Nonlinearity

Integral Nonlinearity

4

4

INL −2 ±0.6 +2 LSB

Voltage Divider Temperature Coefficient (∆VW/VW)/∆T Code = 0x80 15 ppm/°C

Full-Scale Error V

Zero-Scale Error V

RESISTOR TERMINALS

Voltage Range

Capacitance A, B

Capacitance W

5

6

6

C

Shutdown Supply Current

Common-Mode Leakage ICM V

DIGITAL INPUTS AND OUTPUTS

Input Logic High (SDA and SCL)

Input Logic Low (SDA and SCL)8 VIL V

Input Logic High (AD0 and AD1) VIH V

Input Logic Low (AD0 and AD1) VIL V

Input Current IIL V

Input Capacitance

6

C

POWER SUPPLIES

Power Supply Range V

OTP Supply Voltage

8, 9

V

Supply Current IDD V

OTP Supply Current

Power Dissipation

8, 10 , 11

12

Power Supply Sensitivity PSS

2

2

R-INL R

3

R-DNL RWB, VA = no connect −2 ±0.1 +2 LSB

∆RAB T

DNL −1.5 ±0.1 +1.5 LSB

Code = 0xFF −10 −2.5 0 LSB

WFSE

Code = 0x00 0 2 10 LSB

WZSE

VA, VB, VW GND VDD V
CA, CB

W

7

8

I

I

V

A_SD

VIH V

5 pF

IL

DD RANGE

DD_OTP

DD_OTP

P

V

DISS

, VA = no connect +6 ±0.75 +6 LSB

WB

= 25°C −20 +55 %

A

f = 1 MHz, measured to GND,

45 pF

code = 0x80
f = 1 MHz, measured to GND,

60 pF

code = 0x80

= 5.5 V 0.01 1 μA

DD

= VB = VDD/2 1 nA

A

= 5 V 0.7 VDD VDD + 0.5 V

DD

= 5 V −0.5 +0.3 VDD V

DD

= 3 V 2.1 V

DD

= 3 V 0.6 V

DD

= 0 V or 5 V ±1 μA

IN

2.7 5.5 V

T

V

= 25°C 4.75 5 5.25 V

A

= 5 V or VIL = 0 V 3.5 6 μA

IH

= 5 V, TA = 25°C 100 mA

DD_OTP

= 5 V or VIL = 0 V, VDD = 5 V 33 μW

IH

= 5 V ± 10%, code =

V

DD

±0.02 ±0.08 %/%

midscale

Rev. D | Page 3 of 24

AD5170

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Parameter Symbol Conditions Min Typ1Max Unit

DYNAMIC CHARACTERISTICS

–3 dB Bandwidth BW_2.5k Code = 0x80 4.8 MHz
Total Harmonic Distortion THDW V
VW Settling Time tS

Resistor Noise Voltage Density e

1

Typical specifications represent average readings at 25°C and VDD = 5 V.

2

Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from the ideal between successive tap positions. Parts are guaranteed monotonic.

3

VAB = VDD, wiper (VW) = no connect.

4

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V.

DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.

5

The A, B, and W resistor terminals have no limitations on polarity with respect to each other.

6

Guaranteed by design and not subject to production test.

7

Measured at the A terminal. The A terminal is open circuited in shutdown mode.

8

The minimum voltage requirement on the VIH is 0.7 V × VDD. For example, VIH minimum = 3.5 V when VDD = 5 V. It is typical for the SCL and SDA resistors to be pulled

9

Different from operating power supply; power supply for OTP is used one time only.

10

11

12

13

. However, care must be taken to ensure that the minimum VIH is met when the SCL and SDA are driven directly from a low voltage logic controller without

up to V

DD

pull-up resistors.

Different from operating current; supply current for OTP lasts approximately 400 ms for use one time only.
See Figure 26 for the energy plot during OTP program.
P

is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

DISS

All dynamic characteristics use VDD = 5 V.

ELECTRICAL CHARACTERISTICS: 10 KΩ, 50 KΩ, AND 100 KΩ

VDD = 5 V ± 10% or 3 V ± 10%, VA = VDD, VB = 0 V, −40°C < TA < +125°C, unless otherwise noted.

13

= 1 V rms, VB = 0 V, f = 1 kHz 0.1 %

A

= 5 V, VB = 0 V,

V

A

1 μs

±1 LSB error band

R

N_WB

= 1.25 kΩ, f = 1 kHz 3.2 nV/√Hz

WB

Table 2.

Parameter Symbol Conditions Min Typ1Max Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resistor Differential Nonlinearity
Resistor Integral Nonlinearity
Nominal Resistor Tolerance

2

2

R-INL R

3

R-DNL RWB, VA = no connect −1 ±0.1 +1 LSB

∆RAB T

, VA = no connect −2.5 ±0.25 +2.5 LSB

WB

= 25°C −20 +20 %

A

Resistance Temperature Coefficient (∆RAB/RAB)/∆T 35 ppm/°C
RWB (Wiper Resistance) RWB Code = 0x00, VDD = 5 V 160 200 Ω

DC CHARACTERISTICS—POTENTIOMETER DIVIDER
MODE (SPECIFICATIONS APPLY TO ALL VRs)

Differential Nonlinearity
Integral Nonlinearity

4

4

INL −1 ±0.3 +1 LSB

DNL −1 ±0.1 +1 LSB

Voltage Divider Temperature Coefficient (∆VW/VW)/∆T Code = 0x80 15 ppm/°C
Full-Scale Error V
Zero-Scale Error V

Code = 0xFF −2.5 −1 0 LSB

WFSE

Code = 0x00 0 1 2.5 LSB

WZSE

RESISTOR TERMINALS

Voltage Range
Capacitance A, B

5

6

VA, VB, VW GND VDD V
CA, CB

f = 1 MHz, measured to GND,

45 pF

code = 0x80

Capacitance W

6

C

W

f = 1 MHz, measured to GND,

60 pF

code = 0x80
Shutdown Supply Current
Common-Mode Leakage ICM V

7

I

V

A_SD

DD

= VB = VDD/2 1 nA

A

= 5.5 V 0.01 1 μA

DIGITAL INPUTS AND OUTPUTS

Input Logic High (SDA and SCL)
Input Logic Low (SDA and SCL)
Input Logic High (AD0 and AD1) VIH V
Input Logic Low (AD0 and AD1) VIL V
Input Current IIL V
Input Capacitance

6

C

8

8

V

VIH V

V

IL

5 pF

IL

= 5 V 0.7 VDD VDD + 0.5 V

DD

= 5 V −0.5 +0.3 VDD V

DD

= 3 V 2.1 V

DD

= 3 V 0.6 V

DD

= 0 V or 5 V ±1 μA

IN

Rev. D | Page 4 of 24

AD5170

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Parameter Symbol Conditions Min Typ1Max Unit

POWER SUPPLIES

Power Supply Range V
OTP Supply Voltage

8, 9

V

Supply Current IDD V
OTP Supply Current
Power Dissipation

8, 10 , 11

12

I
P

Power Supply Sensitivity PSS

DYNAMIC CHARACTERISTICS

13

–3 dB Bandwidth BW RAB = 10 kΩ, code = 0x80 600 kHz
R
R
Total Harmonic Distortion THDW

VW Settling Time (10 kΩ/50 kΩ/100 kΩ) tS

Resistor Noise Voltage Density e

1

Typical specifications represent average readings at 25°C and VDD = 5 V.

2

Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from the ideal between successive tap positions. Parts are guaranteed monotonic.

3

VAB = VDD, wiper (VW) = no connect.

4

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V.

DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.

5

The A, B, and W resistor terminals have no limitations on polarity with respect to each other.

6

Guaranteed by design and not subject to production test.

7

Measured at the A terminal. The A terminal is open circuited in shutdown mode.

8

The minimum voltage requirement on the VIH is 0.7 V × VDD. For example, VIH minimum = 3.5 V when VDD = 5 V. It is typical for the SCL and SDA resistors to be pulled up

to VDD. However, care must be taken to ensure that the minimum VIH is met when the SCL and SDA are driven directly from a low voltage logic controller without pull­up resistors.

9

Different from operating power supply, power supply OTP is used one time only.

10

Different from operating current, supply current for OTP lasts approximately 400 ms for use one time only.

11

See Figure 26 for the energy plot during OTP program.

12

P

is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

DISS

13

All dynamic characteristics use VDD = 5 V.

2.7 5.5 V

DD RANGE

4.75 5 5.25 V

DD_OTP

= 5 V or VIL = 0 V 3.5 6 μA

IH

V

DD_OTP

V

DISS

= 5 V, TA = 25°C 100 mA

DD_OTP

= 5 V or VIL = 0 V, VDD = 5 V 33 μW

IH

= 5 V ± 10%,

V

DD

±0.02 ±0.08 %/%

code = midscale

= 50 kΩ, code = 0x80 100 kHz

AB

= 100 kΩ, code = 0x80 40 kHz

AB

=1 V rms, VB = 0 V, f = 1 kHz,

V

A

= 10 kΩ

R

AB

= 5 V, VB = 0 V,

V

A

0.1 %

2 μs

±1 LSB error band

R

N_WB

= 5 kΩ, f = 1 kHz 9 nV/√Hz

WB

Rev. D | Page 5 of 24

AD5170

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TIMING CHARACTERISTICS: 2.5 KΩ, 10 KΩ, 50 KΩ, AND 100 KΩ

VDD = 5 V ± 10% or 3 V ± 10%, VA = VDD; VB = 0 V, −40°C < TA < +125°C, unless otherwise noted.

Table 3.

Parameter Symbol Conditions Min Typ Max Unit

I2C INTERFACE TIMING CHARACTERISTICS1 (SPECIFICATIONS

APPLY TO ALL PARTS)
SCL Clock Frequency f
t

Bus Free Time Between Stop and Start t1 1.3 μs

BUF

t

Hold Time (Repeated Start) t2

HD;STA

t

Low Period of SCL Clock t3 1.3 μs

LOW

t

High Period of SCL Clock t4 0.6 μs

HIGH

t

Setup Time for Repeated Start Condition t5 0.6 μs

SU;STA

t

Data Hold Time

HD;DAT

t

Data Setup Time t7 100 ns

SU;DAT

2

tF Fall Time of Both SDA and SCL Signals t8 300 ns
tR Rise Time of Both SDA and SCL Signals t9 300 ns
t

Setup Time for Stop Condition t10 0.6 μs

SU;STO

OTP Program Time t11 400 ms

1

See Figure 2 for locations of measured values.

2

The maximum t

has only to be met if the device does not stretch the low period (t

HD;DAT

t

8

t

6

400 kHz

SCL

After this period, the first clock

0.6 μs

pulse is generated.

t6 0.9 μs

) of the SCL signal.

LOW

t

t

9

2

SCL

t

10

P

04104-044

SDA

t

t

1

PS S

t

2

3

t

9

t

8

Figure 2. I

t

4

2

C Interface Detailed Timing Diagram

t

7

t

5

Rev. D | Page 6 of 24

AD5170

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 4.

Parameter Rating

VDD to GND −0.3 V to +7 V
VA, VB, VW to GND VDD
Terminal Current, A to B, A to W, B to W

Pulsed ±20 mA

Continuous ±5 mA
Digital Inputs and Output Voltage to GND 0 V to 7 V
Operating Temperature Range −40°C to +125°C
Maximum Junction Temperature (T
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C
Thermal Resistance

θJA: 10-Lead MSOP 230°C/W

1

Maximum terminal current is bound by the maximum current handling of

the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.

2

Package power dissipation = (T

2

− TA)/θJA.

JMAX

1

) 150°C

JMAX

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. D | Page 7 of 24

AD5170

G

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

B

2

A

AD5170

3

AD0

V

TOP VIEW

(Not to Scale)

ND

4

5

DD

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 B B Terminal. GND ≤ VB ≤ VDD.
2 A A Terminal. GND ≤ VA ≤ VDD.
3 AD0 Programmable Address Bit 0 for Multiple Package Decoding.
4 GND Digital Ground.
5 VDD

Positive Power Supply. Specified for operation from 2.7 V to 5.5 V. For OTP programming, V
within the 4.75 V to 5.25 V range and capable of driving 100 mA.

6 SCL

Serial Clock Input. Positive edge triggered. Requires a pull-up resistor. If it is driven directly from a logic controller
without the pull-up resistor, ensure that VIH minimum is 0.7 V × VDD.

7 SDA

Serial Data Input/Output. Requires a pull-up resistor. If it is driven directly from a logic controller without the
pull-up resistor, ensure that V

minimum is 0.7 V × VDD.

IH

8 AD1 Programmable Address Bit 1 for Multiple Package Decoding.
9 NC No Connect.
10 W W Terminal. GND ≤ VW ≤ VDD.

10

W

9

NC

8

AD1

SDA

7

SCL

6

04104-048

supply needs to be

DD

Rev. D | Page 8 of 24