Analog Devices AD5165 Datasheet

CLK

256-Position, Ultralow Power

1.8 V Logic-Level Digital Potentiometer

FEATURES

Ultralow standby power IDD = 50 nA typical
256-position
End-to-end resistance 100 kΩ
Logic high voltage 1.8 V
Power supply 2.7 V to 5.5 V
Low temperature coefficient 35 ppm/°C
Compact thin 8-lead TSOT-8 (2.9 mm × 2.8 mm) package
Simple 3-wire digital interface
Wide operating temperature −40°C
Pin-to-pin compatible to AD5160 with CS inverted

APPLICATIONS

Battery-operated electronics adjustment
Remote utilities meter adjustment
Mechanical potentiometer replacement
Transducer circuit adjustment
Automotive electronics adjustment
Gain control and offset adjustment
System calibration
VCXO adjustment

GENERAL OVERVIEW

The AD5165 provides a compact 2.9 mm × 2.8 mm packaged
solution for 256-position adjustment applications. These devices
perform the same electronic adjustment function as mechanical
potentiometers or variable resistors, with enhanced resolution,
solid-state reliability, and superior low temperature coefficient
performance. The AD5165’s supply voltage requirement is 2.7 V
to 5.5 V, but its logic voltage requirement is 1.8 V to V
AD5165 consumes very low quiescent power during standby
mode and is ideal for battery-operated applications.

Wiper settings are controlled through a simple 3-wire interface.
The interface is similar to the SPI® digital interface except for the
inverted chip-select function that minimizes logic power con­sumption in the idling state. The resistance between the wiper
and either endpoint of the fixed resistor varies linearly with
respect to the digital code transferred into the wiper register.

Operating from a 2.7 V to 5.5 V power supply and consuming
less than 50 nA typical standby power allows use in battery­operated portable or remote utility device applications.

to +125°C

DD

. The

AD5165

FUNCTIONAL BLOCK DIAGRAM

V

DD

04749-0-002

A,VB,VW

A

W

B

04749-0-001

< 5V

CS

SDI

3-WIRE

INTERFACE

WIPER

REGISTER

GND

Figure 1.

PIN CONFIGURATION

1

W

2

AD5165

V

DD

TOP VIEW

3

GND

(Not to Scale)

4

CLK

Figure 2.

A

8

B

7

CS

6
5

SDI

TYPICAL APPLICATION

AD5165

CS
CLK
SDI

Figure 3.

5V

V

DD

GND

V

A

WIDE TERMINAL

V

W

VOLTAGE RANGE:

V

B

0V < V

VOH= 1.8V MIN

3.3V

DIGITAL
CONTROL
LOGIC OR

MICRO

Note:
The terms digital potentiometer, RDAC, and VR are used interchangeably.

04749-0-003

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Anal og Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

www.analog.com

AD5165

TABLE OF CONTENTS

Electrical Characteristics—100 kΩ Vers io n .................................. 3

Absolute Maximum Ratings............................................................ 5

Pin Configuration and Functional Descriptions.......................... 6

Typical Performance Characteristics............................................. 7

Tes t Ci r cu it s ..................................................................................... 11

3-Wire Digital Interface................................................................. 12

Theory of Operation ...................................................................... 13

Programming the Variable Resistor .........................................13

Programming the Potentiometer Divider............................... 14

3-Wire Serial Bus Digital Interface.......................................... 14

ESD Protection ........................................................................... 14

Terminal Voltage Operating Range.......................................... 14

Power-Up Sequence ................................................................... 14

Layout and Power Supply Bypassing ....................................... 15

Evaluation Board ........................................................................ 15

Outline Dimensions....................................................................... 16

Ordering Guide .......................................................................... 16

REVISION HISTORY

4/04—Revision 0: Initial Version

Rev. 0 | Page 2 of 16

AD5165

ELECTRICAL CHARACTERISTICS—100 kΩ VERSION

VDD = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; –40°C < TA < +125°C; unless otherwise noted.

Table 1.

Parameter Symbol Conditions Min Typ

DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity

2

R-DNL RWB, V
Resistor Integral Nonlinearity2 R-INL RWB, V
Nominal Resistor Tolerance
Resistance Temperature Coefficient (∆RAB/RAB)/∆Tx10
Wiper Resistance R

3

∆RAB/R

W

AB

TA = 25°C −20 +20 %

6

V

= V

AB

VDD = 2.7 V/5.5 V 85/50 150/120 Ω

= no connect

A

= no connect

A

, wiper = no connect 35 ppm/°C

DD

−1 ±0.1 +1 LSB

−2 ±0.25 +2 LSB

DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE
Resolution N 8 Bits
Differential Nonlinearity

4

DNL −1 ±0.1 +1 LSB
Integral Nonlinearity4 INL −1 ±0.3 +1 LSB
Voltage Divider Temperature

(∆V

W/VW

)/∆Tx10

6

Code = 0x80 15 ppm/°C

Coefficient
Full-Scale Error V
Zero-Scale Error V

WFSE

WZSE

Code = 0xFF −0.5 −0.3 0 LSB

Code = 0x00 0 0.1 0.5 LSB
RESISTOR TERMINALS
Voltage Range
Capacitance6 A, B C

5

V

A,B,W

A,B

GND V

f = 1 MHz, measured to GND,

90 pF

Code = 0x80
Capacitance6 W C

W

f = 1 MHz, measured to GND,

95 pF

Code = 0x80
Common-Mode Leakage I

CM

VA = VB = VDD/2 1 nA
DIGITAL INPUTS AND OUTPUTS
Input Logic High V
Input Logic Low V
Input Capacitance

6

IH

IL

C

IL

VDD = 2.7 V to 5.5 V 1.8 V

VDD = 2.7 V to 5.5 V 0.6 V

5 pF
POWER SUPPLIES
Power Supply Range V
Supply Current I

DD RANGE

DD

2.7 5.5 V

Digital inputs = 0 V or V

DD

0.05 1 µA
VDD = 2.7 V, digital inputs = 1.8 V 10 µA
VDD = 5 V, digital inputs = 1.8 V 500 µA
Power Dissipation
Power Supply Sensitivity PSS

7

P

DISS

Digital inputs = 0 V or V

= +5 V ± 10%,

V

DD

DD

5.5 µW

±0.001 ±0.005 %/%

Code = Midscale

DYNAMIC CHARACTERISTICS

6, 8

Bandwidth −3 dB BW Code = 0x80 55 kHz
Total Harmonic Distortion THD
VW Settling Time t

S

W

VA =1 V rms, VB = 0 V, f = 1 kHz, 0.05 %
VA = 5 V, VB = 0 V,

2 µs

±1 LSB error band

Resistor Noise Voltage Density e

N_WB

RWB = 50 kΩ 28 nV/√Hz

1

Typical specifications represent average readings at +25°C and VDD = 5 V.

2

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.

3

VAB = VDD, wiper (VW) = no connect.

4

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.

5

Resistor terminals A, B, and W have no limitations on polarity with respect to each other.

6

Guaranteed by design and not subject to production test.

7

P

is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

DISS

8

All dynamic characteristics use VDD = 5 V.

1

Max Unit

DD

V

Rev. 0 | Page 3 of 16

AD5165

TIMING CHARACTERISTICS—100 kΩ VERSION

VDD = +5 V ± 10%, or +3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C; unless otherwise noted.

Table 2.

Parameter Symbol Conditions Min Typ

3-WIRE INTERFACE TIMING CHARACTERISTICS
Clock Frequency f
Input Clock Pulse Width tCH, t
Data Setup Time t
Data Hold Time t
CS Setup Time t
CS Low Pulse Width t
CLK Fall to CS Rise Hold Time t
CLK Fall to CS Fall Hold Time t
CS Fall to Clock Rise Setup t

1

Typical specifications represent average readings at +25°C and VDD = 5 V.

2

Guaranteed by design and not subject to production test.

3

All dynamic characteristics use VDD = 5 V.

4

See and for location of measured values. All input control voltages are specified with tFigure 34 Figure 35

level of 1.5 V.

2, , 3 4

(specifications apply to all parts)
= 1/( tCH+ tCL)

CLK

CL

DS

DH

CSS

CSW

CSH0

CSH1

CS1

Clock level high or low 20 ns
5 ns
5 ns
15 ns
40 ns
0 ns
0 ns
10 ns

= tF = 2 ns (10% to 90% of 3 V) and timed from a voltage

R

1

Max Unit

25 MHz

Rev. 0 | Page 4 of 16

AD5165

ABSOLUTE MAXIMUM RATINGS

JMAX

− TA)/θJA.

1, 2

DD

±20 mA

2

±5 mA
±5 mA

) 150°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

TA = +25°C, unless otherwise noted.

Table 3.

Parameter Value

VDD to GND –0.3 V to +7 V
VA, VB, VW to GND V
Maximum Current

I

, IWA Pulsed

WB

Continuous (RWB ≤ 1 kΩ, A open)

I

WB

IWA Continuous (R

≤ 1 kΩ, B open)2

WA

Digital Inputs and Output Voltage to GND 0 V to +7 V
Operating Temperature Range –40°C to +125°C
Maximum Junction Temperature (T
Storage Temperature –65°C to +150°C
Lead Temperature (Soldering, 10 – 30 sec) 245°C
Thermal Resistance2 θJA: TSOT-8 200°C/W

1

Maximum terminal current is bounded by the maximum current handling
of the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.

2

Package power dissipation = (T

JMAX

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 5 of 16