Analog Devices AD5161 Datasheet

A

256-Position SPI/I2C Selectable

FEATURES

256-position
End-to-end resistance 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Compact MSOP-10 (3 mm × 4.9 mm) package
Pin selectable SPI/I
Extra package address decode pin AD0
Full read/write of wiper register
Power-on preset to midscale
Single supply 2.7 V to 5.5 V
Low temperature coefficient 45 ppm/°C
Low power, I
Wide operating temperature –40°C
SDO output allows multiple device daisy-chaining
Evaluation board available

APPLICATIONS

Mechanical potentiometer replacement in new designs
Transducer adjustment of pressure, temperature, position,

chemical, and optical sensors
RF amplifier biasing
Automotive electronics adjustment
Gain control and offset adjustment

GENERAL OVERVIEW

The AD5161 provides a compact 3 mm × 4.9 mm packaged
solution for 256-position adjustment applications. These devices
perform the same electronic adjustment function as mechanical
potentiometers or variable resistors, with enhanced resolution,
solid-state reliability, and superior low temperature coefficient
performance.

The wiper settings are controllable through a pin selectable SPI

2

C compatible digital interface, which can also be used to

or I
read back the wiper register content. When the SPI mode is
used, the device can be daisy-chained (SDO to SDI), allowing
several parts to share the same control lines. In the I
address pin AD0 can be used to place up to two devices on the
same bus. In this same mode, command bits are available to
reset the wiper position to midscale or to shut down the device
into a state of zero power consumption.

Operating from a 2.7 V to 5.5 V power supply and consuming
less than 5 µA allows for usage in portable battery-operated
applications.

2

C compatible interface

= 8 µA

DD

to +125°C

2

C mode,

Digital Potentiometer

AD5161

FUNCTIONAL BLOCK DIAGRAM

SDO/NCV

DD

SDI/SDA

CLK/SCL

DIS

CS/AD0

SPI OR I2C

INTERFACE

WIPER

REGISTER

GND

Figure 1.

PIN CONFIGURATION

10

9

8

7

6

W

V

DD

DIS

GND

CLK/SCL

CS/ADO

SDO/NC

SDI/SD

1

A

2

B

3

4

5

AD5161

TOP VIEW

(Not to Scale)

Figure 2.

Note:
The terms digital potentiometer, VR, and RDAC are used interchangeably.

Purchase of licensed I2C components of Analog Devices or one of its sublicensed
Associated Companies conveys a license for the purchaser under the Philips I
Patent Rights to use these components in an I
conforms to the I

2

C Standard Specification as defined by Philips.

2

C system, provided that the system

A

W

B

2

C

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

AD5161

TABLE OF CONTENTS

Electrical Characteristics—5 kΩ Version ...................................... 3

Level Shifting for Bidirectional Interface................................ 17

Electrical Characteristics—10 kΩ, 50 kΩ, 100 kΩ Versions ....... 4

Timing Characteristics—5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ Versions 5

Absolute Maximum Ratings1.......................................................... 6

Typical Performance Characteristics ............................................. 7

Test Circuits..................................................................................... 11

SPI Interface .................................................................................... 12

I2C Interface..................................................................................... 13

Operation......................................................................................... 14

Programming the Variable Resistor......................................... 14

Programming the Potentiometer Divider............................... 15

Pin Selectable Digital Interface................................................. 15

REVISION HISTORY

Revision 0: Initial Version

ESD Protection ........................................................................... 17

Terminal Voltage Operating Range.......................................... 17

Power-Up Sequence ................................................................... 17

Layout and Power Supply Bypassing ....................................... 17

Pin Configuration and Function Descriptions........................... 18

Pin Configuration ...................................................................... 18

Pin Function Descriptions ........................................................ 18

Outline Dimensions....................................................................... 19

Ordering Guide .......................................................................... 19

ESD Caution................................................................................ 19

Rev. 0 | Page 2 of 20

AD5161

ELECTRICAL CHARACTERISTICS—5 kΩ VERSION

(VDD = 5 V ± 10%, or 3 V ± 10%; VA = +VDD; VB = 0 V; –40°C < TA < +125°C; unless otherwise noted.)

Table 1.

Parameter Symbol Conditions Min Typ1 Max Unit

DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2 R-DNL RWB, V
Resistor Integral Nonlinearity2 R-INL RWB, V
Nominal Resistor Tolerance3 ∆RAB T
Resistance Temperature Coefficient ∆RAB/∆T VAB = VDD, Wiper = no connect 45 ppm/°C
Wiper Resistance RW 50 120 Ω
DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs)
Resolution N 8 Bits
Differential Nonlinearity4 DNL –1.5 ±0.1 +1.5 LSB
Integral Nonlinearity4 INL –1.5 ±0.6 +1.5 LSB
Voltage Divider Temperature Coefficient ∆VW/∆T Code = 0x80 15 ppm/°C
Full-Scale Error V
Zero-Scale Error V

Code = 0xFF –6 –2.5 0 LSB

WFSE

Code = 0x00 0 +2 +6 LSB

WZSE

RESISTOR TERMINALS
Voltage Range5 V
Capacitance6 A, B C

GND VDD V

A,B,W

A,B

Capacitance6 W CW

Shutdown Supply Current7 I

DD_SD

Common-Mode Leakage ICM V
DIGITAL INPUTS AND OUTPUTS
Input Logic High VIH 2.4 V
Input Logic Low VIL 0.8 V
Input Logic High VIH V
Input Logic Low VIL V
Input Current IIL V
Input Capacitance6 C

5 pF

IL

POWER SUPPLIES
Power Supply Range V

2.7 5.5 V

DD RANGE

Supply Current IDD V
Power Dissipation8 P

V

DISS

Power Supply Sensitivity PSS

DYNAMIC CHARACTERISTICS

6, 9

Bandwidth –3dB BW_5K RAB = 5 kΩ, Code = 0x80 1.2 MHz
Total Harmonic Distortion THDW VA = 1 V rms, VB = 0 V, f = 1 kHz 0.05 %
VW Settling Time tS

Resistor Noise Voltage Density e

RWB = 2.5 kΩ, RS = 0 6 nV/√Hz

N_WB

= no connect –1.5 ±0.1 +1.5 LSB

A

= no connect –4 ±0.75 +4 LSB

A

= 25°C –30 +30 %

A

f = 1 MHz, measured to GND,

45 pF

Code = 0x80
f = 1 MHz, measured to GND,

60 pF

Code = 0x80
VDD = 5.5 V 0.01 1 µA

= VB = VDD/2 1 nA

A

= 3 V 2.1 V

DD

= 3 V 0.6 V

DD

= 0 V or 5 V ±1 µA

IN

= 5 V or VIL = 0 V 3 8 µA

IH

= 5 V or VIL = 0 V, VDD = 5 V 0.2 mW

IH

= +5 V ± 10%,

∆V

DD

±0.02 ±0.05 %/%

Code = Midscale

= 5 V, VB = 0 V, ±1 LSB error

V

A

1 µs

band

Rev. 0 | Page 3 of 20

AD5161

ELECTRICAL CHARACTERISTICS—10 kΩ, 50 kΩ, 100 kΩ VERSIONS

(VDD = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; –40°C < TA < +125°C; unless otherwise noted.)

Table 2.

Parameter Symbol Conditions Min Typ1 Max Unit

DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2 R-DNL RWB, V
Resistor Integral Nonlinearity2 R-INL RWB, V
Nominal Resistor Tolerance3 ∆RAB T
Resistance Temperature Coefficient ∆RAB/∆T

Wiper Resistance RW V
DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs)
Resolution N 8 Bits
Differential Nonlinearity4 DNL –1 ±0.1 +1 LSB
Integral Nonlinearity4 INL –1 ±0.3 +1 LSB
Voltage Divider Temperature Coefficient ∆VW/∆T Code = 0x80 15 ppm/°C
Full-Scale Error V
Zero-Scale Error V

Code = 0xFF –3 –1 0 LSB

WFSE

Code = 0x00 0 1 3 LSB

WZSE

RESISTOR TERMINALS
Voltage Range5 V
Capacitance6 A, B C

GND VDD V

A,B,W

A,B

Capacitance6 W CW

Shutdown Supply Current7 I

DD_SD

Common-Mode Leakage ICM V
DIGITAL INPUTS AND OUTPUTS
Input Logic High VIH 2.4 V
Input Logic Low VIL 0.8 V
Input Logic High VIH V
Input Logic Low VIL V
Input Current IIL V
Input Capacitance6 C

5 pF

IL

POWER SUPPLIES
Power Supply Range V

2.7 5.5 V

DD RANGE

Supply Current IDD V
Power Dissipation8 P

DISS

Power Supply Sensitivity PSS

DYNAMIC CHARACTERISTICS

6, 9

Bandwidth –3dB BW

Total Harmonic Distortion THDW

VW Settling Time (10 kΩ/50 kΩ/100 kΩ) tS

Resistor Noise Voltage Density e

R

N_WB

= no connect –1 ±0.1 +1 LSB

A

= no connect –2 ±0.25 +2 LSB

A

= 25°C –30 +30 %

A

V

AB

= VDD,

45 ppm/°C

Wiper = no connect

= 5 V 50 120 Ω

DD

f = 1 MHz, measured to

45 pF

GND, Code = 0x80
f = 1 MHz, measured to

60 pF

GND, Code = 0x80
VDD = 5.5 V 0.01 1 µA

= VB = VDD/2 1 nA

A

= 3 V 2.1 V

DD

= 3 V 0.6 V

DD

= 0 V or 5 V ±1 µA

IN

= 5 V or VIL = 0 V 3 8 µA

IH

= 5 V or VIL = 0 V,

V

IH

V

= 5 V

DD

= +5 V ± 10%,

∆V

DD

0.2 mW

±0.02 ±0.05 %/%

Code = Midscale

= 10 kΩ/50 kΩ/100 kΩ,

R

AB

600/100/40 kHz

Code = 0x80

=1 V rms, VB = 0 V,

V

A

f = 1 kHz, R

= 5 V, VB = 0 V,

V

A

= 10 kΩ

AB

0.05 %

2 µs

±1 LSB error band

= 5 kΩ, RS = 0 9 nV/√Hz

WB

Rev. 0 | Page 4 of 20

AD5161

TIMING CHARACTERISTICS—5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ VERSIONS

(VDD = +5V ± 10%, or +3V ± 10%; VA = VDD; VB = 0 V; –40°C < TA < +125°C; unless otherwise noted.)

Table 3.

Parameter Symbol Conditions Min Typ1 Max Unit

SPI INTERFACE TIMING CHARACTERISTICS
Clock Frequency f
Input Clock Pulsewidth tCH, tCL Clock level high or low 20 ns
Data Setup Time tDS 5 ns
Data Hold Time tDH 5 ns

CS Setup Time
CS High Pulsewidth
CLK Fall to CS Fall Hold Time
CLK Fall to CS Rise Hold Time
CS Rise to Clock Rise Setup
I2C INTERFACE TIMING CHARACTERISTICS

SCL Clock Frequency f
t

Bus Free Time between STOP and START t1 1.3 µs

BUF

t

t
t
t
t
t

Hold Time (Repeated START) t2

HD;STA

Low Period of SCL Clock t3 1.3 µs

LOW

High Period of SCL Clock t4 0.6 50 µs

HIGH

Setup Time for Repeated START Condition t5 0.6 µs

SU;STA

Data Hold Time t6 0.9 µs

HD;DAT

Data Setup Time t7 100 ns

SU;DAT

tF Fall Time of Both SDA and SCL Signals t8 300 ns
tR Rise Time of Both SDA and SCL Signals t9 300 ns
t

Setup Time for STOP Condition t10 0.6 µs

SU;STO

NOTES

1

Typical specifications represent average readings at +25°C and VDD = 5 V.

2

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.

3

VAB = VDD, Wiper (VW) = no connect.

4

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.

DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.

5

Resistor terminals A, B, W have no limitations on polarity with respect to each other.

6

Guaranteed by design and not subject to production test.

7

Measured at the A terminal. The A terminal is open circuited in shutdown mode.

8

P

is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

DISS

9

All dynamic characteristics use VDD = 5 V.

10

See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage

level of 1.5 V.

11

See timing diagrams for locations of measured values.

6, 10

(Specifications Apply to All Parts)

CLK

t

15 ns

CSS

40 ns

t

CSW

t

0 ns

CSH0

t

0 ns

CSH1

t

10 ns

CS1

6, 11

(Specifications Apply to All Parts)

400 kHz

SCL

After this period, the first clock pulse is

0.6 µs

25 MHz

generated.

Rev. 0 | Page 5 of 20

AD5161

ABSOLUTE MAXIMUM RATINGS1

(TA = +25°C, unless otherwise noted.)

Table 4

Parameter Value

VDD to GND –0.3 V to +7 V
VA, VB, VW to GND VDD

1

I

±20 mA

MAX

Digital Inputs and Output Voltage to GND 0 V to +7 V
Operating Temperature Range –40°C to +125°C
Maximum Junction Temperature (T

) 150°C

JMAX

Storage Temperature –65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C
Thermal Resistance2 θJA: MSOP-10 200°C/W

NOTES

1

Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.

2

Package power dissipation = (T

JMAX

– TA)/θJA.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Rev. 0 | Page 6 of 20