256-position
End-to-end resistance 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Compact SOT-23-8 (2.9 mm × 3 mm) package
SPI compatible interface
Power-on preset to midscale
Single supply 2.7 V to 5.5 V
Low temperature coefficient 45 ppm/°C
Low power, I
Wide operating temperature –40°C
Evaluation board available
APPLICATIONS
Mechanical potentiometer replacement in new designs
Transducer adjustment of pressure, temperature, position,
chemical, and optical sensors
RF amplifier biasing
Automotive electronics adjustment
Gain control and offset adjustment
GENERAL OVERVIEW
The AD5160 provides a compact 2.9 mm × 3 mm packaged
solution for 256-position adjustment applications. These devices
perform the same electronic adjustment function as mechanical
potentiometers or variable resistors, with enhanced resolution,
solid-state reliability, and superior low temperature coefficient
performance.
The wiper settings are controllable through an SPI compatible
digital interface. The resistance between the wiper and either
end point of the fixed resistor varies linearly with respect to the
digital code transferred into the RDAC latch.
= 8 µA
DD
to +125°C
Digital Potentiometer
AD5160
FUNCTIONAL BLOCK DIAGRAM
V
DD
CS
SDI
CLK
SPI INTERFACE
WIPER
REGISTER
GND
Figure 1.
PIN CONFIGURATION
V
GND
CLK
W
DD
1
2
AD5160
3
TOP VIEW
(Not to Scale)
4
Figure 2.
A
8
B
7
6
CS
5
SDI
A
Operating from a 2.7 V to 5.5 V power supply and consuming
less than 5 µA allows for usage in portable battery-operated
applications.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
Note:
The terms digital potentiometer, VR, and RDAC are used interchangeably.
(VDD = 5 V ± 10%, or 3 V ± 10%; VA = +VDD; VB = 0 V; –40°C < TA < +125°C; unless otherwise noted.)
Table 1.
Parameter Symbol Conditions Min Typ1 Max Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2 R-DNL RWB, V
Resistor Integral Nonlinearity2 R-INL RWB, V
Nominal Resistor Tolerance3 ∆RAB T
Resistance Temperature Coefficient ∆RAB/∆T VAB = VDD, Wiper = no connect 45 ppm/°C
Wiper Resistance RW 50 120 Ω
DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs)
Resolution N 8 Bits
Differential Nonlinearity4 DNL –1.5 ±0.1 +1.5 LSB
Integral Nonlinearity4 INL –1.5 ±0.6 +1.5 LSB
Voltage Divider Temperature Coefficient ∆VW/∆T Code = 0x80 15 ppm/°C
Full-Scale Error V
Zero-Scale Error V
Code = 0xFF –6 –2.5 0 LSB
WFSE
Code = 0x00 0 +2 +6 LSB
WZSE
RESISTOR TERMINALS
Voltage Range5 V
Capacitance6 A, B C
GND VDD V
A,B,W
A,B
Capacitance6 W CW
Shutdown Supply Current7 I
DD_SD
Common-Mode Leakage ICM V
DIGITAL INPUTS AND OUTPUTS
Input Logic High VIH 2.4 V
Input Logic Low VIL 0.8 V
Input Logic High VIH V
Input Logic Low VIL V
Input Current IIL V
Input Capacitance6 C
5 pF
IL
POWER SUPPLIES
Power Supply Range V
2.7 5.5 V
DD RANGE
Supply Current IDD V
Power Dissipation8 P
V
DISS
Power Supply Sensitivity PSS
DYNAMIC CHARACTERISTICS
6, 9
Bandwidth –3dB BW_5K RAB = 5 kΩ, Code = 0x80 1.2 MHz
Total Harmonic Distortion THDW VA = 1 V rms, VB = 0 V, f = 1 kHz 0.05 %
VW Settling Time tS
(VDD = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; –40°C < TA < +125°C; unless otherwise noted.)
Table 2.
Parameter Symbol Conditions Min Typ1 Max Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2 R-DNL RWB, V
Resistor Integral Nonlinearity2 R-INL RWB, V
Nominal Resistor Tolerance3 ∆RAB T
Resistance Temperature Coefficient ∆RAB/∆T
Wiper Resistance RW V
DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs)
Resolution N 8 Bits
Differential Nonlinearity4 DNL –1 ±0.1 +1 LSB
Integral Nonlinearity4 INL –1 ±0.3 +1 LSB
Voltage Divider Temperature Coefficient ∆VW/∆T Code = 0x80 15 ppm/°C
Full-Scale Error V
Zero-Scale Error V
Code = 0xFF –3 –1 0 LSB
WFSE
Code = 0x00 0 1 3 LSB
WZSE
RESISTOR TERMINALS
Voltage Range5 V
Capacitance6 A, B C
GND VDD V
A,B,W
A,B
Capacitance6 W CW
Shutdown Supply Current7 I
DD_SD
Common-Mode Leakage ICM V
DIGITAL INPUTS AND OUTPUTS
Input Logic High VIH 2.4 V
Input Logic Low VIL 0.8 V
Input Logic High VIH V
Input Logic Low VIL V
Input Current IIL V
Input Capacitance6 C
(VDD = +5V ± 10%, or +3V ± 10%; VA = VDD; VB = 0 V; –40°C < TA < +125°C; unless otherwise noted.)
Table 3.
Parameter Symbol Conditions Min Typ1 Max Unit
SPI INTERFACE TIMING CHARACTERISTICS
Clock Frequency f
Input Clock Pulsewidth tCH, tCL Clock level high or low 20 ns
Data Setup Time tDS 5 ns
Data Hold Time tDH 5 ns
CS Setup Time
CS High Pulsewidth
CLK Fall to CS Fall Hold Time
CLK Fall to CS Rise Hold Time
CS Rise to Clock Rise Setup
NOTES
1
Typical specifications represent average readings at +25°C and VDD = 5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3
VAB = VDD, Wiper (VW) = no connect.
4
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
Measured at the A terminal. The A terminal is open circuited in shutdown mode.
8
P
is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
DISS
9
All dynamic characteristics use VDD = 5 V.
10
See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage
level of 1.5 V.
6, 10
(Specifications Apply to All Parts)
CLK
t
15 ns
CSS
40 ns
t
CSW
t
0 ns
CSH0
t
0 ns
CSH1
t
10 ns
CS1
25 MHz
ABSOLUTE MAXIMUM RATINGS1
(TA = +25°C, unless otherwise noted.)
Table 4.
Parameter Value
VDD to GND –0.3 V to +7 V
VA, VB, VW to GND VDD
1
I
±20 mA
MAX
Digital Inputs and Output Voltage to GND 0 V to +7 V
Operating Temperature Range –40°C to +125°C
Maximum Junction Temperature (T
) 150°C
JMAX
Storage Temperature –65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C
Thermal Resistance2 θJA: MSOP-10 230°C/W
NOTES
1
Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2
Package power dissipation = (T
– TA)/θJA.
JMAX
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 5 of 16
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