Analog Devices AD261BND-4, AD261BND-3, AD261BND-2, AD261BND-1, AD261BND-0 Datasheet

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TYPICAL MODEL

(AD261-2)

SYSTEM

FIELD

+5V dc

5Vdc RTN

+5V dc

5Vdc RTN

THREE-

STATE

LATCH

LINE 0

+5V dc

FLD

5V RTN

FLD

ENABLE

FLD

5V RTN

SYS

+5V dc

SYS

ENABLE

SYS

THREE-

STATE

LATCH

LINE 1

THREE-

STATE

LATCH

LINE 2

LATCH

THREE-

STATE

LINE 4

LINE 3

LATCH

THREE-

STATE

High Speed, Logic Isolator

AD261

FEATURES Isolation Test Voltage: To 3.5 kV rms Five Isolated Logic Lines: Available in Six I/O Configurations Logic Signal Bandwidth: 20 MHz (min) CMV Transient Immunity: 10 kV/ms min Waveform Edge Transmission Symmetry: 61 ns Field and System Output Enable/Three-State Functions Performance Rated Over –258C to +858C UL1950, IEC950, EN60950 Certification (VDE, CE, Pending)

APPLICATIONS PLC/DCS Analog Input and Output Cards Communications Bus Isolation General Data Acquisition Applications IGBT Motor Drive Controls High Speed Digital I/O Ports

GENERAL DESCRIPTION

The AD261 is designed to isolate five digital control signals to/from a microcontroller and its related field I/O components. Six models allow all I/O combinations from five input lines to five output lines, including combinations in between. Every AD261 effectively replaces up to five opto-isolators.

Each line of the AD261 has a bandwidth of 20MHz (min) with a propagation delay of only 14 ns, which allows for extremely fast data transmission. Output waveform symmetry is maintained to within ±1 ns of the input so the AD261 can be used to accurately isolate time-based PWM signals.

All field or system output pins of the AD261 can be set to a high resistance three-state level by use of the two enable pins. A field output three-stated offers a convenient method of presetting logic levels at power-up by use of pull-up/down resistors. System side outputs being three-stated allows for easy multiplexing of multiple AD261s.

The isolation barrier of the AD261 B Grade is 100% tested as high as 3.5 kV rms (system to field). The barrier design also provides excellent common-mode transient immunity from 10 kV/µs common-mode voltage excursions of field side termi- nals relative to the system side, with no false output triggering on either side.

Each output is updated within nanoseconds by input logic transitions, the AD261 also has a continuous output update feature that automatically updates each output based on the dc level of the input. This guarantees the output is always valid 10µs after a fault condition or after the power-up reset interval.

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

Six Isolated Logic Line I/O Configurations Available: The AD261 is available in six pin-compatible versions of I/O configurations to meet a wide variety of requirements.

Wide Bandwidth with Minimal Edge Error: The AD261 affords extremely fast isolation of logic signals due to its 20MHz bandwidth and 14 ns propagation delay. It maintains a waveform input-to-output edge transition error of typically less than ±1 ns (total) for positive vs. negative transition.

3.5 kV rms Test Voltage Isolation Rating: The AD261 B Grade is rated to operate at 1.25 kV rms and is 100% production tested at 3.5 kV rms, using a standard ADI test method.

High Transient Immunity: The AD261 rejects commonmode transients slewing at up to 10 kV/µs without false trigger- ing or damage to the device.

(Continued on page 5)

REV. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1997

AD261–SPECIFICA TIONS

(Typical at TA = +258C, +5 V dc

, +5 V dc

SYS

, tRR = 50 ns max unless otherwise noted)

FLD

Parameter Conditions Min Typ Max Units

INPUT CHARACTERISTICS

Threshold Voltage

Positive Transition (V

Negative Transition (V Hysteresis Voltage (V Input Capacitance (C

) +5 V dc

T+

+5 V dc

) +5 V dc

T–

+5 V dc

) +5 V dc

+5 V dc

) 5pF

= 4.5 V 2.0 2.7 3.15 V

SYS

= 5.5 V 3.0 3.2 4.2 V

SYS

= 4.5 V 0.9 1.8 2.2 V

SYS

= 5.5 V 1.2 2.2 3.0 V

SYS

= 4.5 V 0.4 0.9 1.4 V

SYS

= 5.5 V 0.5 1.0 1.5 V

SYS

Input Bias Current (IIN) Per Input 0.5 µA

OUTPUT CHARACTERISTICS

Output Voltage

High Level (VOH) +5 V dc

Low Level (V Output Three-State Leakage Current ENABLE

DYNAMIC RESPONSE

Max Logic Signal Frequency (f Waveform Edge Symmetry Error (t Logic Edge Propagation Delay (t Minimum Pulsewidth (t Max Output Update Delay on Fault or After

Power-Up Reset Interval (≈ 30 µs)

ISOLATION BARRIER RATING

Operating Isolation Voltage (V Isolation Rating Test Voltage (V

+5 V dc

) +5 V dc

+5 V dc

(Refer to Figure 2)

PWMIN

) 50% Duty Cycle, +5 V dc

MIN

PHL

ERROR

, t

PLH

)1425ns

) 25 ns

) AD261A 375 V rms

CMV

CMV TEST

AD261B 1250 V rms

)

AD261A 1750 V rms

PHL

= 4.5 V, |IO| = 0.02 mA 4.4 V

SYS

= 4.5 V, |IO| = 4 mA 3.7 V

SYS

= 4.5 V, |IO| = 0.02 mA 0.1 V

SYS

= 4.5 V, |IO| = 4 mA 0.4 V

SYS

@ Logic Low/High Level Respectively 0.5 µA

SYS/FLD

= 5 V 20 MHz

vs. t

PLH

SYS

±1ns

12 µs

AD261B 3500 V rms

Transient Immunity (V

TRANSIENT

Isolation Mode Capacitance (C Capacitive Leakage Current (I

) 10,000 V/µs

) Total Capacitance, All Lines 9 15 pF

ISO

) 240 V rms @ 60 Hz 2 µA rms

LEAD

POWER SUPPLY

Supply Voltage (+5 V dc

and +5 V dc

SYS

) Rated Performance 4.5 5.5 V dc

FLD

Operating 4.0 5.75 V dc

Power Dissipation Capacitance Effective, per Input, Either Side 8 pF

Effective per Output, Either Side—No Load 28 pF Quiescent Supply Current Each, +5 V dc Supply Current All Lines @ 10 MHz (Sum of +5 V dc

TEMPERATURE RANGE

Rated Performance (T Storage (T

NOTES

For best performance, bypass +5 V dc supplies to com., at or near the device (0.01 µF). +5 V dc supplies are also internally bypassed with 0.05 µF.

As the supply voltage is applied to either side of the AD261, the internal circuitry will go into a power-up reset mode (all lines disabled) for about 30 µs after the point where +5 V dc

“Operating” isolation voltage is derived from the Isolation Test Voltage in accordance with such methods as found in VDE-0883 wherein a device will be “hi-pot” tested at twice the operating voltage, plus one thousand volts. Partial discharge testing, with an acceptance threshold of 80 pC of discharge may be considered the same as a hi-pot test (but nondestructive).

Partial Discharge at 80 pC THLD.

Supply Current will increase slightly, but otherwise the unit will function within specification to – 40 °C.

Specifications are subject to change without notice.

) –40 +85 °C

STG

SYS & FLD

)

passes above 3.3 V.

SYS & FLD

)18 mA

SYS & FLD

4mA

–25 +85 °C

–2–

REV. 0

AD261

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

Parameter Conditions Min Typ Max Units

Supply Voltage (+5 V dc DC Input Voltage (V DC Output Voltage (V

SYS & FLD

IN MAX

OUT MAX

Clamp Diode Input Current (I Clamp Diode Output Current (I Output DC Current, per Pin (I DC Current, V Storage Temperature (T

or GND (ICC or I

STG

Lead Temperature (Soldering, 10 sec) +300 °C Electrostatic Protection (V

*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device

at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability.

) –0.5 +6.0 V

) Referred to +5 V dc

SYS & FLD

) Referred to +5 V RTN

) For VI < –0.5 V or VI > 5 V RTN

) For VO < –0.5 V or VO > 5 V RTN

) –25 +25 mA

OUT

) –50 +50 mA

GND

and 5 V RTN

SYS & FLD

and 5 V dc

SYS & FLD

SYS & FLD SYS & FLD

Respectively –0.5 +0.5 V Respectively –0.5 +0.5 V

+0.5 V –25 +25 mA

) –40 +85 °C

) Per MIL-STD-883, Method 3015 4.5 5

ESD

I/O CONFIGURATIONS AVAILABLE

PIN CONFIGURATION

The AD261 is available in several configurations. The choice of model is determined by the desired number of input vs. output lines. All models have identical footprints with the power and enable pins always being in the same locations.

PIN FUNCTION DESCRIPTIONS

Pin Mnemonic Function

SYSTEM

4 5

ENABLE

SYS

+5V dc

7 8

5V RTN

SYS

1–5* S0 Through S4 Digital Xmt or Rcv from F0 Through F4 6 ENABLE 7 +5 V dc

SYS

8 5 V RTN

SYS

System Output Enable/Three-State

SYS

System Power Supply (+5 V dc Input) System Power Supply Common

BOTTOM VIEW

9–14 Not Present On Unit 15 5 V RTN 16 +5 V dc

FLD

17 ENABLE 18–22* F0 Through F4 Digital Xmt or Rcv from S0 Through S4

*Function of pin determined by model. Refer to Table I.

Field Power Supply Common Field Power Supply (+5 V Input) Field Output Enable/Three-State

FLD

5V RTN

+5V dc

ENABLE

FLD FLD FLD

15 16 17

FIELD

F3 F4

ORDERING GUIDE

Model Isolation Package Package Number Description Ratings Description Option

AD261AND-0 0 Inputs, 5 Outputs 1.75 kV rms Plastic DIP ND-22A AD261AND-1 1 Input, 4 Outputs 1.75 kV rms Plastic DIP ND-22A AD261AND-2 2 Inputs, 3 Outputs 1.75 kV rms Plastic DIP ND-22A AD261AND-3 3 Inputs, 2 Outputs 1.75 kV rms Plastic DIP ND-22A AD261AND-4 4 Inputs, 1 Output 1.75 kV rms Plastic DIP ND-22A AD261AND-5 5 Inputs, 0 Outputs 1.75 kV rms Plastic DIP ND-22A

AD261BND-0 0 Inputs, 5 Outputs 3.5 kV rms Plastic DIP ND-22A AD261BND-1 1 Input, 4 Outputs 3.5 kV rms Plastic DIP ND-22A AD261BND-2 2 Inputs, 3 Outputs 3.5 kV rms Plastic DIP ND-22A AD261BND-3 3 Inputs, 2 Outputs 3.5 kV rms Plastic DIP ND-22A AD261BND-4 4 Inputs, 1 Output 3.5 kV rms Plastic DIP ND-22A AD261BND-5 5 Inputs, 0 Outputs 3.5 kV rms Plastic DIP ND-22A

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD261 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

REV. 0

–3–

AD261

AD261 CONFIGURATIONS

ENABLE

+5V dc

5V RTN

FLD

AD261-0

LATCH

D E

+5V dc

5V dc RTN

ENABLE

+5V dc

5V RTN

SYS

ENABLE

+5V dc

5V RTN

17 6

FLD

+5V dc

5V dc RTN

THREE-

STATE

THREE-

STATE

THREE-

STATE

THREE-

STATE

THREE-

STATE

LINE 0

LINE 1

LINE 2

LINE 3

LINE 4

SYSTEMFIELD

+5V dc

5V dc RTN

FIELD

THREE-

STATE

THREESTATE

THREE-

STATE

LATCH

D E

LATCH

D E

LINE 0

LINE 1

LINE 2

LINE 3

LINE 4

AD261-1

THREE-

STATE

THREE-

STATE

THREE-

STATE

THREE-

STATE

LATCH

D E

LINE 0

LINE 1

LINE 2

LINE 3

LINE 4

LATCH

THREE-

STATE

D E

THREESTATE

THREE-

STATE

LATCH

D E

LATCH

D E

LATCH

D E

LINE 0

LINE 1

LINE 2

LINE 3

LINE 4

AD261-2

LATCH

D E

LATCH

D E

LATCH

D E

THREE-

STATE

THREE-

STATE

5V dc RTN

SYSTEM

AD261-3

LATCH

D E

LATCH

D E

THREE-

STATE

THREE-

STATE

THREE-

STATE

+5V dc

ENABLE

+5V dc

5V RTN

SYS

ENABLE

+5V dc

5V RTN

FLD

+5V dc

5V dc RTN

FIELD

5V dc RTN

SYSTEM

+5V dc

ENABLE

+5V dc

5V RTN

SYS

–4–

ENABLE

+5V dc

5V RTN

17 6

FLD

+5V dc

FLD

5V dc RTN

FIELD

5V dc RTN

SYSTEM

+5V dc

ENABLE

+5V dc

5V RTN

SYS

REV. 0

AD261

AD261-5

SYSTEM

FIELD

+5V dc

5V dc RTN

+5V dc

5V dc RTN

17 6

+5V dc

FLD

5V RTN

FLD

ENABLE

FLD

5V RTN

SYS

+5V dc

SYS

ENABLE

SYS

LATCH

THREE-

STATE

LINE 4

LINE 3

LATCH

THREE-

STATE

LATCH

THREE-

STATE

LINE 2

LATCH

THREE-

STATE

LATCH

THREE-

STATE

LINE 0

LINE 1

AD261 CONFIGURATIONS

AD261-4

STATE

LATCH D E

LATCH D

LATCH

D E

THREE-

LINE 0

LINE 1

LINE 2

LINE 3

LINE 4

LATCH

THREE-

STATE

THREE-

STATE

THREE-

STATE

THREE-

STATE

D E

ENABLE

+5V dc

5V RTN

17 6

FLD

+5V dc

FLD

5V dc RTN

FIELD

5V dc RTN

SYSTEM

+5V dc

(Continued from page 1)

Field and System Enable Functions: Both the isolated and nonisolated sides of the AD261 have ENABLE pins that threestate all outputs. Upon reenabling these pins, all outputs are updated to reflect the current input logic level.

CE Certifiable: Simply by adding the external bypass capacitors at the supply pins, the AD261 can attain CE certification in most applications (to the EMC directive) and conformance to the low voltage (safety) directive is assured by the EN60950 certification.

Table I. Model Number and Pinout Function

Pin AD261-0 AD261-1 AD261-2 AD261-3 AD261-4 AD261-5

1 S0 (Xmt) S0 (Xmt) S0 (Xmt) S0 (Xmt) S0 (Xmt) S0 (Rcv) 2 S1 (Xmt) S1 (Xmt) S1 (Xmt) S1 (Xmt) S1 (Rcv) S1 (Rcv) 3 S2 (Xmt) S2 (Xmt) S2 (Xmt) S2 (Rcv) S2 (Rcv) S2 (Rcv) 4 S3 (Xmt) S3 (Xmt) S3 (Rcv) S3 (Rcv) S3 (Rcv) S3 (Rcv) 5 S4 (Xmt) S4 (Rcv) S4 (Rcv) S4 (Rcv) S4 (Rcv) S4 (Rcv) 6 ENABLE 7 +5 V dc 8 5 V RTN 9–14 Not Present 15 5 V RTN 16 +5 V dc 17 ENABLE 18 F0 (Rcv) F0 (Rcv) F0 (Rcv) F0 (Rcv) F0 (Rcv) F0 (Xmt) 19 F1 (Rcv) F1 (Rcv) F1 (Rcv) F1 (Rcv) F1 (Xmt) F1 (Xmt) 20 F2 (Rcv) F2 (Rcv) F2 (Rcv) F2 (Xmt) F2 (Xmt) F2 (Xmt) 21 F3 (Rcv) F3 (Rcv) F3 (Xmt) F3 (Xmt) F3 (Xmt) F3 (Xmt) 22 F4 (Rcv) F4 (Xmt) F4 (Xmt) F4 (Xmt) F4 (Xmt) F4 (Xmt)

SYS

FLD

*Pin function is the same on all models, as shown in the AD261-0 column.

REV. 0

***** ***** *****

*** * ***** *****

ENABLE

+5V dc

5V RTN

SYS

GENERAL ATTRIBUTES

The AD261 provides five HCMOS compatible isolated logic lines with ≥ 10 kV/µs common-mode transient immunity.

The case design and pin arrangement provides greater than 18 mm spacing between field and system side conductors, providing CSA/IS and IEC creepage spacing consistent with 750 V mains isolation.

The five unidirectional logic lines have six possible combinations of “ins” and “outs,” or transmitter/receiver pairs; hence there are six AD261 part configurations (see Table I).

Each 20 MHz logic line

has a Schmidt trigger input and a threestate output (on the other side of the isolation barrier) and 14 ns of propagation delay. A single enable pin on either side of the barrier causes all outputs on that side to go three-state and all inputs (driven pins) to ignore their inputs and retain their last known state.

Note: All unused logic inputs (1–5) should be tied either high or low, but not left floating.

Edge “fidelity,” or the difference in propagation time for rising and falling edges, is typically less than ± 1 ns.

Power consumption, unlike opto-isolators, is a function of operating frequency. Each logic line barrier driver requires about 160µA per MHz and each receiver 40 µA per MHz plus, of course, 4 mA total idle current (each side). The supply current diminishes slightly with increasing temperature (about –0.03%/°C).

The total capacitance spanning the isolation barrier is less than 10 pF.

The minimum period of a pulse that can be accurately coupled across the barrier is about 25 ns. Therefore the maximum square-wave frequency of operation is 20 MHz.

–5–

AD261

Logic information is sent across the barrier as “set-hi/set-lo” data that is derived from logic level transitions of the input. At power-up or after a fault condition, an output might not represent the state of the respective channel input to the isolator. An internal circuit operates in the background which interrogates all inputs about every 5 µs and in the absence of logic transitions, sends appropriate “set-hi” or “set-lo” data across the barrier.

Recovery time from a fault condition or at power-up is thus between 5 µs and 10 µs.

INPUT

OUTPUT

EFFECTIVE

CIRCUIT

MODEL

63%

CAPACITANCE

5pF

INPUT

PROPAGATION DELAY

BUFFER

= 100V x C

0.5ns – NO LOAD

= 5.5ns INTO 50pF

TOTAL DELAY =

= 14ns

DELAY LINE

14ns

TOTAL OUTPUT CAPACITANCE

Figure 2. Typical Timing and Delay Models

SCHMITT

TRIGGER

BUFFER

DATA IN

ENABLE

GATED

TRANSPARENT

LATCH

Figure 1. Simplified Block Diagram

POSITIVE GOING INPUT THRESHOLD

NEGATIVE GOING INPUT THRESHOLD

BUFFER

100V

= 13ns (NO LOAD), 18ns (50pF LOAD)

ISOLATION

DRIVER

5pF OUTPUT CAPACITANCE

3.5kV

BARRIER

CONTINUOUS UPDATE CIRCUIT

HYSTERESIS

RECEIVER

37%

DATA

OUTPUT BUFFER

OUT

ENABLE

C3212–8–10/97

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

22-Pin Plastic DIP

(ND-22A)

1.500 (38.1) MAX

SIDE VIEW

0.160 (4.06)

0.140 (3.56)

0.075 (1.91)

0.250 (6.35)

*CREEPAGE PATH (SUBTRACT APPROXIMATELY

0.079 (2mm) FOR SOLDER PAD RADII ON PC BOARD. THIS SPACING SUPPORTS THE INTRINSICALLY SAFE RATING OF 750V.

0.050 (1.27)

PIN 1

SYSTEM

BOTTOM

VIEW

0.738* (18.75)

0.650 (16.51)

0.020 3 0.010

(0.508 3 0.254)

16 PLACES

FIELD

–6–

0.550 (13. 97) MAX

0.440 MAX

0.100 (2.54)

END VIEW

0.350 (8.89)

(11.18)

PRINTED IN U.S.A.

0.050 (1.27)

REV. 0

Analog Devices AD261BND-4, AD261BND-3, AD261BND-2, AD261BND-1, AD261BND-0 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

ORDERING GUIDE

AD261 CONFIGURATIONS

GENERAL ATTRIBUTES