Analog Devices AD1986 Datasheet
AC ’97 SoundMAX CODEC
FEATURES
AC `97 2.3 COMPLIANT FEATURES
6 DAC channels for 5.1 surround
S/PDIF output
Integrated headphone amplifiers
Variable rate audio
Double rate audio (F
Greater than 90 dB dynamic range
20-bit resolution on all DACs
20-bit resolution on all ADCs
Line-level mono phone input
High quality CD input
Selectable MIC input w/preamp
AUX and line-in stereo inputs
External amplifier power down (EAPD)
Power management modes
Jack sensing and device identification
48-pin LQFP package
= 96 kHz)
s
AD1986
ENHANCED FEATURES
Integrated parametric equalizer
Stereo microphone with up to 30 dB gain boost
Integrated PLL for system clocking
Variable sample rate: 7 kHz to 96 kHz
7 kHz to 48 kHz in 1 Hz increments
96 kHz for double rate audio
Jack sense with auto topology switching
Jack presence detection on up to 8 jacks
Three software-controlled VREF_OUT signals
Software-enabled outputs for jack sharing
Auto-down mix and channel spreading
Microphone-to-mono output
Stereo microphone pass-through to mixer
Built-in microphone/center/LFE/line-in sharing
Built-in SURROUND/LINE_IN sharing
Center/LFE line swapping
Microphone swapping
Reduced support component count
General purpose digital output pin (GPO)
Separate LINE_OUT and HP_OUT pins
Headphone drivers on LINE_OUT and HP_OUT pins
Independent headphone/LINE_OUT operation
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
AD1986
TABLE OF CONTENTS
Functional Block Diagram .............................................................. 4
Specifications..................................................................................... 5
AC ’97 Timing Parameters.......................................................... 9
Absolute Maximum Ratings.......................................................... 12
Environmental Conditions........................................................ 12
ESD Caution................................................................................ 12
Pin Configuration And Function Description ...........................13
AC ’97 Registers.............................................................................. 15
Register Details ...............................................................................17
Reset (Register 0x00).................................................................. 17
Master Volume (Register 0x02)................................................ 17
Headphone Volume (Register 0x04)........................................ 18
Mono Volume (Register 0x06)..................................................18
PC Beep (Register 0x0A) ........................................................... 19
Phone Volume (Register 0x0C)................................................ 19
Surround DAC PCM Rate (Register 0x2E) ............................ 30
C/LFE DAC PCM Rate (Register 0x30).................................. 30
ADC PCM Rate (Register 0x32) .............................................. 30
C/LFE DAC Volume (Register 0x36)....................................... 31
Surround DAC Volume (Register 0x38) ................................. 31
SPDIF Control (Register 0x3A)................................................ 32
EQ Control Register (Register 0x60)....................................... 33
EQ Data Register (Register 0x62) ............................................ 34
Misc Control Bits 2 (Register 0x70)......................................... 34
Jack Sense (Register 0x72)......................................................... 35
Serial Configuration (Register 0x74)....................................... 37
Misc Control Bits 1 (Register 0x76)......................................... 39
Advanced Jack Sense (Register 0x78)...................................... 40
Misc Control Bits 3 (Register 0x7A)........................................ 41
Vendor ID Registers (Register 0x7C to 0x7E) ........................ 42
Microphone Volume (Register 0x0E) ...................................... 20
Line In Volume (Register 0x10)................................................ 21
CD Volume (Register 0x12)...................................................... 21
AUX Volume (Register 0x16) ...................................................22
Front DAC Volume (Register 0x18)......................................... 22
ADC Select (Register 0x1A)...................................................... 23
ADC Volume (Register 0x1C) .................................................. 24
General-Purpose (Register 0x20)............................................. 25
Audio Int and Paging (Register 0x24) .....................................25
Power-Down Ctrl/Stat (Register 0x26).................................... 26
Ext’d Audio ID (Register 0x28)................................................. 27
Ext’d Audio Stat/Ctrl (Register 0x2A)...................................... 28
Front DAC PCM Rate (Register 0x2C) ................................... 29
REVISION HISTORY
CODEC Class/Revision Register (Register 0x60).................. 42
PCI Subsystem Vendor ID Register (Register 0x62, Page 01)
....................................................................................................... 43
PCI Subsystem Device ID Register (Register 0x64, Page 01)43
Function Select Register (Register 0x66, Page 01)................. 43
Information and I/O Register (Register 0x68, Page 01)........ 44
Sense Register (Register 0x6A, Page 01) ................................. 46
Jack Presence Detection................................................................. 48
Audio Jack Styles (NC/NO) ...................................................... 48
Microphone Selection/Mixing...................................................... 49
Outline Dimensions....................................................................... 50
Ordering Guide .......................................................................... 50
10/04—Initial Version: Revision 0
Rev. 0 | Page 2 of 52
AD1986
NOTES
REDUCED SUPPORT COMPONENTS
The AD1986’s many improvements reduce external support
components for particular applications.
• Multiple Microphone Sourcing: The MIC_1/2, LINE_IN
and C/LFE pins may all be selected as sources for
microphone input (boost amplifier).
• Multiple VREF_OUT Pins: Each microphone-capable pin
group (MIC_1/2, LINE_IN and C/LFE) has separate,
software controllable VREF_OUT pins, reducing the need
for external biasing components.
• Internal Microphone Mixing: Any combination of the
MIC_1/2, LINE_IN and C/LFE pins may be summed to
produce the microphone input. This removes the need for
external mixing components in those applications that
externally mixed microphone sources.
• Advanced Jack Presence Detection: Using two CODEC
pins, eight resistors and isolated switch jacks, the AD1986
can detect jack insertion on eight separate jacks. Previous
CODECs would have required 8 CODEC pins and
16 resistors.
• Internal Microphone/Line In/C/LFE Sharing: On systems
that share the microphone with the C/LFE jack there are
no external components required. The micro-phone
selector can select the LINE_IN pins in those cases where
the microphone and line input devices are swapped.
• Internal Line In/Microphone/Surround Sharing: On
systems that share the line in with the surround jack there
are no external components required.
• Dual Headphone Amplifiers: The AD1986 can drive
headphones out of the HP_OUT or LINE_OUT pins.
Rev. 0 | Page 3 of 52
AD1986
S
S
FUNCTIONAL BLOCK DIAGRAM
MIC_1
MIC_2
PHONE_IN
CD_L
CD_GND
CD_R
AUX_L
AUX_R
LINE_IN_L
LINE_IN_R
PCBEEP_IN
LFE_OUT
MICROPHONE
SELECTOR/
MIXING AND
GAIN BLOCK
SELECT
MZ
CD
DIFF AMP
LINE
IN
A
SPRD
AD1986
RECORD
SELECTOR
M
SPDIF TX
G
G
GA
CODEC CORE
20-BIT
M
Σ-∆ ADC
20-BIT
M
Σ-∆ ADC
24-BIT
Σ-∆ DAC
ADC
SLOT
LOGIC
DAC
SLOT
LOGIC
AC97CKSPDIF_OUT
PLL
RESET
SYNC
BITCLK
SDATA_OUT
SDATA_IN
AC '97 INTERFACE V2.3
CENTER_OUT
MONO_OUT
URR_OUT_L
URR_OUT_R
LINE_OUT_L
LINE_OUT_R
HP_OUT_L
HP_OUT_R
MZ
A
SPRD
M
A
MIX
MZ
A
SOSEL
MZ
A
SOSEL
A
M
HP
M
HP
M
HP
M
HP
LOSELLOSEL
A
A
HPSELHPSEL
A
MMM
Σ
G = GAIN
A = ATTENUATION
M = MUTE
Z = HI-Z
GA
GA
GA
GA
M
M
M
Σ
M
GA
GAMGA
M
GA
GA
M
M
M
M
Σ
M
M
M
A
M
M
M
M
M
GA
GA
GA
GA
GA
24-BIT
Σ-∆ DAC
PC BEEP
GENERATOR
24-BIT
Σ-∆ DAC
24-BIT
Σ-∆ DAC
24-BIT
Σ-∆ DAC
24-BIT
Σ-∆ DAC
VOLTAGE
REFERENCE
EQ
EQ
VREF_FILT
AC '97
CONTROL
REGISTERS
EQ COEF STORAGE
EAPD
Z
G
Z
G
Z
G
JACK SENSE
ANALOG MIXING CONTROL
GPIO
JACK_SENSE_A
JACK_SENSE_B
EAPD
GPO
VREF_OUT
(MIC1/2)
VREF_OUT
(C/LFE)
VREF_OUT
(LINE_IN)
04785-0-003
Figure 1.
Rev. 0 | Page 4 of 52
AD1986
SPECIFICATIONS
Test conditions, unless otherwise noted.
Table 1.
Parameter Typ Unit
Temperature 25 °C
Digital Supply (DVDD) 3.3 ±10% V
Analog Supply (AVDD) 5.0 ±10% V
Sample Rate (FS) 48 kHz
Input Signal 1,008 Hz
Analog Output Pass Band 20 Hz–20 kHz
V
IH
V
IL
V
IH
V
IL
2.0 V
0.8 V
2.4 V
0.6 V
DAC Test Conditi ons
Calibrated
Output −3 dB Relative to Full Scale
10 kΩ Output Load: Line (Surround), Mono, Center, and LFE
ADC Test Conditions
Calibrated
0 dB PGA Gain
Input −3.0 dB Relative to Full Scale
32 Ω Output Load: Headphone
Table 2. Analog Input
Input Voltage Min Typ Max Unit
MIC_1/2, LINE_IN, CD, AUX, PHONE_IN (No Preamp) 1 VRMS
1
C/LFE and SURROUND (When Used as Inputs) 2.83 V p-p
MIC_1/2, LINE_IN, C/LFE With 30 dB Preamp 0.032 VRMS
0.089 V p-p
MIC_1/2, LINE_IN, C/LFE With 20 dB Preamp 0.1 VRMS
0.283 V p-p
MIC_1/2, LINE_IN, C/LFE With 10 dB Preamp 0.316 VRMS
0.894 V p-p
Input Impedance
2
20 kΩ
Input Capacitance2 5 7.5 pF
1
RMS values assume sine wave input.
2
Guaranteed by design, not production tested.
Table 3. Master Volume
Parameter Min Typ Max Unit
Step Size (LINE_OUT, HP Out, Mono Out, SURROUND, CENTER, LFE) −1.5 dB
Output Attenuation Range (0 dB to –46.5 dB) −6.5 dB
Mute Attenuation of 0 dB Fundamental2 −80 dB
Table 4. Programmable Gain Amplifier—ADC
Parameter Min Typ Max Unit
Step Size 1.5 dB
PGA Gain Range Span (0 dB to 22.5 dB) 22.5 dB
Rev. 0 | Page 5 of 52
AD1986
Table 5. Analog Mixer—Input Gain/Amplifiers/Attenuators
Parameter Min Typ Max Unit
Signal-to-Noise Ratio (SNR)
CD to LINE_OUT 90 dB
LINE, AUX, PHONE to LINE_OUT
MIC_1 or MIC_2 to LINE_OUT1 80 dB
Step Size: All Mixer Inputs (Except PC Beep) −1.5 dB
Step Size: PC Beep −3.0 dB
Input Gain/Attenuation Range: All Mixer Inputs (+12 dB to −34.5 dB) −46.5 dB
1
Guaranteed by design, not production tested.
Table 6. Digital Decimation and Interpolation Filters
Parameter Min Typ Max Unit
Pass Band 0 0.4 × FSHz
Pass Band Ripple ±0.09 dB
Transition Band 0.4 × FS 0.6 × FSHz
Stop Band 0.6 × FS ∞ Hz
Stop Band Rejection −74 dB
Group Delay 16/F
Group Delay Variation Over Pass Band 0 µs
1
1
88 dB
S
S
Table 7. Analog-to-Digital Converters
Parameter Min Typ Max Unit
Resolution 20 Bits
Total Harmonic Distortion (THD) −95 dB
Dynamic Range (−60 dB Input, THD + N referenced to Full Scale, A-Weighted) −85 dB
Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L) −80 dB
LINE_IN to Other Inputs −100 −80 dB
Gain Error (Full-Scale Span Relative to Nominal Input Voltage) ±10 %
Interchannel Gain Mismatch (Difference of Gain Errors) ±0.5 dB
ADC Offset Error ±5 mV
Rev. 0 | Page 6 of 52
AD1986
Table 8. Digital-to-Analog Converters
Parameter Min Typ Max Unit
Resolution 24 Bits
Total Harmonic Distortion (LINE_OUT Drive) −92 dB
Total Harmonic Distortion HP_OUT −75 dB
Dynamic Range (−60 dB Input, THD + N referenced to Full Scale, A-Weighted) 91 dB
Gain Error (Full-Scale Span Relative to Nominal Input Voltage) ±10 %
Interchannel Gain Mismatch (Difference of Gain Errors) ±0.7 dB
DAC Crosstalk1 (Input L, Zero R, Read R_OUT; Input R, Zero L, Read L_OUT) −80 dB
1
Guaranteed by design, not production tested.
Table 9. Analog Output
Parameter Min Typ Max Unit
FULL-SCALE OUTPUT VOLTAGE: SURROUND, CENTER/LFE, MONO_OUT 1 VRMS
2.83 V p-p
Output Impedance1 300 Ω
External Load Impedance1 10 kΩ
Output Capacitance1 15 pF
External Load Capacitance 1,000 pF
FULL-SCALE OUTPUT VOLTAGE: HP_OUT, LINE_OUT 1 VRMS
2.83 V p-p
Output Impedance1 1 Ω
External Load Impedance1 32 Ω
Output Capacitance1 15 pF
External Load Capacitance1 1,000 pF
VREF_FILT, A
A
= 3.3 V 1.125 V
VDD
VREF_OUT(MIC, C/LFE, LIN) (xVREF [2:0] = 001) 2.250 V
(xVREF [2:0] = 100, A
(xVREF [2:0] = 100, A
(xVREF [2:0] = 010) 0.0 V
Current Drive 5 mA
Mute Click (Muted Output, Unmuted Midscale DAC Output) ±5 mV
= 5.0 V 2.050 2.250 2.450 V
VDD
= 5.0 V) 3.700 V
VDD
= 3.3 V) 2.250 V
VDD
Table 10. Static Digital Specifications—AC ’97
Parameter Min Typ Max Unit
High Level Input Voltage (VIH), Digital Inputs 0.65 × DV
Low Level Input Voltage (VIL) 0.35 × DV
High Level Output Voltage (VOH), IOH = 2 mA 0.90 × DV
Low Level Output Voltage (VOL), IOL = 2 mA 0.10 × DV
V
DD
DD
V
DD
DD
V
V
Input Leakage Current −10 10 µA
Output Leakage Current −10 10 µA
Input/Output Pin Capacitance 7.5 pF
Rev. 0 | Page 7 of 52
AD1986
Table 11. Power Supply (Quiescent State)
Parameter Min Typ Max Unit
Power Supply Range—Analog (AVDD) ±10% 4.5 5.5 V
Power Supply Range—Digital (DVDD) ±10% 2.97 3.63 V
Power Dissipation—Analog (AVDD)/Digital (DVDD) 365/171.6 mW
Analog Supply Current—Analog (AVDD) 73 mA
Digital Supply Current—Digital (DVDD) 52 mA
Power Supply Rejection (100 mV p–p Signal @ 1 kHz) 40 dB
Table 12. Power-Down States—AC ’97 (Quiescent State)
Parameter Set Bits DVDDTyp AVDD Typ Unit
ADC PR0 53.0 45.7 mA
FRONT DAC PR1 53.7 47.7 mA
CENTER DAC PRI 62.0 53.2 mA
SURROUND DAC PRJ 53.5 47.1 mA
LFE DAC PRK 62.0 52.8 mA
ADC + ALL DACs PR1, PR0, PRI, PRJ, PRK 27.0 14.5 mA
Mixer PR2 36.6 53.2 mA
ADC + Mixer PR2, PR0 27.6 45.7 mA
ALL DACs + Mixer PR2, PR1, PRI, PRJ, PRK 12.6 33.0 mA
ADC + ALL DACs + Mixer PR2, PR1, PR0, PRI, PRJ, PRK 2.4 14.5 mA
Standby PR5, PR4, PR3, PR2, PR1(IJK), PR0 0.0 0.05 mA
Headphone Standby PR6 55.0 53.2 mA
LINE_OUT HP Standby LOHPEN = 0 62.0 53.2 mA
Table 13. Clock Specifications—AC ’97
Parameter Min Typ Max Unit
Input Clock Frequency (Reference Clock Mode)
Recommended Clock Duty Cycle 40 50 60 %
1
Refer to AC ’97, Revision 2.3 specifications for details of clock detection at startup. AD1986 CODEC clock source detection must follow AC ’97, Revision 2.3 guidelines.
1
14.31818
MHz
48.000
Rev. 0 | Page 8 of 52
AD1986
AC ’97 TIMING PARAMETERS
Guaranteed over operating temperature range. Refer to the AC ’97 specifications (Revision 2.3, Release 1.0) for further information. The
specification can be downloaded from http://developer.intel.com/ial.scalableplatforms/audio.
t
RST2CLK
t
RST_LOW
RESET
BIT_CLK
04785-0-005
Figure 2. Cold Reset Timing (CODEC is Supplying the BIT_CLK Signal)
Table 14.
Symbol Parameter Min Typ Max Unit
t
RST_LOW
t
RST2CLK
Recommended During Active (Low) RESET Signal 1.0 µS
RESET Inactive (High) to BIT_CLK Active 162.8 400,000 nS
SYNC
BIT_CLK
t
SYNC_HIGH
Figure 3. Warm Reset Timing
t
SYNC2CLK
04785-0-006
Table 15.
Symbol Parameter Min Typ Max Unit
t
SYNC_HIGH
t
SYNC2CLK
Sync Active (High) Pulse Width 1.3 µS
Sync Inactive to BITCLK Startup Delay 162.8 nS
RESET
SDATA_OUT
SYNC
BIT_CLK, EAPD,
SPDIF_OUT,
SDATA_IN,
DIGITAL I/O
t
SETUP2RST
re 4. ATE Test Mode
Figu
Hi-Z
t
OFF
04785-0-007
Table 16.
Symbol Parameter Min Typ Max Unit
t
SETUP2RST
t
OFF
Setup to RESET Inactive (SYNC, SDATA_OUT) 15 nS
Rising Edge of RESET to Hi-Z Delay 25 nS
Rev. 0 | Page 9 of 52
AD1986
t
CLK_LOW
BIT_CLK
t
CLK_HIGH
t
CLK_PERIOD
t
SYNC_LOW
SYNC
t
SYNC_HIGH
t
SYNC_PERIOD
Figure 5. Bit Clock and Sync Timing
Table 17.
Symbol
t
SYNC_HIGH
t
CLK_LOW
t
CLK_PERIOD
Parameter Min Typ Max Units
BITCLK High Pulse Width 40.5 41.7 nS
BITCLK Low Pulse Width 39.7 40.6 nS
BITCLK Period 81.4 nS
BIT_CLK Frequency 12.288 MHz
BIT_CLK Frequency Accuracy ±1.0 ppm
BIT_CLK Jitter
t
SYNC_HIGH
t
SYNC_LOW
t
SYNC_PERIOD
Sync Active (High) Pulse Width 1.3 µS
Sync Inactive (Low) Pulse Width 19.5 µS
Sync Period 20.8 µS
1, 2
750 ps
Sync Frequency 48.0 kHz
04785-0-008
1
Guaranteed
2
Output jitte
Table
Symbol Typ Max Units
t
S2_PDOWN
by design, but not production tested.
r directly dependent on input clock jitter.
18.
Parameter Min
End ATA_IN Low of Slot 2 to BIT_CLK, SD 0 1.0 µS
SLOT 1 SLOT 2
SYNC
BIT_CLK
SDATA_OUT
SDATA_IN
WRITE TO
03 26
BIT_CLK NOT TO SCALE
Figure 6. Link Low Power Mode Timing
DATA
PR4
t
S2_PDOWN
04785-0-009
Rev. 0 | Page 10 of 52
AD1986
S
T
BIT_CLK
SYNC
SDATA_IN
t
RISECLK
t
RISESYNC
t
FALLCLK
t
FALLSYNC
t
RISEDIN
DATA_OU
t
RISEDOUT
Figure 7. Signal Rise and Fall Tim
t
t
es
FALLDIN
FALLDOUT
04785-0-010
ble 19.
Ta
mbol Min Typ it
Sy Parameter Max Un
t
RISECLK
t
FALLCLK
t
RISESYNC
t
RISESYNC
t
RISEDIN
t
RISEDIN
t
RISEDOUT
t
RISEDOUT
2 4 BIT_CLK Fall Time 6 nS
SYNC Rise Time 2 4 6 nS
SYNC Fall Time 2 4 6 nS
SDATA_IN Rise Time 2 4 6 nS
SDATA_IN Fall Time 2 4 6 nS
SDATA_OUT Rise Time 2 4 6 nS
SDATA_OUT Fall Time 2 4 6 nS
4 6 BIT_CLK Rise Time 2 nS
t
CO
t
SETUP
BIT_CLK
SDATA_OUT
SDATA_IN
SYNC
IH
V
OH
V
OL
t
HOLD
V
IL
04785-0-011
V
Figure 8. Link Low Power Mode Timing (Detail)
Table 20.
Symbol Parameter Min Typ Max Unit
t
CO
t
SETUP
t
HOLD
V
V
V
V
IH
IL
OH
OL
Propagation Delay 25 nS
Setup to Falling Edge of BIT_CLK 4 nS
Hold from Falling Edge of BIT_CLK 3 nS
Digital Signal High Level Input Voltage 0.65 DV
DD
Digital Signal Low Level Input Voltage 0.35 DV
Digital Signal High Level Output Voltage 0.9 DV
DD
Digital Signal Low Level Output Voltage 0.1 DV
V
V
DD
V
DD
V
Rev. 0 | Page 11 of 52
AD1986
ABSOLUTE MAXIMUM RATINGS
Table 21.
Power Supply Min Max Unit
Digital (DVDD) −0.3 +3.6 V
Analog (AVDD) −0.3 +6.0 V
Input Current (Except Supply Pins) ±10.0 mA
Analog Input Voltage (Signal Pins) −0.3 AVDD + 0.3 V
Digital Input Voltage (Signal Pins) −0.3 DVDD + 0.3 V
Ambient Temperature (Operating)
Commercial
Industrial
0
–40
+70
+85
Storage Temperature −65 +150 °C
Stresses greater than those listed under Absolute Maximum
Ratings may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
°C
ENVIRONMENTAL CONDITIONS
Ambient Temperature Rating
T
= T
AMB
T
CASE
PD = power dissipation in W
= thermal resistance (case-to-ambient)
θ
CA
= thermal resistance (junction-to-ambient)
θ
JA
= thermal resistance (junction-to-case)
θ
JC
Table 22. Thermal Resistance
Package θ
LQFP 76.2°C/W 17°C/W 59.2°C/W
− (PD × θCA)
CASE
= case temperature in °C
JA
θ
JC
θ
CA
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 12 of 52
AD1986
PIN CONFIGURATION AND FUNCTION DESCRIPTION
S/PDIF_OUT
EAPD
AVDDLINE_OUT_R
AVSSLINE_OUT_L
AVDDHEADPHONE_R
AVSSHEADPHONE_L
AVDDMONO_OUT
SURR_OUT_R
36
SURR_OUT_L
35
AV
34
DD
VREF_OUT (C/LFE)
33
LFE_OUT
32
CENTER_OUT
31
AV
30
SS
VREF_OUT (LINE_IN)
29
VREF_OUT (MIC_1/2)
28
VREF_FILT
27
AV
26
SS
AV
25
DD
CD_R
MIC_1
MIC_2
LINE_IN_L
LINE_IN_R
04785-0-001
DV
DD
AC97CK
GPO
DV
SS
SDATA_OUT
BIT_CLK
DV
SS
SDATA_IN
DV
DD
SYNC
RESET
PCBEEP
48 47 46 45 44 39 38 3743 42 41 40
1
PIN 1
2
IDENTIFIER
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
PHONE_IN
AUX_L
AUX_R
AD1986
TOP VIEW
(Not to Scale)
CD_L
CD_GND
JACK_SENSE_A
JACK_SENSE_B
Figure 9. Pin Configuration
Table 23. Pin Function Descriptions
Mnemonic Pin Number Input/Ouput Description
AC ’97CK 2 I External Clock In (14.31818 MHz).
SDATA_OUT 5 I AC Link Serial Data Output. Input Stream.
BIT_CLK 6 O AC Link Bit Clock. 12.288 MHz Serial Data Clock.
SDATA_IN 8 I/O AC Link Serial Data Input. Output Stream.
SYNC 10 I AC Link Frame Sync .
RESET
11 I AC Link Reset. Master Hardware Reset.
Table 24. Digital Input/Output
Mnemonic
Pin
Number
Input/
Output Description
S/PDIF_OUT 48 O S/PDIF Output.
EAPD 47 O External Amplifier Power-Down Output.
GPO 3 O General-Purpose Output pin. A digital signal that can be used to control external circuitry.
Table 25. Jack Sense
Mnemonic Pin Number Input/Ouput Description
JACK_SENSE_A 16 I JackSense 0–3 Input
JACK_SENSE_B 17 I Jack Sense 4–7 Input
Rev. 0 | Page 13 of 52
AD1986
Table 26. Analog Input/Output
Pin
Mnemonic
Number
PCBEEP 12 I Analog PC Beep Input. Routed to all output capable pins when RESET is asserted.
PHONE_IN 13 I Monaural Line Level Input.
AUX_L 14 I Auxiliary Left Channel Input.
AUX_R 15 I Auxiliary Right Channel Input.
CD_L 18 I CD-Audio-Left Channel.
CD_GND 19 I CD-Audio-Analog-Ground-Reference (for Differential CD Input).
CD_R 20 I CD-Audio-Right Channel.
MIC_1 21 I Microphone 1 or Line-In-Left Input (See LISEL Bits in Register 0x76).
MIC_2 22 I Microphone 2 or Line-In-Right Input (See LISEL Bits in Register 0x76).
LINE_IN_L 23 I Line-In-Left Channel or Microphone 1 Input (See OMS Bits in Register 0x74).
LINE_IN_R 24 I Line-In-Right Channel or Microphone 2 Input (See OMS Bits in Register 0x74).
CENTER_OUT 31 I/O Center-Channel Output or Microphone 1 Input (See OMS Bits in Register 0x74).
LFE_OUT 32 I/O Low-Frequency-Enhanced Output or Microphone 2 Input (See OMS Bits in Register 0x74).
HEADPHONE_L 39 O Headphone-Out-Left Channel (See HPSEL Bits in Register 0x76).
HEADPHONE_R 41 O Headphone-Out-Right Channel (See HPSEL Bits in Register 0x76).
LINE_OUT_L 43 O Line-Out (Front)—Left Channel (See LOSEL Bit in Register 0x76) (HP Drive-Capable).
LINE_OUT_R 45 O Line-Out (Front)—Right Channel (See LOSEL Bit in Register 0x76) (HP Drive-Capable).
MONO_OUT 37 O Monaural Output to Telephony Subsystem Speakerphone.
SURR_OUT_L 35 I/O Surround-Left Channel Output or Line-In-Left Input (See LISEL and SOSEL Bits in Register 0x76).
SURR_OUT_R 36 I/O
Input/
Ouput
Description
Surround-Right Channel Output or Line-In-Right Input (See LISEL and SOSEL Bits in
Register 0x76).
Table 27. Filter/Reference
Mnemonic
Pin
Number
Input/
Ouput
Description
VREF_FILT 27 O Voltage Reference Filter.
VREF_OUT (MIC) 28 O Programmable Voltage Reference Output (Intended for MIC Bias on the MIC_1/2 Channels).
VREF_OUT
29 O Programmable Voltage Reference Output (Intended for MIC Bias on the LINE_IN Channels).
(LINE_IN)
VREF_OUT (C/LFE) 33 O Programmable Voltage Reference Output (Intended for MIC Bias on the C/LFE Channels).
Table 28. Power and Ground
Input/
Mnemonic Pin Number
DV
DD
1 Digital Supply Voltage (3.3 V).
Ouput
Description
9
DV
SS
4 Digital Supply Return (Ground).
7
AV
DD
25 Analog Supply Voltage (5.0 V or 3.3 V). AV
supplies should be well filtered because supply
DD
34 noise will degrade audio performance.
38 I
42
46
AV
SS
26 Analog Supply Return (Ground).
30
40
44
Rev. 0 | Page 14 of 52
AD1986
AC ’97 REGISTERS
Table 29. Register Map
Reg Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
0x00 Reset x SE4 SE3 SE2 SE1 SE0 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 0x0290
0x02 Master Volume LM x x LV4 LV3 LV2 LV1 LV0 RM x x RV4 RV3 RV2 RV1 RV0 0x8080
0x04 Headphones Volume LM x x LV4 LV3 LV2 LV1 LV0 RM x x RV4 RV3 RV2 RV1 RV0 0x8080
0x06 Mono Volume M x x x x x x x x x x V4 V2 V2 V1 V0 0x8000
0x0A PC Beep M A/DS x F7 F6 F5 F4 F3 F2 F1 F0 V3 V2 V1 V0 x 0x8000
0x0C Phone Volume M x x x x x x x x x x V4 V3 V2 V1 V0 0x8008
0x0E Microphone Volume LM x x LV4 LV3 LV2 LV1 LV0 RM M20 x RV4 RV3 RV2 RV1 RV0 0x8888
0x10 Line In Volume LM x x LV4 LV3 LV2 LV1 LV0 RM x x RV4 RV3 RV2 RV1 RV0 0x8888
0x12 CD Volume LM x x LV4 LV3 LV2 LV1 LV0 RM x x RV4 RV3 RV2 RV1 RV0 0x8888
0x16 AUX Volume LM x x LV4 LV3 LV2 LV1 LV0 RM x x RV4 RV3 RV2 RV1 RV0 0x8888
0x18 Front DAC Volume LM x x LV4 LV3 LV2 LV1 LV0 RM x x RV4 RV3 RV2 RV1 RV0 0x8888
0x1A ADC Select x x x x x LS2 LS1 LS0 x x x x x RS2 RS1 RS0 0x0000
0x1C ADC Volume LM x x x LV3 LV2 LV1 LV0 RM x x x RV3 RV2 RV1 RV0 0x8080
0x20 General Purpose x x x x DRSS1 DRSS0 MIX MS LPBK x x x x x x x 0x0000
0x24 Audio Int. and Paging I4 I3 I2 I1 I0 x x x x x x x PG3 PG2 PG1 PG0 0xxx00
0x26 Power-Down Ctrl/Stat EAPD PR6 PR5 PR4 PR3 PR2 PR1 PR0 x x x x REF ANL DAC ADC 0x000x
0x28 Ext’d Audio ID ID11ID0 x x REV1 REV0 AMAP LDAC SDAC CDAC DSA1 DSA0 x SPDF DRA VRA 0x0BC7
0x2A Ext’d Audio Stat/Ctrl x x PRK PRJ PRI SPCV x LDAC SDAC CDAC SPSA1 SPSA0 x SPDIF DRA VRA 0x0xx0
0x2C Front DAC PCM Rate R15 R14 R13 R12 R11 R10 R09 R08 R07 R06 R05 R04 R03 R02 R01 R00 0xBB80
0x2E Surr. DAC PCM Rate R15 R14 R13 R12 R11 R10 R09 R08 R07 R06 R05 R04 R03 R02 R01 R00 0xBB80
0x30 C/LFE DAC PCM Rate R15 R14 R13 R12 R11 R10 R09 R08 R07 R06 R05 R04 R03 R02 R01 R00 0xBB80
0x32 ADC PCM Rate R15 R14 R13 R12 R11 R10 R09 R08 R07 R06 R05 R04 R03 R02 R01 R00 0xBB80
0x36 C/LFE DAC Volume LFEM x x LFE4 LFE3 LFE2 LFE1 LFE0 CNTM x x CNT4 CNT3 CNT2 CNT1 CNT0 0x8888
0x38 Surround DAC Volume LM x x LV4 LV3 LV2 LV1 LV0 RM x x RV4 RV3 RV2 RV1 RV0 0x8888
0x3A SPDIF Control V VCFG SPSR x L CC6 CC5 CC4 CC3 CC2 CC1 CC0 PRE COPY /AUDIO PRO 0x2000
0x60 EQ Control EQM x x x x x x x SYM CHS BCA5 BCA4 BCA3 BCA2 BCA1 BCA0 0x8080
0x62 EQ Data CFD15 CFD14 CFD13 CFD12 CFD11 CFD10 CFD9 CFD8 CFD7 CFD6 CFD5 CFD4 CFD3 CFD2 CFD1 CFD0 0xxxxx
0x70 Misc. Control Bits 2 x x x MVREF2 MVREF1 MVREF0 x x MMDIS x JSMAP CVREF2 CVREF1 CVREF0 x x 0x0000
0x72 Jack Sense JS1 SPRD JS1 DMX JS0 DMX JS MT2 JS MT1 JS MT0 JS1 EQB JS0 EQB x x JS1 MD JS0 MD JS1 ST JS0 ST JS1 INT JS0 INT 0x0000
0x74 Serial Configuration SLOT16 REGM2 REGM1 REGM0 REGM3 OMS2 OMS1 OMS0 SPOVR LBKS1 LBKS0 INTS CSWP SPAL SPDZ SPLNK 0x1001
0x76 Misc. Control Bits 1 DACZ AC97NC2MSPLT SODIS3CLDIS x DMIX1 DMIX0 SPRD 2CMIC SOSEL SRU LISEL1 LISEL0 MBG1 MBG0 0x6010
0x78 Advanced Jack Sense JS7ST JS7INT JS6ST JS6INT JS5ST JS5INT JS4ST JS4INT JS4-7H x JS3MD JS2MD JS3ST JS2ST JS3INT JS2INT 0xxxxx
0x7A Misc. Control Bits 3 JSINVB HPSEL1 HPSEL0 LOSEL JSINVA LVREF2 LVREF1 LVREF0 x x x LOHPEN GPO MMIX x x 0x0000
0x7C Vendor ID1 F7 F6 F5 F4 F3 F2 F1 F0 S7 S6 S5 S4 S3 S2 S1 S0 0x4144
0x7E Vendor ID2 T7 T6 T5 T4 T3 T2 T1 T0 REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0 0x5378
0x601 CODEC Class/Rev x x x CL4 CL3 CL2 CL1 CL0 RV7 RV6 RV5 RV4 RV3 RV2 RV1 RV0 0x0002
0x621 PCI SVID PVI15 PVI14 PVI13 PVI12 PVI11 PVI10 PVI9 PVI8 PVI7 PVI6 PVI5 PVI4 PVI3 PVI2 PVI1 PVI0 0xFFFF
0x641 PCI SID PI15 PI14 PI13 PI12 PI11 PI10 PI9 PI8 PI7 PI6 PI5 PI4 PI3 PI2 PI1 PI0 0xFFFF
Rev. 0 | Page 15 of 52
AD1986
Reg Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
0x661 Function Select x x x x x x x x x x x FC3 FC2 FC1 FC0 T/R 0x0000
0x681 Function Information G4 G3 G2 G1 G0 INV DL4 DL3 DL2 DL1 DL0 IV x x x FIP 0xXxxx
0x6A1 Sense Register ST2 ST1 ST0 S4 S3 S2 S1 S0 OR1 OR0 SR5 SR4 SR3 SR2 SR1 SR0 0xXxxx
1
CODEC is always master, ID bits are read-only 0 (zeros).
2
Bits for the AD198x are backwards-compatible only, AC97NC and MSPLT are read-only 1 (ones).
3
SODIS/SOSEL were LODIS/LOSEL in the AD1985. Most AD1985 configurations swapped LINE_OUT and SURROUND pins; these bits really operated as SO not LO.
Rev. 0 | Page 16 of 52
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