ANALOG DEVICES AD1974 Service Manual

4 ADC with PLL,

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FEATURES

Phase-locked loop generated or direct master clock Low EMI design 107 dB dynamic range and SNR

−94 dB THD + N Single 3.3 V supply Tolerance for 5 V logic inputs Supports 24 bits and 8 kHz to 192 kHz sample rates Differential ADC input Log volume control with autoramp function SPI®-controllable for flexibility Software-controllable clickless mute Software power-down Right justified, left justified, I Master and slave modes up to 16-channel input/output Available in a 48-lead LQFP

APPLICATIONS

Automotive audio systems Home Theater Systems Set-top boxes Digital audio effects processors

2

S, and TDM modes

192 kHz, 24-Bit Codec

AD1974

GENERAL DESCRIPTION

The AD1974 is a high performance, single-chip codec that provides four analog-to-digital converters (ADCs) with differential inputs using the Analog Devices, Inc. patented multibit sigmadelta (Σ-Δ) architecture. An SPI port is included, allowing a microcontroller to adjust volume and many other parameters. The AD1974 operates from 3.3 V digital and analog supplies. The AD1974 is available in a single-ended output 48-lead LQFP.

The AD1974 is designed for low EMI. This consideration is

pparent in both the system and circuit design architectures.

a By using the on-board phase-locked loop (PLL) to derive the master clock from the LR clock or from an external crystal, the AD1974 eliminates the need for a separate high frequency master clock and can also be used with a suppressed bit clock. The ADCs are designed using the latest continuous time architectures from Analog Devices to further minimize EMI. By using 3.3 V supplies, power consumption is minimized, further reducing emissions.

FUNCTIONAL BLOCK DIAGRAM

AD1974

ADC

ANALOG

AUDIO

INPUTS

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

ADC

PRECISION

VOLTAGE

REFERENCE

96kHz/192kHz

QUAD

DEC

FILTER

48kHz/

Figure 1.

DIGITAL AUDIO INPUT/OUTPUT

SERIAL DATA PORT

SDATA

OUT

CLOCKS

TIMING MANAGEMENT

AND CONTROL

(CLOCK AND PLL )

CONTROL PO RT

SPI

12.48MHz

CONTROL DAT A

INPUT/OUTPUT

06614-001

AD1974

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REVISION HISTORY

4/07—Revision 0: Initial Version

Rev. 0 | Page 2 of 24

AD1974

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SPECIFICATIONS

TEST CONDITIONS

Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications.

Supply Voltages (AVDD, DVDD) 3.3 V

Temp e r a t ure Ra n ge

1

As specified in Ta b le 1 and Tabl e 2

Master Clock 12.288 MHz (48 kHz f

Input Sample Rate 48 kHz

Measurement Bandwidth 20 Hz to 20 kHz

Word Width 24 bits

Load Capacitance (Digital Output) 20 pF

Load Current (Digital Output) ±1 mA or 1.5 kΩ to ½ DVDD supply

Input Voltage High 2.0 V

Input Voltage Low 0.8 V

1

Functionally guaranteed at −40°C to +125°C case temperature.

, 256 × fS mode)

S

ANALOG PERFORMANCE SPECIFICATIONS

Specifications guaranteed at 25°C (ambient).

Table 1.

Parameter Conditions Min Typ Max Unit

ANALOG-TO-DIGITAL CONVERTERS

ADC Resolution All ADCs 24 Bits Full-Scale Input Voltage (Differential) 1.9 V rms Dynamic Range 20 Hz to 20 kHz, −60 dB input

No Filter (RMS) 98 102 dB

With A-Weighted Filter (RMS) 100 105 dB Total Harmonic Distortion + Noise (THD + N) −1 dBFS −96 −87 dB Gain Error −10 +10 % Interchannel Gain Mismatch −0.25 +0.25 dB Offset Error −10 0 +10 mV Gain Drift 100 ppm/°C Interchannel Isolation −110 dB CMRR 100 mV rms, 1 kHz 55 dB 100 mV rms, 20 kHz 55 dB Input Resistance 14 kΩ Input Capacitance 10 pF Input Common-Mode Bias Voltage 1.5 V

REFERENCE

Internal Reference Voltage FILTR pin 1.50 V External Reference Voltage FILTR pin 1.32 1.50 1.68 V Common-Mode Reference Output CM pin 1.50 V

Rev. 0 | Page 3 of 24

AD1974

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Specifications measured at 130°C (case).

Table 2.

Parameter Conditions Min Typ Max Unit

ANALOG-TO-DIGITAL CONVERTERS

ADC Resolution All ADCs 24 Bits Full-Scale Input Voltage (Differential) 1.9 V rms Dynamic Range 20 Hz to 20 kHz, −60 dB input

No Filter (RMS) 95 102 dB

With A-Weighted Filter (RMS) 97 105 dB Total Harmonic Distortion + Noise (THD + N) −1 dBFS −96 −87 dB Gain Error −10 +10 % Interchannel Gain Mismatch −0.25 +0.25 dB Offset Error −10 0 +10 mV

REFERENCE

Internal Reference Voltage FILTR pin 1.50 V External Reference Voltage FILTR pin 1.32 1.50 1.68 V Common-Mode Reference Output CM pin 1.50 V

CRYSTAL OSCILLATOR SPECIFICATIONS

Table 3.

Parameter Min Typ Max Unit

Transconductance 3.5 Mmhos

DIGITAL INPUT/OUTPUT SPECIFICATIONS

−40°C < TA < +130°C, DVDD = 3.3 V ± 10%.

Table 4.

Parameter Conditions/Comments Min Typ Max Unit

Input Voltage High (VIH) 2.0 V Input Voltage High (VIH) MCLKI pin 2.2 V Input Voltage Low (VIL) 0.8 V Input Leakage IIH @ VIH = 2.4 V 10 μA I High Level Output Voltage (VOH) IOH = 1 mA DVDD − 0.60 V Low Level Output Voltage (VOL) IOL = 1 mA 0.4 V Input Capacitance 5 pF

@ VIL = 0.8 V 10 μA

IL

Rev. 0 | Page 4 of 24

AD1974

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POWER SUPPLY SPECIFICATIONS

Table 5.

Parameter Conditions/Comments Min Typ Max Unit

SUPPLIES

Voltage DVDD 3.0 3.3 3.6 V AVDD 3.0 3.3 3.6 V Digital Current MCLK = 256 f

S

Normal Operation fS = 48 kHz 56 mA f f

= 96 kHz 65 mA

S

= 192 kHz 95 mA

S

Power-Down fS = 48 kHz to 192 kHz 2.0 mA

Analog Current

Normal Operation 74 mA Power-Down 23 mA

DISSIPATION

Operation MCLK = 256 fS, 48 kHz

All Supplies 429 mW Digital Supply 185 mW Analog Supply 244 mW

Power-Down, All Supplies 83 mW

POWER SUPPLY REJECTION RATIO

Signal at Analog Supply Pins 1 kHz, 200 mV p-p 50 dB 20 kHz, 200 mV p-p 50 dB

DIGITAL FILTERS

Table 6.

Parameter Mode Factor Min Typ Max Unit

ADC DECIMATION FILTER

Pass Band 0.4375 f

All modes @ 48 kHz

S

21 kHz Pass-Band Ripple ±0.015 dB Transition Band 0.5 f

S

Stop Band 0.5625 f

S

24 kHz

27 kHz Stop-Band Attenuation 79 dB Group Delay 22.9844 f

S

479 μs

TIMING SPECIFICATIONS

−40°C < TA < +130°C, DVDD = 3.3 V ± 10%.

Table 7.

Parameter Condition Comments Min Max Unit

INPUT MASTER CLOCK (MCLK) AND RESET

t

MH

t

MH

f

MCLK

f

MCLK

t

PDR

t

PDRR

MCLK duty cycle ADC clock source = PLL clock @ 256 fS, 384 fS, 512 fS, 768 fS 40 60 %

ADC clock source = direct MCLK @ 512 f

(bypass

S

40 60 %

on-chip PLL) MCLK frequency PLL mode, 256 fS reference 6.9 13.8 MHz Direct 512 fS mode 27.6 MHz Low 15 ns Recovery Reset to active output 4096 t

MCLK

Rev. 0 | Page 5 of 24

AD1974

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Parameter Condition Comments Min Max Unit

PLL

Lock Time MCLK and LRCLK input 10 ms 256 fS VCO Clock 40 60 %

Output Duty Cycle MCLK_O Pin

SPI PORT See Figure 5

t

CCH

t

CCL

f

CCLK

t

CDS

t

CDH

t

CLS

t

CLH

t

CLHIGH

t

COE

t

COD

t

COH

t

COTS

ADC SERIAL PORT See Figure 13

t

ABH

t

ABL

t

ALS

t

ALH

t

ALS

t

ABDD

AUXILIARY INTERFACE See Figure 12

t

XDS

t

XDH

t

XBH

t

XBL

t

XLS

t

XLH

CCLK high 35 ns CCLK low 35 ns CCLK frequency f

CCLK

= 1/t

CCP

; only t

shown in Figure 5

CCP

10 MHz

CDATA setup To CCLK rising 10 ns CDATA hold From CCLK rising 10 ns Setup To CCLK rising 10 ns Hold From CCLK falling 10 ns High Not shown in Figure 5 10 ns COUT enable From CCLK falling 30 ns COUT delay From CCLK falling 30 ns COUT hold From CCLK falling, not shown in Figure 5 30 ns COUT tristate From CCLK falling 30 ns

ABCLK high Slave mode 10 ns ABCLK low Slave mode 10 ns ALRCLK setup To ABCLK rising, slave mode 10 ns ALRCLK hold From ABCLK rising, slave mode 5 ns ALRCLK skew From ABCLK falling, master mode −8 +8 ns ASDATA delay From ABCLK falling 18 ns

AAUXDATA se t u p To AUXBCLK ris ing 1 0 ns AAUXDATA hold From AUXBCLK rising 5 ns AUXBCLK high 10 ns AUXBCLK low 10 ns AUXLRCLK setup To AUXBCLK rising 10 ns AUXLRCLK hold From AUXBCLK rising 5 ns

Rev. 0 | Page 6 of 24

AD1974

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ABSOLUTE MAXIMUM RATINGS

Table 8.

Parameter Rating

Analog (AVDD) −0.3 V to +3.6 V Digital (DVDD) −0.3 V to +3.6 V Input Current (Except Supply Pins) ±20 mA Analog Input Voltage (Signal Pins) –0.3 V to AVDD + 0.3 V Digital Input Voltage (Signal Pins) −0.3 V to DVDD + 0.3 V Operating Temperature Range (Case) −40°C to +125°C Storage Temperature Range −65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

θJA represents thermal resistance, junction-to-ambient; θ represents the thermal resistance, junction-to-case. All characteristics are for a 4-layer board.

Table 9.

Package Type θ

48-Lead LQFP 50.1 17 °C/W

JA

θ

JC

Unit

ESD CAUTION

Rev. 0 | Page 7 of 24

AD1974

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

AGND

AVDD

NC NC NC NC

PD/RST

NC

DGND

2

3

4

5

6

7

8

9

10

11

12

MCLKI/XI

MCLKO/XO

NC = NO CONNECT

AVDD48LF47ADC2RN46ADC2RP45ADC2LN44ADC2LP43ADC1RN42ADC1RP41ADC1LN40ADC1LP39CM38AVDD

AD1974

TOP VIEW

(Not to S cale)

SINGLE-ENDED

OUTPUT

13

15NC16

17

18

20

21

DVDD

AUXDATA214AUXDATA1

AUXBCLK

AUXLRCLK

ASDATA219ASDATA1

ABCLK

37

36

AGND

35

FILTR

34

AGND

33

AVDD

32

AGND

31

NC

30

NC

29

NC

28

NC

27

CLATCH

26

CCLK

25

DGND

22

23

24

CIN

COUT

ALRCLK

06614-020

Figure 2. AD1974 Single-Ended Output, 48-Lead LQFP Pin Configuration

Table 10. Pin Function Description

Pin No. Type1 Mnemonic Description

1, 4, 32, 34, 36 I AGND Analog Ground. 2 I MCLKI/XI Master Clock Input/Crystal Oscillator Input. 3 O MCLKO/XO Master Clock Output/Crystal Oscillator Output. 5, 33, 37, 48 I AVDD Analog Power Supply. Connect to analog 3.3 V supply. 6 to 9, 11, 16, 28 to 31 NC No Connect. 10 I

PD

/RST

Power-Down/Reset (Active Low).

12, 25 I DGND Digital Ground. 13 I DVDD Digital Power Supply. Connect to digital 3.3 V supply. 14 I/O AUXDATA2 Auxiliary Data Input 2 (From External ADC 2). 15 I/O AUXDATA1 Auxiliary Data Input 1 (From External ADC 1). 17 I/O AUXBCLK Auxiliary Bit Clock.

18 I/O AUXLRCLK Auxiliary Left-Right Framing Clock. 19 I/O ASDATA2 ADC Serial Data Output 2 (ADC 2 Left and ADC 2 Right)/ADC TDM Data Input. 20 O ASDATA1 ADC Serial Data Output 1 (ADC 1 Left and ADC 1 Right)/ADC TDM Data Output. 21 I/O ABCLK Serial Bit Clock for ADCs. 22 I/O ALRCLK Left-Right Framing Clock for ADCs. 23 I CIN Control Data Input (SPI). 24 I/O COUT Control Data Output (SPI). 26 I CCLK Control Clock Input (SPI). 27 I

CLATCH

Latch Input for Control Data (SPI). 35 O FILTR Voltage Reference Filter Capacitor Connection. Bypass with 10 μF||100 nF to AGND. 38 O CM Common-Mode Reference Filter Capacitor Connection. Bypass with 47 μF||100 nF to AGND. 39 I ADC1LP ADC1 Left Positive Input. 40 I ADC1LN ADC1 Left Negative Input. 41 I ADC1RP ADC1 Right Positive Input. 42 I ADC1RN ADC1 Right Negative Input. 43 I ADC2LP ADC2 Left Positive Input.

Rev. 0 | Page 8 of 24

ANALOG DEVICES AD1974 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TEST CONDITIONS

ANALOG PERFORMANCE SPECIFICATIONS

CRYSTAL OSCILLATOR SPECIFICATIONS

DIGITAL INPUT/OUTPUT SPECIFICATIONS

POWER SUPPLY SPECIFICATIONS

DIGITAL FILTERS

TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS