ANALOG DEVICES AD1954 Service Manual
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reliable. However, no responsibility is assumed by Analog Devices for its
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Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
AD1954
SigmaDSP
5 V 3-Channel Audio DAC System
Accepts Sample Rates up to 48 kHz
7 Biquad Filter Sections per Channel
and Adjustable Time Constants
0 ms to 6 ms Variable Delay/Channel for Speaker Alignment
Stereo Spreading Algorithm for Phat Stereo™ Effect
via SPI Port
200 Parameters via SPI Port
SPI Port Features Safe-Upload Mode for Transparent Filter
2 Control Registers Allow Complete Control of Modes and
70 dB Stop-Band Attenuation
On-Chip Clickless Volume Control
48 kHz Sample Rates
2
S Compatible, and DSP Serial Port Modes
Auxiliary Digital Input
FUNCTIONAL BLOCK DIAGRAM
SERIAL CONTROL
INTERFACE
MCLK
MUX
MCLK
GENERAT
OR
(256f
S
/512fS)
DAC – L
D
AC – R
D
AC – SW
DATA CAPTURE
OUT
AUDIO DAT
A
MUX
26 22
DSP CORE
D
ATA FORMAT:
3.23 (SINGLE PRECISION)
3.45 (DOUBLE PRECISION)
RAM R
OM
3
3
3
3
3
ANALOG
OUTPUTS
AD1954
MASTER CLOCK
OUTPUT
SERIAL DATA
INPUTS
MASTER
CLOCK INPUTS
SERIAL D
ATA
OUTPUT
SPI INPUT
SPI DAT
A
OUTPUT
AUX SERIAL
DATA INPUT
DIGITAL
OUTPUT
Graphical Custom Programming Tools
44-Lead MQFP or 48-Lead LQFP Plastic Package
APPLICATIONS
2.0/2.1 Channel Audio Systems (Two Main Channels plus
Subwoofer)
Automotive Sound Systems
The AD1954 is a complete 26-bit single-chip 3-channel digital
equalization, dual-band compression/limiting, delay compensa-
tion, and image enhancement. These algorithms can be used to
compensate for real-world limitations of speakers, ampli ers, and
listening environments, resulting in a dramatic improvement of
perceived audio quality.
The signal processing used in the AD1954 is comparable to that
found in high-end studio equipment. Most of the processing is
done in full 48-bit double-precision mode, resulting in very good
low-level signal performance and the absence of limit cycles or
idle tones. The compressor/limiter uses a sophisticated two-band
)
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AD1954
TABLE OF CONTENTS
FEATURES/
APPLICATIONS
. . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . .
FUNCTIONAL BLOCK DIAGRAM
. . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. .
3
ABSOLUTE MAXIMUM RATINGS
. . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
PIN CONFIGURATIONS
. . . . . . . . . . . . . . . . . . . . . . . . . . .
PIN FUNCTION DESCRIPTIONS
. . . . . . . . . . . . . . . . . . . .
TYPICAL
PERFORMANCE CHARACTERISTICS
. . . . . . .
(continued from page 1)
. . . . . . .
FEATURES
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . .
PIN FUNCTIONS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . .
Numeric Formats
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal DSP Signal Data Format
. . . . . . . . . . . . . . . . . . . .
High-Pass Filter
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. .
Biquad Filters
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . .
Volume
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Delay
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . .
Main Compressor/Limiter
. . . . . . . . . . . . . . . . . . . . . . . . . .
RMS Time Constant
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RMS Hold Time
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. .
RMS Release Rate
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Look-Ahead
Delay
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Postcompression
Gain
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . .
De-emphasis Filtering
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using the Sub Reinjection Paths for Systems with
No Subwoofer
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . .
Interpolation Filters
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
Volume Registers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. .
Parameter RAM Contents
. . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . .
4
INITIALIZATION
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
Power-Up Sequence
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . .
DATA CAPTURE REGISTERS
. . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . .
DIGITAL CONTROL PINS
. . . . . . . . . . . . . . . . . . . . . . . . .
Mute
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . .
De-emphasis
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . .
ANALOG OUTPUT SECTION
. . . . . . . . . . . . . . . . . . . . . .
30
. . . . . .
3
APPENDIX
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . .
3
. . .
3
. . . . . . . . . . . . . . . . . . . . . . . . . .
3
3
Revision History
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . .
3
4
www.BDTIC.com/ADI
–3
AD1954–SPECIFICATIONS
Test conditions, unless otherwise noted.
, DV
)
Ambient Temperature
Input Clock
Input Signal
Input Sample Rate
48 kHz
Measurement Bandwidth
Word Width
Load Capacitance
Load Impedance
Input Voltage High
Input Voltage Low
ANALOG PERFORMANCE
Parameter
Typ
Max
Unit
RESOLUTION
Bits
No Filter (Stereo)
dB
With A-Weighted Filter
dB
DYNAMIC RANGE (20 Hz to 20 kHz, –60 dB Input) (Left/Right Output)
No Filter
dB
With A-Weighted Filter
dB
TOTAL HARMONIC DISTORTION PLUS NOISE (Left/Right Output)
VO = –0.5 dB
–93
–100
dB
No Filter (Stereo)
dB
With A-Weighted Filter
dB
DYNAMIC RANGE (20 Hz to 20 kHz, –60 dB Input) (Subwoofer Output)
No Filter
dB
With A-Weighted Filter
dB
TOTAL HARMONIC DISTORTION PLUS NOISE (Subwoofer Output)
VO = –0.5 dB
–90
–96
dB
ANALOG OUTPUTS
Differential Output Range (± Full Scale) (Left/Right Output)
V p-p
Differential Output Range (± Full Scale) (Subwoofer Output)
V p-p
V
DC ACCURACY
–5
–8
Interchannel Gain Mismatch
–0.250
dB
ppm/°C
DC Offset
–30
mV
INTERCHANNEL CROSSTALK (EIAJ Method)
–120
dB
INTERCHANNEL PHASE DEVIATION
Degrees
MUTE ATTENUATION
–107
dB
DE-EMPHASIS GAIN ERROR
dB
Performance of right and left channels are identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation speci cations).
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AD1954
(continued)
Parameter
Typ
Max
Unit
Input Voltage High (V
IH
)
V
Input Voltage High (V
IH
) – RESETB
V
Input Voltage Low (V
)
V
Input Leakage (I
@ V
= 2.1 V)
µA
Input Leakage (I
@ V
@ V
= 0.8 V)
= 0.8 V)
µA
High Level Output Voltage (V
OH
), I
OH
DVDD – 0.5
V
Low Level Output Voltage (V
OL
), I
OL
V
Input Capacitance
pF
Parameter
Min
Typ
Max
Unit
Voltage, Analog and Digital
4.5
V
Analog Current
4248mA
Analog Current, Power-Down
40
46
Digital Current
Digital Current, SPI Power-Down
Digital Current, Reset Power-Down
mA
DISSIPATION
mW
mW
325
mW
mW
Reset Power-Down, Both Supplies
465
mW
POWER SUPPLY REJECTION RATIO
–80
dB
–80
dB
ODVDD current is dependent on load capacitance and clock rate.
TEMPERATURE RANGE
Parameter
Min
Typ
Max
Unit
Functionality Guaranteed
–40
–55
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AD1954
–5
Parameter
Min
Typ
Max
Unit
t
DMDC
MCLK Recommended Duty Cycle @ 12.288 MHz (256 f
S
Mode)
45
t
DMDC
MCLK Recommended Duty Cycle @ 24.576 MHz (512 f
S
Mode)
40
t
MCLK Delay (All Mode)
ns
t
DBH
BCLK Low Pulsewidth
ns
t
DBH
BCLK High Pulsewidth
ns
t
BCLK Delay (to BCLKO)
ns
t
DLS
LRCLK Setup
ns
t
DLH
LRCLK Hold
ns
t
DLD
LRCLK Delay (to LRCLKO)
ns
t
DDS
ns
t
ns
t
ns
t
CCL
ns
t
CCH
ns
t
CLS
ns
t
CLH
ns
t
CLD
ns
t
CDS
ns
t
CDH
ns
t
COD
35
ns
t
COH
ns
t
DCD
DCSOUT Delay
35
ns
t
DCH
DCSOUT Hold
ns
t
PD/RST Low Pulsewidth
ns
Parameter
Min
Typ
Max
Unit
Pass-Band Ripple
dB
dB
Pass Band
kHz
S
S
S
sec
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AD1954
–6
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily ac cu mu late on
the human body and test equipment and can discharge without detection. Although the AD1954 features
proprietary ESD pro tec tion circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD pre cau tions are rec om mend ed to avoid per for mance
deg ra da tion or loss of functionality.
ABSOLUTE MAXIMUM RATINGS
DVDD to DGND
. . . . . . . . . . . . . . . . . . . . . . .
–0.3 V to +6 V
. . . . . . . . . . . . . . . . . . . . . .
–0.3 V to +6 V
AVDD to AGND
. . . . . . . . . . . . . . . . . . . . . . . .
–0.3 V to +6 V
Digital Inputs
. . . . . . . . . . . .
DGND – 0.3 V to DVDD + 0.3 V
Analog Inputs
. . . . . . . . . . . . .
AGND – 0.3 V to AVDD + 0.3 V
AGND to DGND
. . . . . . . . . . . . . . . . . . . . .
–0.3 V to + 0.3 V
Reference Voltage
. . . . . . . . . . . . . . . . . . . . .
(AVDD + 0.3)/2 V
Maximum Junction Temperature
. . . . . . . . . . . . . . . . . .
125°C
. . . . . . . . . . . . . .
–65°C to +150°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
300°C/10 sec
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those indicated in the operational section of
this speci cation is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
PIN CONFIGURATIONS
44-LEAD MQFP
3
4
5
6
7
1
2
10
11
8
9
40 39 3841
42
4344 36 35 3437
29
30
31
32
33
27
28
25
26
23
24
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
121314 15 16 17 18 192021 22
RESETB
AVDD
AGND
AGND
VOUTL–
VOUTL+
AVDD
AGND
AVDD
VOUTR+
AD1954
CDATA
LRCLK1
SDATA0
BCLK0
LRCKL0
CCLK
MCLK2
MCLK1
MCLK0
DEEMP/SDATA_AUX
MUTE
DVDD
SDATA2
BCLK2
LRCLK2
SDATA1
BCLK1
VOUTR–
AGND
VOUTS+
VOUTS–
CLATCH
DGND
COUT
ODVDD
BCLKOUT
MCLKOUT
DCSOUT
LRCLKOUT
SDATAOUT
ZEROFLAG
FILTCAP
VREF
DGND
48-LEAD LQFP
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44 39 38 3743 42 41 40
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
NC
AGND
VOUTL–
VOUTL+
AVDD
AGND
AVDD
NC
MCLK2
MCLK1
MCLK0
DEEMP/SDATA_AUX
MUTE
DVDD
NC = NO CONNECT
SDATA2
BCLK2
LRCLK2
SDATA1
VOUTR+
VOUTR–
AGND
VOUTS+
AD1954
BCLK1
VOUTS–
DGND
MCLKOUT
COUT
DCSOUT
ODVDD
LRCLKOUT
BCLKOUT
SDATAOUT
ZEROFLAG
FILTERCAP
VREF
NC
DGND
LRCLK1
SDATA0
BCLK0
LRCLK0
CDATA
CCLK
CLATCH
RESETB
AVDD
AGND
NC
Package Characteristics (44-Lead MQFP)
Min
Typ
Max
Unit
JA
(Thermal Resistance—
Junction to Ambient)
JC
(Thermal Resistance—
Junction to Ambient)
Package Characteristics (48-Lead LQFP)
Typ
Max
Unit
JA
(Thermal Resistance—
Junction to Ambient)
JC
(Thermal Resistance—
Junction to Ambient)
Model
Temperature Range
Package Description
Package Option
AD1954YS
–40°C to +105°C
44-Lead MQFP
AD1954YSRL
–40°C to +105°C
44-Lead MQFP
AD1954YST
–40°C to +105°C
48-Lead LQFP
AD1954YSTRL
–40°C to +105°C
48-Lead LQFP
AD1954YSTRL7
–40°C to +105°C
48-Lead LQFP
EVAL-AD1954EB
Evaluation Board
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AD1954
PIN FUNCTION DESCRIPTIONS
Pin No.
Pin No.
Input/
Mnemonic
Description
NC
No Connect
MCLK2
IN
Master Clock Input 2 256 f
S
/512 f
S
3
MCLK1
IN
Master Clock Input 1 256 f
S
/512 f
S
3
4
MCLK0
IN
Master Clock Input 0 256 f
S
/512 f
S
4
DEEMP/
IN
Enables 44.1 kHz De-emphasis Filter (Others Available through SPI Control)
Auxiliary Serial Data Input
MUTE
IN
Mute Signal. Initiates volume ramp-down.
DVDD
Digital Supply for DSP Core, 4.5 V to 5.5 V
IN
BCLK2
IN
Bit Clock 2
LRCLK2
IN
Left/Right Clock 2
IN
BCLK1
IN
Bit Clock 1
DGND
Digital Ground
LRCLK1
IN
Left/Right Clock 1
IN
BCLK0
IN
Bit Clock 0
LRCLK0
IN
Left/Right Clock 0
IN
IN
IN
RESETB
IN
Reset Signal, Active Low
AVDD
Analog 5 V Supply
AGND
Analog GND
NC
No Connect
VOUTS–
Negative Sub Analog DAC Output
VOUTS+
Positive Sub Analog DAC Output
AGND
Analog GND
VOUTR–
Negative Left Analog DAC Output
VOUTR+
Positive Left Analog DAC Output
30
AVDD
Analog 5 V Supply
31
AGND
Analog GND
3032AVDD
Analog 5 V Supply
3133VOUTL+
Positive Left Analog DAC Output
3234VOUTL–
Negative Left Analog DAC Output
33
35
AGND
Analog GND
36
NC
No Connect
37
NC
No Connect
34
38
VREF
IN
35
39
FILTCAP
IN
3640ZEROFLAG
Zero Flag Output. High when both left and right channels are 0 for 1024 frames.
37
38
BCLKOUT
Bit Clock Mux Output
3943LRCLKOUT
Left/Right Clock Mux Output
40
44
Digital Supply Pin for Output Drivers, 2.5 V to 5.5 V
41
45
DCSOUT
Data Capture Serial Output for Data Capture Registers. Use in conjunction with
selected LRCLK and BCLK to form a 3-wire output.
42
46
43
MCLKOUT
Master Clock Output 512 f
S
/256 f
S
(Frequency Selected by SPI Register)
48
DGND
Digital Ground
For a complete description of the pins, refer to the Pin Functions section.
www.BDTIC.com/ADI
–8
AD1954–Typical Performance Characteristics
0
–160
0 202
4 6 8 14 16 18
–20
–80
–120
–40
–60
–100
–140
10 12
kHz
dB
0
–160
0 202
4 6 8 14 16 18
–20
–80
–120
–40
–60
–100
–140
10 12
kHz
dB
Hz
0
–20
20 10k
–10
1k100
–2
–4
–6
–8
–12
–14
–16
–18
50 200 500 5k
dB
2k
3.0
–3.0
–120 0–100 –80 –20
0.5
–1.0
–2.0
0
–0.5
–1.5
–2.5
–60 –40
dBFS
2.5
1.5
2.0
1.0
dB
–2.0
–120 0–100 –80 –20–60
ms
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
V
PERFORMANCE PLOTS
The following plots demonstrate the performance achieved on the
with a THD+N of –100 dB, which is dominated by a second
har monic. TPC 2 shows an FFT of a –60 dB sine wave, demon-
strating the lack of low-level artifacts. TPC 3 shows a frequency
response plot with the seven equalization biquads set to an alter-
nating pattern of 6 dB boosts and cuts. TPC 4 shows a linearity
plot, where the measurement was taken with the same equalization
curve used to make TPC 3. When the biquad lters are not in use,
the signal passes through the lters with no quantization effects.
TPC 4 therefore demonstrates that using double-precision math
in the biquad lters has virtually eliminated any quantization
with the attack and recovery characteristics plainly visible. The
rms detector was programmed for normal rms time constants;
the hold/decay feature was not used for this plot.
www.BDTIC.com/ADI
AD1954
–9
An extensive SPI port allows click-free parameter updates, along
with read-back capability from any point in the algorithm ow.
The AD1954 includes ADI’s patented multibit
DAC architec-
ture. This architecture provides 112 dB SNR and dynamic range
to be used in applications ranging from low-end boom boxes to
high-end professional mixing/editing systems.
The AD1954 also has a digital output that allows it to be used
purely as a DSP. This digital output can also be used to drive an
external DAC to extend the number of channels beyond the three
that are provided on the chip.
This chip can be used with either its default signal processing
program or with a custom user-designed program. Graphical pro-
gramming tools are available from ADI for custom programming.
FEATURES
The AD1954 is comprised of a 26-bit DSP (48 bits with double
precision) for interpolation and audio processing, three multibit
modulators, and analog output drive circuitry. Other features
include an on-chip parameter RAM that uses a safe-upload feature
for transparent and simultaneous updates of lter coef cients and
digital de-emphasis lters. Also, on-chip input selectors allow up
to three sources of serial data and master clock to be selected.
The 3-channel con guration is especially useful for 2.1 playback
systems that include two satellite speakers and a subwoofer.
The default program allows for independent equalization and
compression/limiting for the satellite and subwoofer outputs.
Figure 1 shows the block diagram of the device.
The AD1954 contains a program RAM that boots from an internal
program ROM on power-up. Signal processing parameters are
stored in a 256-location parameter RAM, which is initialized on
power-up by an internal boot ROM. New values are written to
the parameter RAM using the SPI port. The values stored in the
parameter RAM control the IIR equalization lters, the dual-
band compressor/limiter, the delay values, and the settings of the
stereo spreading algorithm.
The AD1954 has a very sophisticated SPI port that supports
complete read/write capability of both the program and the para-
meter RAM. Two control registers are also provided to control
the chip serial modes and various other optional features. Hand-
shaking is also included for ease of memory uploads/downloads.
The AD1954 contains four independent data capture circuits,
which can be programmed to tap the signal ow of the processor
can be accessed either through a separate serial out pin (i.e., that
can be connected to an external DAC or DSP) or by reading from
the data capture SPI registers. This allows the basic functionality
of the AD1954 to be easily extended.
The processor core in the AD1954 has been designed from the
ground up for straightforward coding of sophisticated compres-
sion/limiting algorithms. The AD1954 contains two independent
compressor/limiters with rms based amplitude detection and
curve that is loaded by the user into a look-up table that resides
in the parameter RAM. The compressor also features look-ahead
compression that prevents compressor overshoots.
continued from page 1
)
3:1
AUDIO
DATA
MUX
1
3
3
SPI PORT
3:1
MCLK
MUX
1
DAC – L
COEFFICIENT
ROM
64 22
26 22
DSP CORE
D
ATA FORMAT:
3.23 (SINGLE PRECISION)
3.45 (DOUBLE PRECISION)
3
3
ANALOG
OUTPUTS
MASTER
CLOCK I/O
GROUP
DCSOUT
SPI I/O
GROUP
3
SERIAL
IN
1
DATA MEMORY, 512 26
CONTROL
REGISTERS
TRAP REG.
(I
2
S, SPI)
SAFELOAD
REGISTERS
PROGRAM
RAM
512 35
PARAMETER
RAM
256 22
BOOT ROM
BOOT ROM
MEMORY CONTROLLERS
DAC – R
DAC – SW
2
BIAS
ANALOG
BIAS GROUP
RESETB MUTE DE-EMPHASIS
ZEROFLAG
NOTES
1
CONTROLLED THROUGH SPI CONTROL REGISTERS.
2
DAC DOES NOT USE DIGITAL INTERPOLATION.
SERIAL D
ATA I/O
GROUP
DCSOUT TRAP
AUX SERIAL
DATA INPUT
MCLK
GENERATOR
1
(256 fS/512 fS IN)
256
f
S
/512 fS OUT
VOLTAGE
REFERENCE
VREF
D
VDD A
VDD ODVDD
3
FILTCAP
AGND DGND
3 2
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AD1954
–10
The AD1954 has a very exible serial data input port, which
chips, AES/EBU receivers, and sample rate converters. The
AD1954 can be con gured in left-justi ed, I
2
DSP serial port compatible modes. It can support 16 bits, 20 bits,
in MSB rst, twos complement format. The part can also be set
up in a 4-channel serial input mode by simultaneously using the
serial input mux and the auxiliary serial input.
The AD1954 operates from a single 5 V power supply. It is fabri-
cated on a single monolithic integrated circuit and is housed in a
44-lead MQFP or 48-lead LQFP package for operation over the
temperature range –40°C to +105°C.
PIN FUNCTIONS
All input pins have a logic threshold compatible with TTL input
levels and can therefore be used in systems with 3.3 V logic. All
digital output levels are controlled by the ODVDD pin, which
may range from 2.7 V to 5.5 V, for compatibility with a wide
range of external devices. (See Pin Function Descriptions table.)
—Serial Data Inputs
writing to Bits 7 and 6 in Control Register 2. Default is 00, which
selects SDATA0. The serial format is selected by writing to Bits 3–0
of Control Register 0. See SPI Read/Write Data Formats section
for recommendations on how to change input sources without
causing a click or pop noise.
LRCLK0, LRCLK1, LRCLK2
—Left/Right Clocks for Framing the
Input Data
The active LRCLK input is selected by writing to Bits 7 and 6
in Control Register 2. The default is 00, which selects LRCLK0.
The interpretation of the LRCLK changes according to the serial
mode, set by writing to Control Register 0.
BCLK0, BCLK1, BCLK2
—Serial Bit Clocks for Clocking in the
The active BCLK input is selected by writing to Bits 7 and 6 in
interpretation of BCLK changes according to the serial mode,
which is set by writing to Control Register 0.
LRCLKOUT, BCLKOUT, SDATAOUT
—Output of Mux that
These pins may be used to send the selected serial input signals
to other external devices. This output pin is enabled by writing a
MCLK0, MCLK1, MCLK2
—Master Clock Inputs
Active input selected by writing to Bits 5 and 4 of Control Regis-
ter 2. The default is 00, which selects MCLK0. The master clock
frequency must be either 256
f
S
or 512
f
S
, where f
S
is the input
sampling rate. The master clock frequency is programmed by
writing to Bit 2 of Control Register 2. The default is 0 (512
S
).
how to change clock sources without causing an audio click or pop.
Note that since the default MCLK source pin is MCLK0, there
must be a clock signal present on this pin on power-up so that
the AD1954 can complete its initialization routine.
MCLKOUT
—Master Clock Output
The master clock output pin may be programmed to produce
either 256
S
, 512
S
, or a copy of the selected MCLK input
pin. This pin is programmed by writing to Bits 1 and 0 of Control
Register 2. The default is 00, which disables the MCLKO pin.
—Serial Data In for the SPI Control Port
—Serial Data Output
This is used for reading back registers and memory locations. It
is three-stated when an SPI read is not active. See SPI Port section
for more information on SPI port timing.
—SPI Bit Rate Clock
This pin either may run continuously or be gated off in between
—SPI Latch Signal
It must go low at the beginning of an SPI transaction and high at the
end of a transaction. Each SPI transaction may take a different
number of CCLKs to complete, depending on the address and
read/write bit that are sent at the beginning of the SPI transaction.
Detailed SPI timing information is given in SPI Port section.
RESETB
—Active Low Reset Signal
After RESETB goes high, the AD1954 goes through an initial-
ization sequence where the program and parameter RAMs are
initialized with the contents of the on-board boot ROMs. All
initialization is complete after 1024 MCLK cycles. Since the
MCLK IN FREQ SELECT (Bit 2 in Control Register 2) defaults
to 512
S
at power-up, this initialization will proceed at the
external MCLK rate and will take 1024 MCLK cycles to com-
plete, regardless of the absolute frequency of the external MCLK.
New values should not be written to the SPI port until the initial-
ization is complete.
ZEROFLAG
—Zero-Input Indicator
This pin will go high if both serial inputs have been inactive (zero
data) for 1024 LRCLK cycles. This pin may be used to drive an
external mute FET for reduced noise during digital silence. This
pin also functions as a test out pin, controlled by the test register
end user, one may be of some use. If the Test Register is pro-
grammed with the number 7 (decimal), the ZEROFLAG output
will be switched to the output of the internal pseudo-random noise
generator. This noise generator operates at a bit rate of 128
f
S
used to generate white noise (or, with appropriate ltering, pink
noise) to be used as a test signal for measuring speakers or room
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AD1954
DCSOUT
—Data Capture Serial Out
This pin will output the DSP’s internal signals, which can be used
by external DACs or other signal processing devices. The signals
that are captured and output on the DCSOUT pin are controlled
by writing program counter trap numbers to SPI Addresses 263
nal program counter contents are equal to the trap values written
to the SPI port, the selected DSP register is transferred to the
DCSOUT parallel-to-serial registers and shifted out on the
DCSOUT pin. Table XX shows the program counter trap values
nal points of the algorithm ow.
The DCSOUT pin is meant to be used in conjunction with the
LRCLK and BCLK signals that are provided to the serial input
port. The format of DCSOUT is the same as the format used
for the serial port. In other words, if the serial port is running in
I
3-wire I
2
The DCSOUT pin can be used for a variety of purposes. If the
DCSOUT pin is used to drive another external DAC, then a
4.1 system is possible using a new program downloaded into the
program RAM.
DEEMP/SDATA_AUX
—De-emphasis Input Pin/Auxiliary Serial
Data Input
In de-emphasis mode, if this pin is asserted high, then a digital
de-emphasis lter will be inserted into the signal ow. The
de-emphasis curve is valid only for a sample rate of 44.1 kHz;
curves for 32 kHz and 48 kHz may be programmed using the
data input. This function is set by writing a 1 to Bit 11 of Control
Register 1. The same clocks are used for this serial input as are
used for the SDATA0, SDATA1, and SDATA2 signals. This serial
input can only be used in the signal processing ow when using
Analog Devices’ custom programming tools; see the Graphical
still available while this pin is used as a serial input but only
through SPI control.
MUTE
—Mute Output Signal
When this pin is asserted high, a ramp sequence is started, which
gradually reduces the volume to zero. When de-asserted, the volume
ramps from zero back to the original volume setting. The ramp
speed is timed so that it takes 10 ms to reach 0 volume when starting
from the default 0 dB volume setting.
VOUTL+, VOUTL2
—Left Channel Differential Analog Outputs
Full-scale outputs correspond to 1 Vrms on each output pin or
The full-scale swing scales directly with VREF. These outputs are
capable of driving a load of >5 k
, with a maximum peak current
of 1 mA from each pin. An external third order lter is recom-
mended for ltering out-of-band noise.
VOUTR+, VOUTR2
—Right Channel Differential Outputs
left channel
VOUTL+, VOUTL–.
VOUTS+, VOUTS2
—Subchannel Differential Outputs
These outputs are designed to drive loads of 10 k
or greater,
with a peak current capability of 250 µA. This output does not
use digital interpolation, since it is intended for low frequency
VREF
—Analog Reference Voltage Input
The nominal VREF input voltage is 2.5 V; the analog gain scales
directly with the voltage on this pin. When using the AD1954 to
drive a power ampli er, it is recommended that the VREF voltage
be derived by dividing down and heavily ltering the supply to the
power ampli er. This provides a bene t if the compressor/limiter
in the AD1954 is used to prevent ampli er clipping. In this case, if
the DAC output voltage is scaled to the ampli er power supply, a
xed compressor threshold can be used to protect an ampli er
whose supply may vary over a wide range. Any ac signal on this
pin will cause distortion, and therefore, a large decoupling capaci-
tor may be necessary to ensure that the voltage on VREF is clean.
The input impedance of VREF is greater than 1 M
FILTCAP
—Filter Capacitor Point
This pin is used to reduce the noise on an internal biasing point
in order to provide the highest performance. It may not be neces-
sary to connect this pin, depending on the quality of the layout
DVDD
—Digital VDD for Core
—Digital VDD for All Digital Outputs
Variable from 2.7 V to 5.5 V.
DGND (2)
—Digital Ground
AVDD (3)
—Analog VDD
Bypass capacitors should be placed close to the pins and connected
directly to the analog ground plane.
AGND (3)
—Analog Ground
For best performance, separate nonoverlapping analog and digital
ground planes should be used.
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