Analog Devices AD1941 pE Datasheet

SigmaDSPTM Multichannel

Preliminary Technical Data

FEATURES

16-channel digital audio processor
Accepts sample rates up to 192 kHz
28-bit × 28-bit multiplier with full 56-bit accumulator
Fully-programmable program RAM for custom

program download
Parameter RAM allows complete control of 1,024 parameters
Control port features safeload for transparent parameter

updates and complete mode and memory transfer control
Target/slew RAM for click-free volume control and dynamic

parameter updates
Double precision mode for full 56-bit processing
PLL for generating MCLK from 64 × f

clocks

512 × f

S

Hardware-accelerated DSP core
21 kB (6,144 words) data memory for up to 128 ms of audio

delay at f

= 48 kHz

s

Flexible serial data port with I

and right-justified serial port modes
8- and 16-channel TDM input/output modes
On-chip voltage regulator for compatibility with 3.3 V and

5 V systems
Programmable low power mode
Fast start-up and boot time from power on or reset
48-lead LQFP plastic package

GENERAL DESCRIPTION

The AD1941 is a complete 28-bit, single-chip, multichannel
audio DSP for equalization, multiband dynamics processing,
delay compensation, speaker compensation, and image
enhancement. These algorithms can be used to compensate for
the real-world limitations of speakers, amplifiers, and listening
environments, resulting in a dramatic improvement of
perceived audio quality.

The signal processing used in the AD1941 is comparable to that
found in high end studio equipment. Most of the processing is
done in full, 56-bit double-precision mode, resulting in very
good low level signal performance and the absence of limit
cycles or idle tones. The dynamics processor uses a sophisti­cated, multiple-breakpoint algorithm often found in high end
broadcast compressors.

, 256 × fS, 384 × fS, or

S

2

S compatible, left-justified,

28-Bit Audio Processor

AD1941

APPLICATIONS

Automotive sound systems
Digital televisions
Home theater systems (Dolby Digital/DTS postprocessor)
Multichannel audio systems
Mini-component stereos
Multimedia audio
Digital speaker crossover
Musical instruments
In-seat sound systems (aircrafts/motor coaches)

FUNCTIONAL BLOCK DIAGRAM

4

AD1940

VOLTAGE

REGULATOR

2

SERIAL DATA/

TDM INPUTS

MASTER

CLOCK

INPUT

SPI I/O

4

PLL

SERIAL

CONTROL

INTERFACE

Figure 1.

The AD1941 is a fully-programmable DSP. Easy to use software
allows the user to graphically configure a custom signal
processing flow using blocks such as biquad filters, dynamics
processors, and surround sound processors. An extensive
control port allows click-free parameter updates, along with
readback capability from any point in the algorithm flow.

The AD1941’s digital input and output ports allow a glueless
connection to ADCs and DACs by multiple, 2-channel serial
data streams or TDM data streams. When in TDM mode, the
AD1941 can input 8 or 16 channels of serial data, and can
output either 8 or 16 channels of serial data. The input and
output port configurations can be individually set. The AD1941

2

is controlled on a 2-wire I

C bus.

28 × 28

DSP CORE

DATA FORMAT:

5.23 (SINGLE
PRECISION)

10.46 (DOUBLE
PRECISION)

RAM ROM

2
2

SERIAL
DATA/
TDM
OUTPUTS

04607-0-001

Rev. PrE

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

AD1941 Preliminary Technical Data

TABLE OF CONTENTS

Specifications..................................................................................... 3

RAMs and Registers....................................................................... 16

Digital I/O ..................................................................................... 3

Power.............................................................................................. 3

Temperature Range ...................................................................... 3

Digital Timing............................................................................... 4

PLL ................................................................................................. 4

Regulator........................................................................................ 4

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Digital Timing Diagrams................................................................. 6

Pin Configuration and Function Descriptions............................. 8

Features............................................................................................ 10

Pin Functions.............................................................................. 11

Signal Processing ............................................................................ 13

Overview...................................................................................... 13

Numeric Formats........................................................................ 13

Control Port Addressing............................................................ 16

Parameter RAM Contents......................................................... 16

Recommended Program/Parameter Loading Procedures.... 17

Target/Slew RAM ....................................................................... 17

Safeload Registers....................................................................... 19

Data Capture Registers.............................................................. 20

DSP Core Control Register....................................................... 20

RAM Configuration Register ................................................... 21

Control Port Read/Write Data Formats.................................. 22

Serial Data Input/Output Ports .................................................... 24

Serial Output Control Registers ............................................... 26

Serial Input Control Register.................................................... 26

Initialization.................................................................................... 29

Power-Up Sequence................................................................... 29

Setting Master Clock/PLL Mode.............................................. 29

Programming.............................................................................. 13

Control Port.....................................................................................14

Overview...................................................................................... 14

2

I

C Port ........................................................................................ 14

Voltage Regulator....................................................................... 29

Outline Dimensions....................................................................... 30

Ordering Guide .......................................................................... 30

Rev. PrE | Page 2 of 32

Preliminary Technical Data AD1941

SPECIFICATIONS

Test conditions, unless otherwise noted.

Table 1.

Parameter Conditions

Supply Voltage (VDD) 2.5 V
PLL Voltage (PLL_VDD) 2.5 V
Output Voltage (ODVDD) 5.0 V
INVDD Voltage 5.0 V
Ambient Temperature 25°C
Master Clock Input 3.072 MHz, 64 × fs mode
Load Capacitance 50 pF
Load Current ±1 mA
Input Voltage, HI 2.4 V
Input Voltage, LO 0.8 V

DIGITAL I/O

Table 2. Digital I/O1

Parameter Min Max Unit

Input Voltage, HI (VIH) 2.1 V
Input Voltage, LO (VIL) 0.8 V
Input Leakage (IIH) 10 µA
Input Leakage (IIL) 10 µA
High Level Output Voltage (VOH) ODVDD = 4.5 V, IOH = 1 mA 3.9 V
High Level Output Voltage (VOH) ODVDD = 3.0 V, IOH = 1 mA 2.6 V
Low Level Output Voltage (VOL) ODVDD = 4.5 V, IOL = 1 mA 0.4 V
Low Level Output Voltage (VOL) ODVDD = 3.0 V, IOL = 1 mA 0.3 V
Input Capacitance 5 pF

1

All measurements across −40°C to 125°C (case) and across VDD = 2.25 V to 2.75 V.

POWER

Table 3.

Parameter Min Typ Max1 Unit

Supplies

Voltage 2.25 2.5 2.75 V
Digital Current 92 1552 mA
PLL Current 3.5 8 mA
Digital Current, Reset 4.53 133 mA
PLL Current, Reset 3 8.5 mA

Dissipation

Operation, all supplies 238.8 mW
Reset, all supplies 10.8 mW

1

Maximum specifications are measured across −40°C to 125°C (case) and across VDD = 2.25 V to 2.75 V.

2

Measurement running a typical large program that writes to all 16 outputs with 0 dB digital sine waves applied to all eight inputs. Your program may differ.

3

The digital reset current is specified for the given test conditions. This current scales with the input MCLK rate, so higher input clocks draw more current while in reset.

TEMPERATURE RANGE

Table 4.

Parameter Min Typ Max Unit

Functionality Guaranteed –40 +105 °C Ambient
–40 +125 °C Case

Rev. PrE | Page 3 of 32

AD1941 Preliminary Technical Data

DIGITAL TIMING

Table 5 Digital Timing1

Parameter Comments Min Max Unit

tMP MCLK Period 512 fS mode 36 244 ns
tMP MCLK Period 384 fS mode 48 366 ns
tMP MCLK Period 256 fS mode 73 488 ns
tMP MCLK Period 64 fS mode 291 1953 ns
tMP MCLK Period Bypass mode 12 ns
t

MCLK Duty Cycle Bypass mode 40 60 %

MDC

t

BCLK_IN LO Pulse Width 4 ns

BIL

t

BCLK_IN HI Pulse Width 2 ns

BIH

t

LRCLK_IN Setup To BCLK_IN rising 12 ns

LIS

t

LRCLK_IN Hold From BCLK_IN rising 0 ns

LIH

t

SDATA_INx Setup To BCLK_IN rising 3 ns

SIS

t

SDATA_INx Hold From BCLK_IN rising 2 ns

SIH

t

LRCLK_OUTx Setup Slave mode 2 ns

LOS

t

LRCLK_OUTx Hold Slave mode 2 ns

LOH

tTS

t

SODS

t

SODM

t

RLPW

BCLK_OUTx Falling to
LRCLK_OUTx Timing Skew

SDATA_OUTx Delay Slave mode, from BCLK_OUTx falling 17 ns

SDATA_OUTx Delay Master mode, from BCLK_OUTx falling 17 ns

RESETB LO Pulse Width 10 ns

1

All timing specifications are given for the default (I2S) states of the serial input control port and the serial output control ports. See Table 32.

2 ns

PLL

Table 6.

Parameter Min Typ Max Unit

Lock Time 3 20 ms

REGULATOR

Table 7.

Parameter Min Typ Max Unit

VSENSE Output Voltage 2.25 2.5 2.68 V

Rev. PrE | Page 4 of 32

Preliminary Technical Data AD1941

ABSOLUTE MAXIMUM RATINGS

Table 8.

Parameter Min Max Unit

VDD to DGND –0.3 +3.0 V
PLL_ VDD to PGND –0.3 +3.0 V
OD VDD to DGND –0.3 +6.0 V
INVDD to DGND ODVDD +6.0 V
Digital Inputs DGND – 0.3 INVDD + 0.3 V
Maximum Junction Temperature 135 °C
Storage Temperature Range –65 +150 °C
Soldering (10 sec) 300 °C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Table 9. Package Characteristics

Parameter Min Typ Max Unit

θJA Thermal Resistance (Junction-to-Ambient) 72 °C/W
θJC Thermal Resistance (Junction-to-Case) 19.5 °C/W

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. PrE | Page 5 of 32

AD1941 Preliminary Technical Data

DIGITAL TIMING DIAGRAMS

BCLK_IN

LRCLK_IN

SDATA_INX

LEFT-JUSTIFIED

MODE

SDATA_INX

2

I

S-JUSTIFIED

MODE

SDATA_INX

RIGHT-JUSTIFIED

MODE

BCLK_OUTX

LRCLK_OUTX

t

BIH

t

BIL

t

LIS

t

SIS

MSB

t

SIH

8-BIT CLOCKS
(24-BIT DATA)

12-BIT CLOCKS
(20-BIT DATA)

14-BIT CLOCKS
(18-BIT DATA)

16-BIT CLOCKS
(16-BIT DATA)

t

SIS

MSB-1

MSB

t

SIH

t

SIS

MSB

t

SIH

Figure 2. Serial Input Port Timing

t

BIH

t

BIL

t

LOS

t

LCH

t

LIH

t

SIS

LSB

t

SIH

04607-0-013

t

TS

SDATA_OUTX

LEFT-JUSTIFIED

MODE

SDATA_OUTX

2

I

S-JUSTIFIED

MODE

SDATA_OUTX

RIGHT-JUSTIFIED

MODE

t

SDDS

t

SDDM

MSB

8-BIT CLOCKS
(24-BIT DATA)

12-BIT CLOCKS
(20-BIT DATA)

14-BIT CLOCKS
(18-BIT DATA)

16-BIT CLOCKS
(16-BIT DATA)

t

SDDS

t

SDDM

MSB-1

MSB

Figure 3. Serial Output Port Timing

Rev. PrE | Page 6 of 32

t

SDDS

t

SDDM

MSB

LSB

04607-0-014

Preliminary Technical Data AD1941

t

MP

MCLK

RESETB

t

RLPW

Figure 4. Master Clock and Reset Timing

04607-0-016

Rev. PrE | Page 7 of 32

AD1941 Preliminary Technical Data

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TA_OUT6
SDA

L
C
S

TA_OUT5

ODVDD

SDA

C

C
N

N

_OUT4

SDATA

B
T
E
S
E
R

VDD

36
35
34
33
32
31
30
29
28

27
26
25

D
N
G

GND
BCLK_OUT1
LRCLK_OUT1
ODVDD
SDATA_OUT3
SDATA_OUT2
SDATA_OUT1
SDATA_OUT0
ODVDD
BCLK_OUT0
LRCLK_OUT0
VDD

04607-0-011

VDD

MCLK

RESERVED
PLL_CTRL0
PLL_CTRL1
PLL_CTRL2

PLL_GND

PLL_VDD

I2C_FILT_EN

LRCLK_IN

BCLK_IN

GND

NC = NO CONNECT

Figure 5. 48-Lead LQFP Pin Configuration, AD1941

IVE

SENSE

GND

VREF

VDR

48 47 46 45 44 39 38 3743 42 41 40

1

PIN 1
INDICATOR

2
3
4
5
6
7
8

9
10
11
12

13 14 15 16 17 18 19 20 21 22 23 24

1

D

N

D

I
_

V

A
T
A
D
S

SDATA_IN0

DATA_OUT7

V

VSUPPLY

INVDDS

AD1941

TOP VIEW

(Not to Scale)

3

2

A

N

N

D

I

I

_

_

S

A

A

T

T

A

A

ADR_SEL

D

D

S

S

Table 10. Pin Function Descriptions

Pin No. I/O Mnemonic Description
1, 25, 37 VDD Core Power.
2 IN MCLK Master Clock Input.
3, 21, 22 RESERVED These pins should be connected to ground.
4 IN PLL_CTRL0 PLL Control 0.
5 IN PLL_CTRL1 PLL Control 1.
6 IN PLL_CTRL2 PLL Control 2.
7 PLL_GND PLL Ground.
8 PLL_VDD PLL Power.
9 IN I2C_FILT_ENB I2C Filter Enable, Active Low.
10 IN LRCLK_IN Left/Right Clock for Serial or TDM Data Inputs.
11 IN BCLK_IN Bit Clock for Serial or TDM Data Inputs.
12, 24, 36, 48 GND Digital Ground.
13 VDD Core Power.
14 IN SDATA_IN0 Serial Data Input 0.
12 IN SDATA_IN1 Serial Data Input 1.
16 IN SDATA_IN2/TDM_IN1 Serial Data Input 2/TDM Input 1.
17 IN SDATA_IN3/TDM_IN0 Serial Data Input 3/TDM Input 0.
18 IN ADR_SEL Control Port Address Select.
19 IN/OUT SDA I2C Serial Data I/O.
20 IN SCL I2C Clock.
23 IN RESETB Reset the AD1941.
26 IN/OUT LRCLK_OUT0 Left/Right Clock Output 0.
27 IN/OUT BCLK_OUT0 Bit Clock Output 0.
28, 33, 40 ODVDD Power connection for Output Pins.
29 OUT SDATA_OUT0/TDM_O0 Serial Data Output 0/TDM (16- or 8-Channel) Output 0
30 OUT SDATA_OUT1 Serial Data Output 1.
31 OUT SDATA_OUT2 Serial Data Output 2.
32 OUT SDATA_OUT3 Serial Data Output 3.

Rev. PrE | Page 8 of 32

Preliminary Technical Data AD1941

Pin No. I/O Mnemonic Description
34 IN/OUT LRCLK_OUT1 Left/Right Clock Output 1.
35 IN/OUT BCLK_OUT1 Bit Clock Output 1.
38 OUT SDATA_OUT4/TDM_O1 Serial Data Output 4./TDM (8-Channel) Output 1
39 OUT SDATA_OUT5 Serial Data Output 5.
41 OUT SDATA_OUT6 Serial Data Output 6.
42 OUT SDATA_OUT7/DCSOUT Serial Data Output 7/Data Capture Output.
43 INVDD Input Voltage Reference.
44 IN VSUPPLY Voltage Level Input to Regulator. Usually 3.3 V or 5 V.
45 IN VSENSE Digital Power Level. Should be tied to VDD.
46 OUT VDRIVE Drive for External PNP Transistor.
47 OUT VREF Reference Level for Voltage Regulator.

Rev. PrE | Page 9 of 32

AD1941 Preliminary Technical Data

FEATURES

The core of the AD1941 is a 28-bit DSP (56-bit with double
precision) optimized for audio processing.

The AD1941 contains a program RAM that is initialized from
an internal program ROM on power-up. The program RAM
can be loaded with a custom program after power-up. Signal
processing parameters are stored in a 1024-location parameter
RAM, which is initialized on power-up by an internal boot­ROM. New values are written to the parameter RAM using the
control port. The values stored in the parameter RAM control
individual signal processing blocks, such as IIR equalization
filters, dynamics processors, audio delays, and mixer levels. A
safeload feature allows parameters to be transparently updated
without causing clicks on the output signals.

The target/slew RAM contains 64 locations and can be used as
channel volume controls or for other parameter updates. These
RAM locations take a target value for a given parameter and
ramp the current parameter value to the new value using a
specified time constant and one of a selection of linear or
logarithmic curves.

The AD1941 contains eight independent data capture circuits
that can be programmed to tap the signal flow of the processor
at any point in the DSP algorithm flow. Six of these captured
signals can be accessed by reading from the data capture
registers through the control port. The remaining two data
capture registers can be used to send any internal captured
signal to a stereo digital output signal on Pin SDATA_OUT7 for
driving external DACs or digital analyzers.

The AD1941 has very flexible serial data input/output ports that
allows for glueless interconnection to a variety of ADCs, DACs,
general-purpose DSPs, S/PDIF receivers, and sample rate

2

converters. The AD1941 can be configured in I

S, left-justified,
right-justified, or TDM serial port compatible modes. It can
support 16, 20, and 24 bits in all modes. The AD1941 accepts
serial audio data in MSB first and twos complement format.

The AD1941 operates from a single 2.5 V power supply. It is
fabricated on a single monolithic integrated circuit and is
housed in a 48-lead LQFP package for operation over the
–40°C to +105°C temperature range.

The AD1941 has a sophisticated control port that supports
complete read/write capability of all memory locations. Five
control registers (core, RAM configuration, Serial Output 0 to 7,
Serial Output 8 to 15, and serial input) are provided to offer
complete control of the chip’s configuration and serial modes.
Handshaking is included for ease of memory
uploads/downloads.

DATA MEMORY

6k × 28

TARGET/SLEW

RAM

64 × 28

INPUT

INPUT

2

2

4

MCLK

PLL

SERIAL

CONTROL

PORT

CONTROL

REGISITER
TRAP REG.

SAFELOAD

REGISTER

BOOT ROM

PROGRAM

RAM

1536 × 40

SERIAL

DATA/TDM

GROUP

PLL MODE

SELECT

MASTER

CLOCK

SPI I/O

GROUP

RESETB

Figure 6. Block Diagram

28 × 28

DSP CORE

DATA FORMAT:

5.23 (SINGLE PRECISION)

10.46 (DOUBLE PRECISION)

BOOT ROM

PARAMETER

RAM

1024 × 28

COEFFICIENT

512 × 28

VOLTAGE REGULATORMEMORY CONTROLLERS

ROM

2
2

4

SERIAL DATA/
TDM OUTPUT
GROUP

REGULATOR
GROUP

04607-0-003

Rev. PrE | Page 10 of 32