ANALOG DEVICES AD1941 Service Manual

SigmaDSP Multichannel

FEATURES

16-channel digital audio processor
Accepts sample rates up to 192 kHz
28-bit × 28-bit multiplier with full 56-bit accumulator
Fully programmable program RAM for custom

program download
Parameter RAM allows complete control of 1,024 parameters
Control port features safeload for transparent parameter

updates and complete mode and memory transfer control
Target/slew RAM for click-free volume control and dynamic

parameter updates
Double precision mode for full 56-bit processing
PLL for generating MCLK from 64 × f

clocks

512 × f

S

Hardware-accelerated DSP core
21 kB (6,144 words) data memory for up to 128 ms of audio

delay at f

= 48 kHz

s

Flexible serial data port with I

and right-justified serial port modes
8- and 16-channel TDM input/output modes
On-chip voltage regulator for compatibility with 3.3 V and

5 V systems
Programmable low power mode
Fast start-up and boot time from power-on or reset
48-lead LQFP plastic package

GENERAL DESCRIPTION

The AD1940/AD1941 are a complete 28-bit, single-chip, multi-

channel audio SigmaDSP
processing, delay compensation, speaker compensation, and
image enhancement. These algorithms can be used to compen­sate for the real world limitations of speakers, amplifiers, and
listening environments, resulting in a dramatic improvement of
perceived audio quality.

The signal processing used in the AD1940/AD1941 is
comparable to that found in high end studio equipment. Most
of the processing is done in full, 56-bit double-precision mode,
resulting in very good, low level signal performance and the
absence of limit cycles or idle tones. The dynamics processor
uses a sophisticated, multiple-breakpoint algorithm often found
in high end broadcast compressors.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

™ for equalization, multiband dynamic

, 256 × fS, 384 × fS, or

S

2

S-compatible, left-justified,

28-Bit Audio Processor

AD1940/AD1941

APPLICATIONS

Automotive sound systems
Digital televisions
Home theater systems (Dolby digital/DTS postprocessor)
Multichannel audio systems
Mini-component stereos
Multimedia audio
Digital speaker crossover
Musical instruments
In-seat sound systems (aircrafts/motor coaches)

FUNCTIONAL BLOCK DIAGRAM

4

AD1940/AD1941

VOLTAGE

REGULATOR

2

DATA FORMAT:

5.23 (SINGLE

10.46 (DOUBLE

RAM ROM

Figure 1.

28 × 28

DSP CORE

PRECISION)

PRECISION)

SERIAL DATA/

TDM INPUTS

MASTER

CLOCK

INPUT

2

SPI/I

C I/O

4

PLL

SERIAL

CONTROL

INTERFACE

The AD1940/AD1941 are a fully programmable DSP. Easy to
use software allows the user to graphically configure a custom
signal processing flow using blocks such as biquad filters, dyna­mics processors, and surround sound processors. An extensive
control port allows click-free parameter updates, along with
readback capability from any point in the algorithm flow.

The AD1940/AD1941’s digital input and output ports allow a
glueless connection to ADCs and DACs by multiple, 2-channel
serial data streams or TDM data streams. When in TDM mode,
the AD1940/AD1941 can input 8 or 16 channels of serial data,
and can output 8 or 16 channels of serial data. The input and
output port configurations can be individually set. The AD1940

is controlled by a 4-wire SPI

a 2-wire I

2

C® bus. Other than the control interface, the functions

® port; the AD1941 is controlled by

of the two parts are identical.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

www.analog.com

2
2

SERIAL
DATA/
TDM
OUTPUTS

04607-0-001

AD1940/AD1941

TABLE OF CONTENTS

Specifications..................................................................................... 3

AD1941 I2C Port......................................................................... 15

Digital I/O ..................................................................................... 3

Power.............................................................................................. 3

Digital Timing............................................................................... 4

PLL ................................................................................................. 5

Regulator........................................................................................ 5

Temperature Range ...................................................................... 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Digital Timing Diagrams................................................................. 7

Pin Configuration and Function Descriptions............................. 9

Features ............................................................................................ 11

Pin Functions ..............................................................................12

Signal Processing ............................................................................ 14

Overview...................................................................................... 14

Numeric Formats........................................................................ 14

RAMs and Registers....................................................................... 19

Control Port Addressing............................................................ 19

Parameter RAM Contents......................................................... 19

Recommended Program/Parameter Loading Procedures.... 20

Targ e t/Sl ew RAM ....................................................................... 20

Safeload Registers....................................................................... 23

Data Capture Registers .............................................................. 23

DSP Core Control Register ....................................................... 24

RAM Configuration Register ................................................... 25

Control Port Read/Write Data Formats .................................. 25

Serial Data Input/Output Ports .................................................... 28

Serial Output Control Registers ............................................... 30

Serial Input Control Register.................................................... 30

Initialization .................................................................................... 33

Power-Up Sequence ................................................................... 33

Programming.............................................................................. 14

Control Port..................................................................................... 15

Overview...................................................................................... 15

AD1940 SPI Port ........................................................................15

REVISION HISTORY

4/05—Rev. 0 to Rev. A

Added AD1941............................................................... Universal

Changes to Specifications............................................................3

Changes to Pin Function Descriptions......................................9

Changes to Features Section......................................................11

Changes to Pin Functions Section............................................13

Addition of AD1940 SPI Port Section .....................................15

Added Table 13 to Table 16 .......................................................18

7/04—Revision 0: Initial Version

Setting Master Clock/PLL Mode.............................................. 33

Volt a ge Re gu lat o r ....................................................................... 33

Outline Dimensions....................................................................... 35

Ordering Guide .......................................................................... 35

Rev. A | Page 2 of 36

AD1940/AD1941

SPECIFICATIONS

Test conditions, unless otherwise noted.

Table 1.

Parameter Conditions

Supply Voltage (VDD) 2.5 V
PLL Voltage (PLL_VDD) 2.5 V
Output Voltage (ODVDD) 5.0 V
INVDD Voltage 5.0 V
Ambient Temperature 25°C
Master Clock Input 3.072 MHz, 64 × fs mode
Load Capacitance 50 pF
Load Current ±1 mA
Input Voltage, HI 2.4 V
Input Voltage, LO 0.8 V

DIGITAL I/O

VDD = 2.25 V to 2.75 V. Specifications measured across −40°C to 125°C (case).

Table 2.

Parameter Comments Min Max Unit

Input Voltage, HI (VIH) 2.1 V
Input Voltage, LO (VIL) 0.8 V
Input Leakage (IIH) 10 µA
Input Leakage (IIL) 10 µA
High Level Output Voltage (VOH) ODVDD = 4.5 V, IOH = 1 mA 3.9 V
High Level Output Voltage (VOH) ODVDD = 3.0 V, IOH = 1 mA 2.6 V
Low Level Output Voltage (VOL) ODVDD = 4.5 V, IOL = 1 mA
Low Level Output Voltage (VOL) ODVDD = 3.0 V, IOL = 1 mA1 0.3 V
Input Capacitance 5 pF

1

SDA is measured with a 3 mA sink current.

1

0.4 V

POWER

Table 3.

Parameter Min Typ Max

SUPPLIES

Voltage 2.25 2.5 2.75 V

Digital Current 92 155

PLL Current 3.5 8 mA

Digital Current, Reset 4.5

3

PLL Current, Reset 3 8.5 mA
DISSIPATION

Operation, All Supplies 238.8 mW

Reset, All Supplies 10.8 mW

1

Maximum specifications are measured across −40°C to 125°C (case) and across VDD = 2.25 V to 2.75 V.

2

Measurement running a typical large program that writes to all 16 outputs with 0 dB digital sine waves applied to all eight inputs. The end user’s program may differ.

3

The digital reset current is specified for the given test conditions. This current scales with the input MCLK rate, so higher input clocks draw more current while in reset.

Rev. A | Page 3 of 36

1

Unit

2

mA

133 mA

AD1940/AD1941

DIGITAL TIMING

VDD = 2.25 to 2.75 V. Specifications measured across –40°C to 125°C.

Table 4. Digital Timing

Parameter Mnemonic Comments Min Max Unit

MASTER CLOCK, SERIAL DATA PORTS, RESET

MCLK Period t
MCLK Period tMP 384 fS mode 48 366 ns
MCLK Period tMP 256 fS mode 73 488 ns
MCLK Period tMP 64 fS mode 291 1953 ns
MCLK Period tMP Bypass mode 12 ns
MCLK Duty Cycle t
BCLK_IN LO Pulse Width t
BCLK_IN HI Pulse Width t
LRCLK_IN Setup t
LRCLK_IN Hold t
SDATA_INx Setup t
SDATA_INx Hold t
LRCLK_OUTx Setup t
LRCLK_OUTx Hold t
BCLK_OUTx Falling to LRCLK_OUTx

Timing Skew

SDATA_OUTx Delay

SDATA_OUTx Delay

RESETB LO Pulse Width t

SPI PORT (AD1940)

CCLK Pulse Width LO t
CCLK Pulse Width HI t
CLATCH Setup t
CLATCH Hold t
CLATCH Pulse Width HI t
CDATA Setup t
CDATA Hold t
COUT Delay t

I2C PORT (AD1941)

SCL Clock Frequency f
SCL Low t
SCL High t
Setup Time (Start Condition) t

Hold Time (Start Condition) t

Setup Time (Stop Condition) t
Data Setup Time t
SDA and SCL Rise Time t
SDA and SCL Fall Time t
Bus-Free Time t

1

All timing specifications are given for the default (I2S) states of the serial input control port and the serial output control ports. See Ta . ble 37

2

These specifications are based on the internal master clock period in a specific application. In normal operation, the master clock runs at 1,536 × fs, so the internal

master clock at f

= 48 kHz has a 14 ns period. The values in parentheses are the timing values for fs = 48 kHz.

s

1

MP

Bypass mode 40 60 %

MDC

4 ns

BIL

2 ns

BIH

To BCLK_IN rising 12 ns

LIS

From BCLK_IN rising 0 ns

LIH

To BCLK_IN rising 3 ns

SIS

From BCLK_IN rising 2 ns

SIH

Slave mode 2 ns

LOS

LOH

t

TS

t

Slave mode, from

SODS

t

Master mode, from

SODM

10 ns

RLPW

CCPL

CCPH

CLS

CLH

CLPH

CDS

CDH

COD

SCL

SCLL

SCLH

SCS

512 fS mode 36 244 ns

Slave mode 2 ns
2 ns

BCLK_OUTx falling

BCLK_OUTx falling

1 × INTMCLK (14)
1 × INTMCLK (14)

17 ns

17 ns

2

ns

2

ns
To CCLK rising 0 ns
From CCLK rising 2 × INTMCLK + 4 (32)2 ns
2 × INTMCLK (28)

2

ns
To CCLK rising 0 ns
From CCLK rising 2 × INTMCLK + 2 (30)2 ns
From CCLK rising 4 × INTMCLK +18 (74)2ns

400 kHz

1.3 µs

0.6 µs
Relevent for repeated start

0.6 µs

condition

SCH

First clock generated after

0.6 µs

this period

SSH

DS

SR

SF

BFT

0.6 µs
100 ns
300 ns
300 ns
Between stop and start 1.3 µs

Rev. A | Page 4 of 36

AD1940/AD1941

PLL

VDD = 2.25 to 2.75 V. Specifications measured across –40°C to 125°C.

Table 5.

Parameter Min Typ Max Unit

Lock Time 3 20 ms

REGULATOR

VDD = 2.25 to 2.75 V. Specifications measured across –40°C to 125°C.

Table 6.

Parameter Min Typ Max Unit

VSENSE Output Voltage 2.25 2.5 2.68 V

TEMPERATURE RANGE

Table 7.

Parameter Min Typ Max Unit

Functionality Guaranteed –40 +105 °C Ambient
–40 +125 °C Case

Rev. A | Page 5 of 36

AD1940/AD1941

ABSOLUTE MAXIMUM RATINGS

Table 8.

Parameter Min Max Unit

VDD to DGND –0.3 +3.0 V
PLL_ VDD to PGND –0.3 +3.0 V
OD VDD to DGND –0.3 +6.0 V
INVDD to DGND ODVDD +6.0 V
Digital Inputs DGND – 0.3 INVDD + 0.3 V
Maximum Junction

Temperature

Storage Temperature

Range

Soldering (10 sec) 300 °C

Table 9. Package Characteristics

Parameter Min Typ Max Unit

θJA Thermal Resistance (Junction-

to-Ambient)

θJC Thermal Resistance (Junction-

to-Case)

135 °C

–65 +150 °C

72 °C/W

19.5 °C/W

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. A | Page 6 of 36

AD1940/AD1941

DIGITAL TIMING DIAGRAMS

LCH

t

LIH

t

SIS

LSB

t

SIH

04607-0-013

t

TS

BCLK_IN

LRCLK_IN

SDATA_INX

LEFT-JUSTIFIED

MODE

SDATA_INX

I2S-JUSTIFIED

MODE

SDATA_INX

RIGHT-JUSTIFIED

MODE

BCLK_OUTX

LRCLK_OUTX

t

BIH

t

BIL

t

LIS

t

SIS

MSB

t

SIH

8-BIT CLOCKS
(24-BIT DATA)

12-BIT CLOCKS
(20-BIT DATA)

14-BIT CLOCKS
(18-BIT DATA)

16-BIT CLOCKS
(16-BIT DATA)

t

SIS

MSB-1

MSB

t

SIH

t

SIS

MSB

t

SIH

Figure 2. Serial Input Port Timing

t

BIH

t

BIL

t

LOS

t

SDATA_OUTX

LEFT-JUSTIFIED

MODE

SDATA_OUTX

2

S-JUSTIFIED

I

MODE

SDATA_OUTX

RIGHT-JUSTIFIED

MODE

t

SDDS

t

SDDM

MSB

8-BIT CLOCKS
(24-BIT DATA)

12-BIT CLOCKS
(20-BIT DATA)

14-BIT CLOCKS
(18-BIT DATA)

16-BIT CLOCKS
(16-BIT DATA)

t

SDDS

t

SDDM

MSB-1

MSB

Figure 3. Serial Output Port Timing

Rev. A | Page 7 of 36

t

SDDS

t

SDDM

MSB

LSB

04607-0-014

AD1940/AD1941

K

t

CLS

CLATCH

CCLK

CDATA

COUT

SDA

t

CDS

t

CCPH

t

TSCH

t

CCPL

t

CDH

Figure 4. AD1940 SPI Port Timing

t

DS

t

SR

t

SCLH

t

TSCH

t

CLH

t

COD

t

CLPH

04607-0-015

MCLK

RESETB

SCL

t

t

SCLL

ST

Figure 5. AD1941 I

t

SCS

2

C Port Timing

t

SSH

04607-026

t

MP

t

RLPW

04607-0-016

Figure 6. Master Clock and Reset Timing

Rev. A | Page 8 of 36

AD1940/AD1941

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

VDD

MCLK

RESERVED
PLL_CTRL0
PLL_CTRL1
PLL_CTRL2

PLL_GND
PLL_VDD

NC

LRCLK_IN

BCLK_IN

GND

NC = NO CONNECT

UT7

RIVE

ENSE

GND

VREFVD

PIN 1
INDICATOR

D
D
V

SDATA_IN0

VS

AD1940

TOP VIEW

(Not to Scale)

2

1

N

N

I

I

_

_

A

A

T

T

A

A

D

D

S

S

48 47 46 45 44 39 38 3743 42 41 40

1
2
3
4
5
6
7
8

9
10
11
12

13 14 15 16 17 18 19 20 21 22 23 24

VSUPPLY

3
N

I
_
A
T

A
D
S

INVDD

SDATA_O

T
U
O
C

ADR_SEL

ATA_OUT6
SD

K
L
C
C

_OUT5

ODVDD

SDATA

A

H

T

C

A

T

D

A
L

C

C

SDATA_OUT4VDD

B
T
E
S
E
R

36
35
34
33
32
31
30
29
28
27
26
25

D
N
G

GND
BCLK_OUT1
LRCLK_OUT1
ODVDD
SDATA_OUT3
SDATA_OUT2
SDATA_OUT1
SDATA_OUT0
ODVDD
BCLK_OUT0
LRCLK_OUT0
VDD

04607-0-002

VDD

MCLK

RESERVED
PLL_CTRL0
PLL_CTRL1
PLL_CTRL2

PLL_GND

PLL_VDD

I2C_FILT_EN

LRCLK_IN

BCLK_IN

GND

NC = NO CONNECT

RIVE

GND

VREFVD

48 47 46 45 44 39 38 3743 42 41 40

1

PIN 1
INDICATOR

2
3
4
5
6
7
8

9
10
11
12

13 14 15 16 17 18 19 20 21 22 23 24

DD
V

DATA_IN1

SDATA_IN0

S

UT7

ENSE
VS

VSUPPLY

INVDD

SDATA_O

AD1941

TOP VIEW

(Not to Scale)

_IN3

SDA

ADR_SEL

SDATA_IN2SDATA

ATA_OUT6
SD

CL
S

ODVDD

NC

Figure 7. 48-Lead LQFP Pin Configuration, AD1940 Figure 8. 48-Lead LQFP Pin Configuration, AD1941

Table 10. Pin Function Descriptions

Pin No.

AD1940 AD1941 I/O Mnemonic Description

1, 25, 37 1, 25, 37 VDD Core Power.
2 2 IN MCLK Master Clock Input.
3 3 RESERVED This pin should be connected to ground.
4 4 IN PLL_CTRL0 PLL Control 0.
5 5 IN PLL_CTRL1 PLL Control 1.
6 6 IN PLL_CTRL2 PLL Control 2.
7 7 PLL_GND PLL Ground.
8 8 PLL_VDD PLL Power.
9 21, 22 NC No Connect.
9 IN I2C_FILT_ENB I2C Filter Enable, Active Low.
10 10 IN LRCLK_IN Left/Right Clock for Serial or TDM Data Inputs.
11 11 IN BCLK_IN Bit Clock for Serial or TDM Data Inputs.
12, 24, 36,

48

12, 24, 36,
48

GND Digital Ground.

13 13 VDD Core Power.
14 14 IN SDATA_IN0 Serial Data Input 0.
15 12 IN SDATA_IN1 Serial Data Input 1.
16 16 IN SDATA_IN2/TDM_IN1 Serial Data Input 2/TDM Input 1.
17 17 IN SDATA_IN3/TDM_IN0 Serial Data Input 3/TDM Input 0.
18 18 IN ADR_SEL Control Port Address Select.
19 OUT COUT SPI Data Output.
20 IN CCLK Clock for SPI.
21 IN CLATCH SPI Data Latch.

_OUT5

SDATA

NC

SDATA_OUT4VDD

ETB
RES

36
35
34
33
32
31
30
29
28
27
26
25

GND

GND
BCLK_OUT1
LRCLK_OUT1
ODVDD
SDATA_OUT3
SDATA_OUT2
SDATA_OUT1
SDATA_OUT0
ODVDD
BCLK_OUT0
LRCLK_OUT0
VDD

04607-0-011

Rev. A | Page 9 of 36

AD1940/AD1941

Pin No.

AD1940 AD1941 I/O Mnemonic Description

22 IN CDATA Data Input for SPI.
19 IN/OUT SDA I2C Serial Data I/O.
20 IN SCL I2C Clock.
23 23 IN RESETB Reset the AD1940/AD1941.
26 26 IN/OUT LRCLK_OUT0 Left/Right Clock Output 0.
27 27 IN/OUT BCLK_OUT0 Bit Clock Output 0.
28, 33, 40 28, 33, 40 ODVDD Power Connection for Output Pins.
29 29 OUT SDATA_OUT0/TDM_O0 Serial Data Output 0/TDM (16- or 8-Channel) Output 0.
30 30 OUT SDATA_OUT1 Serial Data Output 1.
31 31 OUT SDATA_OUT2 Serial Data Output 2.
32 32 OUT SDATA_OUT3 Serial Data Output 3.
34 34 IN/OUT LRCLK_OUT1 Left/Right Clock Output 1.
35 35 IN/OUT BCLK_OUT1 Bit Clock Output 1.
38 38 OUT SDATA_OUT4/TDM_O1 Serial Data Output 4./TDM (8-Channel) Output 1.
39 39 OUT SDATA_OUT5 Serial Data Output 5.
41 41 OUT SDATA_OUT6 Serial Data Output 6.
42 42 OUT SDATA_OUT7/DCSOUT Serial Data Output 7/Data Capture Output.
43 43 INVDD Input Voltage Reference.
44 44 IN VSUPPLY Voltage Level Input to Regulator. Usually 3.3 V or 5 V.
45 45 IN VSENSE Digital Power Level. Should be tied to VDD.
46 46 OUT VDRIVE Drive for External PNP Transistor.
47 47 OUT VREF Reference Level for Voltage Regulator.

Rev. A | Page 10 of 36

AD1940/AD1941

A

FEATURES

The core of the AD1940/AD1941 is a 28-bit DSP (56-bit, double
precision) optimized for audio processing. The parts’ program
RAM can be loaded with a custom program after power-up.
Signal processing parameters are stored in a 1024 location
parameter RAM, which is initialized on power-up by an internal
boot ROM. New values are written to the parameter RAM using
the control port. The values stored in the parameter RAM
control individual signal processing blocks, such as IIR equali­zation filters, dynamics processors, audio delays, and mixer
levels. A safeload feature allows parameters to be transparently
updated without causing clicks on the output signals.

The target/slew RAM contains 64 locations and can be used as
channel volume controls or for other parameter updates. These
RAM locations take a target value for a given parameter and
ramp the current parameter value to the new value using a
specified time constant and one of a selection of linear or
logarithmic curves.

The AD1940/AD1941 contain eight independent data capture
circuits that can be programmed to tap the signal flow of the
processor at any point in the DSP algorithm flow. Six of these
captured signals can be accessed by reading from the data
capture registers through the control port. The remaining two
data capture registers can be used to send any internal captured
signal to a stereo digital output signal on Pin SDATA_OUT7 for
driving external DACs or digital analyzers.

The AD1940/AD1941 have a sophisticated control port that
supports complete read/write capability of all memory
locations. Five control registers (Core, RAM configuration,
Serial Output 0 to 7, Serial Output 8 to 15, and serial input) are
provided to offer complete control of the chip’s configuration
and serial modes. Handshaking is included for ease of memory
uploads/downloads. The AD1940 is SPI-controlled and the

2

AD1941 is controlled by an I

C bus.

The AD1940/AD1941 have very flexible serial data input/output
ports that allow glueless interconnection to a variety of ADCs,
DACs, general-pur pose DSPs, S/PDIF receivers and trans­mitters, and sample rate converters. The AD1940/AD1941 can

2

be configured in I

S, left-justified, right-justified, or TDM serial
port-compatible modes. It can support 16, 20, and 24 bits in all
modes. The AD1940/AD1941 accepts serial audio data in MSB
first and twos complement format.

A master clock phase-locked loop (PLL) allows the AD1940/
AD1941 to be clocked from a variety of different clock speeds.
The PLL can accept inputs of 64 × f
f

to generate the core’s internal master clock.

S

, 256 × fS, 384 × fS, or 512 ×

S

The AD1940/AD1941 operate from a single 2.5 V power supply.
An on-board voltage regulator can be used to operate the chip
with 3.3 V or 5 V supplies. They are fabricated on a single
monolithic integrated circuit and are housed in 48-lead
LQFP packages for operation over the –40°C to +105°C
temperature range.

2
2

4

SERIAL DATA/
TDM OUTPUT
GROUP

REGULATOR
GROUP

04607-0-003

SERIAL

DATA/TDM

INPUT

GROUP

PLL MODE

SELECT

MASTER

CLOCK

INPUT

CONTROL PORT

I/O GROUP

DDRESS SELECT

RESETB

DATA MEMORY

6k × 28

TARGET/SLEW

64 × 28

2

2

4

CONTROL

RAM

MCLK

PLL

SERIAL

PORT

CONTROL

REGISITER
TRAP REG.

SAFELOAD

REGISTER

BOOT ROM

PROGRAM

RAM

1536 × 40

28 × 28

DSP CORE

DATA FORMAT:

5.23 (SINGLE PRECISION)

10.46 (DOUBLE PRECISION)

BOOT ROM

PARAMETER

RAM

1024 × 28

COEFFICIENT

512 × 28

VOLTAGE REGULATORMEMORY CONTROLLERS

ROM

Figure 9. Block Diagram

Rev. A | Page 11 of 36