ANALOG DEVICES AD1939 Service Manual

4 ADC/8 DAC with PLL,

A

FEATURES

PLL generated or direct master clock Low EMI design 112 dB DAC/107 dB ADC dynamic range and SNR

−94 dB THD + N Single 3.3 V supply Tolerance for 5 V logic inputs Supports 24-bits and 8 kHz to 192 kHz sample rates Differential ADC input Differential DAC output Log volume control with autoramp function SPI controllable for flexibility Software-controllable clickless mute Software power-down Right-justified, left-justified, I Master and slave modes up to 16-channel input/output 64-lead LQFP package Qualified for automotive applications

APPLICATIONS

Automotive audio systems Home Theater Systems Set-top boxes Digital audio effects processors

2

S, and TDM modes

192 kHz, 24-Bit Codec

AD1939

GENERAL DESCRIPTION

The AD1939 is a high performance, single-chip codec that provides four analog-to-digital converters (ADCs) with differential input, and eight digital-to-analog converters (DACs) with differential output using the Analog Devices, Inc. patented multibit sigma-delta (Σ-Δ) architecture. An SPI port is included, allowing a microcontroller to adjust volume and many other parameters. The AD1939 operates from 3.3 V digital and analog supplies. The AD1939 is available in a 64-lead (differential output) LQFP package.

The AD1939 is designed for low EMI. This consideration is apparent in both the system and circuit design architectures. By using the on-board PLL to derive the master clock from the LR clock or from an external crystal, the AD1939 eliminates the need for a separate high frequency master clock and can also be used with a suppressed bit clock. The DACs and ADCs are designed using the latest Analog Devices continuous time architectures to further minimize EMI. By using 3.3 V supplies, power consumption is minimized, further reducing emissions.

FUNCTIONAL BLOCK DIAGRAM

DIGITAL AUDIO INPUT/OUTPUT

AD1939

ADC

NALOG

AUDIO

INPUTS

ADC

PRECISION

VOLTAGE

REFERENCE

DIGITAL

FILTER

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

SERIAL DATA PORT

SDATA

OUT

TIMING MANAGEMENT

AND CONTROL

(CLOCK AND PLL )

CONTROL P ORT

CONTROL DAT A

INPUT/OUTPUT

DAC

SDATA

IN

CLOCKS

SPI

Figure 1.

DIGITAL

FILTER

AND

VOLUME

CONTROL

DAC DAC DAC DAC DAC DAC DAC

ANALOG AUDIO OUTPUTS

06071-001

AD1939

REVISION HISTORY

7/11—Rev. C to Rev. D

Changes to Pin 15, Pin 18, Pin 19, and Pin 20 Descriptions ...... 9

Changes to Pin 26 and Pin 27 Descriptions................................ 10

9/10—Rev. B to Rev. C

Added Qualified for Automotive Applications to the Features

Section................................................................................................ 1

Changed Case Temperature from 130°C to 125°C ...................... 4

Changed T Changed T

Changes to Ordering Guide.......................................................... 31

Added Automotive Products Section .......................................... 31

3/10—Rev. A to Rev. B

Changes to Ordering Guide.......................................................... 31

6/07—Rev. 0 to Rev. A

from −40°C to +130°C to −40°C to +105°C ........... 5

A

from −40°C to +130°C to −40°C to +105°C ........... 7

A

Outline Dimensions....................................................................... 31

Ordering Guide .......................................................................... 31

Automotive Products................................................................. 31

Deleted I

Change to Figure 1 ............................................................................1

Changes to Figure 2...........................................................................9

Changes to Table 10 ..........................................................................9

Changes to Table 11 ....................................................................... 14

Changes to Table 12 ....................................................................... 16

Changes to Figure 24 and Figure 25............................................. 22

Changes to Table 13 ....................................................................... 23

Change to Figure 26....................................................................... 23

Changes to Table 15 and Table 16 ................................................ 24

Changes to Figure 27 and Figure 28............................................. 29

Change to Figure 30....................................................................... 30

Updated Outline Dimensions....................................................... 31

Changes to Ordering Guide.......................................................... 31

7/06—Revision 0: Initial Version

2

C References.......................................................Universal

Rev. D | Page 2 of 32

AD1939

SPECIFICATIONS

TEST CONDITIONS

Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications.

Supply voltages (AVDD, DVDD) 3.3 V

Temperature range

Master clock 12.288 MHz (48 kHz fS, 256 × fS mode)

Input sample rate 48 kHz

Measurement bandwidth 20 Hz to 20 kHz

Word width 24 bits

Load capacitance (digital output) 20 pF

Load current (digital output) ±1 mA or 1.5 kΩ to ½ DVDD supply

Input voltage high 2.0 V

Input voltage low 0.8 V

1

Functionally guaranteed at −40°C to +125°C case temperature.

ANALOG PERFORMANCE SPECIFICATIONS

Specifications guaranteed at an ambient temperature of 25°C.

Table 1.

Parameter Conditions/Comments Min Typ Max Unit

ANALOG-TO-DIGITAL CONVERTERS

ADC Resolution All ADCs 24 Bits Dynamic Range 20 Hz to 20 kHz, −60 dB input

No Filter (RMS) 96 102 dB

With A-Weighted Filter (RMS) 98 105 dB Total Harmonic Distortion + Noise −1 dBFS −96 −87 dB Full-Scale Input Voltage (Differential) 1.9 V rms Gain Error −10 +10 % Interchannel Gain Mismatch −0.25 +0.25 dB Offset Error −10 0 +10 mV Gain Drift 100 ppm/°C Interchannel Isolation −110 dB CMRR 100 mV rms, 1 kHz 55 dB 100 mV rms, 20 kHz 55 dB Input Resistance 14 kΩ Input Capacitance 10 pF Input Common-Mode Bias Voltage 1.5 V

DIGITAL-TO-ANALOG CONVERTERS

Dynamic Range 20 Hz to 20 kHz, −60 dB input

No Filter (RMS) 102 107 dB

With A-Weighted Filter (RMS) 105 110 dB

With A-Weighted Filter (Average) 112 dB Total Harmonic Distortion + Noise 0 dBFS

Two channels running −94 dB

Eight channels running −86 −76 dB Full-Scale Output Voltage 1.76 (4.96) V rms (V p-p) Gain Error −10 +10 % Interchannel Gain Mismatch −0.2 +0.2 dB Offset Error −25 −6 +25 mV Gain Drift −30 +30 ppm/°C Interchannel Isolation 100 dB

1

As specified in Tab le 1 and Ta ble 2

Rev. D | Page 3 of 32

AD1939

Parameter Conditions/Comments Min Typ Max Unit

Interchannel Phase Deviation 0 Degrees Volume Control Step 0.375 dB Volume Control Range 95 dB De-emphasis Gain Error ±0.6 dB Output Resistance at Each Pin 100 Ω

REFERENCE

Internal Reference Voltage FILTR pin 1.50 V External Reference Voltage FILTR pin 1.32 1.50 1.68 V Common-Mode Reference Output CM pin 1.50 V

REGULATOR

Input Supply Voltage VSUPPLY pin 4.5 5 5.5 V Regulated Output Voltage VSENSE pin 3.19 3.37 3.55 V

Specifications measured at a case temperature of 125°C.

Table 2.

Parameter Conditions/Comments Min Typ Max Unit

ANALOG-TO-DIGITAL CONVERTERS

ADC Resolution All ADCs 24 Bits Dynamic Range 20 Hz to 20 kHz, −60 dB input

No Filter (RMS) 93 102 dB

With A-Weighted Filter (RMS) 96 104 dB Total Harmonic Distortion + Noise −1 dBFS −96 −87 dB Full-Scale Input Voltage (Differential) 1.9 V rms Gain Error −10 +10 % Interchannel Gain Mismatch −0.25 +0.25 dB Offset Error −10 0 +10 mV

DIGITAL-TO-ANALOG CONVERTERS

Dynamic Range 20 Hz to 20 kHz, −60 dB input

No Filter (RMS) 101 107 dB

With A-Weighted Filter (RMS) 104 110 dB

With A-Weighted Filter (Average) 112 dB Total Harmonic Distortion + Noise 0 dBFS

Two channels running −94 dB

Eight channels running −86 −70 dB Full-Scale Output Voltage 1.76 (4.96) V rms (V p-p) Gain Error −10 +10 % Interchannel Gain Mismatch −0.2 +0.2 dB Offset Error −25 −6 +25 mV Gain Drift −30 +30 ppm/°C

REFERENCE

Internal Reference Voltage FILTR pin 1.50 V External Reference Voltage FILTR pin 1.32 1.50 1.68 V Common-Mode Reference Output CM pin 1.50 V

REGULATOR

Input Supply Voltage VSUPPLY pin 4.5 5 5.5 V Regulated Output Voltage VSENSE pin 3.2 3.43 3.65 V

CRYSTAL OSCILLATOR SPECIFICATIONS

Table 3.

Parameter Min Typ Max Unit

Transconductance 3.5 mmhos

Rev. D | Page 4 of 32

AD1939

DIGITAL INPUT/OUTPUT SPECIFICATIONS

−40°C < TA < +105°C, DVDD = 3.3 V ± 10%.

Table 4.

Parameter Conditions/Comments Min Typ Max Unit

High Level Input Voltage (VIH) 2.0 V MCLKI/XI pin 2.2 V Low Level Input Voltage (VIL) 0.8 V Input Leakage IIH @ VIH = 2.4 V 10 μA I High Level Output Voltage (VOH) IOH = 1 mA DVDD − 0.60 V Low Level Output Voltage (VOL) IOL = 1 mA 0.4 V Input Capacitance 5 pF

POWER SUPPLY SPECIFICATIONS

Table 5.

Parameter Conditions/Comments Min Typ Max Unit

SUPPLIES

Voltage DVDD 3.0 3.3 3.6 V AVDD 3.0 3.3 3.6 V VSUPPLY 4.5 5.0 5.5 V Digital Current Master clock = 256 f

Normal Operation fS = 48 kHz 56 mA

f f

Power-Down fS = 48 kHz to 192 kHz 2.0 mA

Analog Current

Normal Operation 74 mA Power-Down 23 mA

DISSIPATION

Operation Master clock = 256 fS, 48 kHz

All Supplies 429 mW Digital Supply 185 mW Analog Supply 244 mW

Power-Down, All Supplies 83 mW

POWER SUPPLY REJECTION RATIO

Signal at Analog Supply Pins 1 kHz, 200 mV p-p 50 dB 20 kHz, 200 mV p-p 50 dB

@ VIL = 0.8 V 10 μA

IL

S

= 96 kHz 65 mA

S

= 192 kHz 95 mA

S

Rev. D | Page 5 of 32

AD1939

DIGITAL FILTERS

Table 6.

Parameter Mode Factor Min Typ Max Unit

ADC DECIMATION FILTER

Pass Band 0.4375 f Pass-Band Ripple ±0.015 dB Transition Band 0.5 f Stop Band 0.5625 f Stop-Band Attenuation 79 dB Group Delay 22.9844/f

DAC INTERPOLATION FILTER

Pass Band 48 kHz mode, typical @ 48 kHz 0.4535 f 96 kHz mode, typical @ 96 kHz 0.3646 f 192 kHz mode, typical @ 192 kHz 0.3646 f Pass-Band Ripple 48 kHz mode, typical @ 48 kHz ±0.01 dB 96 kHz mode, typical @ 96 kHz ±0.05 dB 192 kHz mode, typical @ 192 kHz ±0.1 dB Transition Band 48 kHz mode, typical @ 48 kHz 0.5 f 96 kHz mode, typical @ 96 kHz 0.5 f 192 kHz mode, typical @ 192 kHz 0.5 f Stop Band 48 kHz mode, typical @ 48 kHz 0.5465 f 96 kHz mode, typical @ 96 kHz 0.6354 f 192 kHz mode, typical @ 192 kHz 0.6354 f Stop-Band Attenuation 48 kHz mode, typical @ 48 kHz 70 dB 96 kHz mode, typical @ 96 kHz 70 dB 192 kHz mode, typical @ 192 kHz 70 dB Group Delay 48 kHz mode, typical @ 48 kHz 25/f

96 kHz mode, typical @ 96 kHz 11/f 192 kHz mode, typical @ 192 kHz 8/f

All modes, typical @ 48 kHz

S

21 kHz

24 kHz 27 kHz

479 μs

22 kHz 35 kHz 70 kHz

24 kHz 48 kHz 96 kHz 26 kHz 61 kHz 122 kHz

521 μs 115 μs 42 μs

TIMING SPECIFICATIONS

−40°C < TA < +105°C, DVDD = 3.3 V ± 10%.

Table 7.

Parameter Condition Comments Min Max Unit

INPUT MASTER CLOCK (MCLK) AND RESET

t

MH

t

MH

f

MCLK

f

MCLK

t

PDR

t

PDRR

PLL

Lock Time MCLK and LRCLK input 10 ms 256 fS VCO Clock, Output Duty Cycle,

MCLKO/XO Pin

MCLK duty cycle

DAC/ADC clock source = PLL clock @ 256 f

, 512 fS, and 768 f

f

S

DAC/ADC clock source = direct MCLK @ 512 f

, 384

40 60 %

S

(bypass on-chip PLL) MCLK frequency PLL mode, 256 fS reference 6.9 13.8 MHz Direct 512 fS mode 27.6 MHz Low 15 ns Recovery Reset to active output 4096 t

MCLK

40 60 %

Rev. D | Page 6 of 32

AD1939

Parameter Condition Comments Min Max Unit

SPI PORT See Figure 11

t

CCH

t

CCL

f

CCLK

t

CDS

t

CDH

t

CLS

t

CLH

t

CLHIGH

t

COE

t

COD

t

COH

t

COTS

DAC SERIAL PORT See Figure 24

t

DBH

t

DBL

t

DLS

t

DLH

t

DLS

t

DDS

t

DDH

ADC SERIAL PORT See Figure 25

t

ABH

t

ABL

t

ALS

t

ALH

t

ALS

t

ABDD

AUXILIARY INTERFACE

t

AXDS

t

AXDH

t

DXDD

t

XBH

t

XBL

t

DLS

t

DLH

CCLK high 35 ns CCLK low 35 ns CCLK frequency f

CCLK

= 1/t

CCP

; only t

shown in Figure 11 10 MHz

CCP

CIN setup To CCLK rising 10 ns CIN hold From CCLK rising 10 ns CLATCH CLATCH

CLATCH

setup hold high

To CCLK rising 10 ns From CCLK falling 10 ns Not shown in Figure 11 10 ns

COUT enable From CCLK falling 30 ns COUT delay From CCLK falling 30 ns COUT hold From CCLK falling, not shown in Figure 11 30 ns COUT tristate From CCLK falling 30 ns

DBCLK high Slave mode 10 ns DBCLK low Slave mode 10 ns DLRCLK setup To DBCLK rising, slave mode 10 ns DLRCLK hold From DBCLK rising, slave mode 5 ns DLRCLK skew From DBCLK falling, master mode −8 +8 ns DS DATA setup To DBCLK risin g 10 ns DSDATA hold From DBCLK rising 5 ns

ABCLK high Slave mode 10 ns ABCLK low Slave mode 10 ns ALRCLK setup To ABCLK rising, slave mode 10 ns ALRCLK hold From ABCLK rising, slave mode 5 ns ALRCLK skew From ABCLK falling, master mode −8 +8 ns ASDATA delay From ABCLK falling 18 ns

AAUXDATA s etu p To AUXBCLK risi n g 10 ns AAUXDATA hold From AUXBCLK rising 5 ns DAUXDATA delay From AUXBCLK falling 18 ns AUXBCLK high 10 ns AUXBCLK low 10 ns AUXLRCLK setup To AUXBCLK rising 10 ns AUXLRCLK hold From AUXBCLK rising 5 ns

Rev. D | Page 7 of 32

AD1939

ABSOLUTE MAXIMUM RATINGS

Table 8.

Parameter Rating

Analog (AVDD) −0.3 V to +3.6 V Digital (DVDD) −0.3 V to +3.6 V VSUPPLY −0.3 V to +6.0 V Input Current (Except Supply Pins) ±20 mA Analog Input Voltage (Signal Pins) –0.3 V to AVDD + 0.3 V Digital Input Voltage (Signal Pins) −0.3 V to DVDD + 0.3 V Operating Temperature Range (Case) −40°C to +125°C Storage Temperature Range −65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

θJA represents thermal resistance, junction-to-ambient; θ All characteristics are for a 4-layer board.

Table 9. Thermal Resistance

Package Type θ

64-Lead LQFP 47 11.1 °C/W

ESD CAUTION

represents the thermal resistance, junction-to-case.

JC

JA

θ

JC

Unit

Rev. D | Page 8 of 32

AD1939

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

AGND

AVDD

OL3P

OL3N

OR3P

OR3N

OL4P

OL4N

OR4P

OR4N

PD/RST

DGND

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

MCLKI/XI

MCLKO/XO

DSDATA4

NC = NO CONNECT

NC64NC63AVDD62LF61ADC2RN60ADC2RP59ADC2LN58ADC2LP57ADC1RN56ADC1RP55ADC1LN54ADC1LP53CM52AVDD51NC50NC

AD1939

TOP VIEW

(Not to Scale)

DIFFERENTIAL

OUTPUT

17

DVDD

20

DSDATA318DSDATA219DSDATA1

21

22

23

24

25

27

28

29

DBCLK

DLRCLK

VDRIVE

VSENSE

VSUPPLY

ASDATA226ASDATA1

ABCLK

ALRCLK

49

30

32

CIN

COUT31DVDD

Figure 2. 64-Lead LQFP, Differential Output, Pin Configuration

Table 10. Pin Function Descriptions

Pin No. In/Out Mnemonic Description

1 I AGND Analog Ground. 2 I MCLKI/XI Master Clock Input/Crystal Oscillator Input. 3 O MCLKO/XO 4 I AGND 5 I AVDD 6 O OL3P 7 O OL3N 8 O OR3P 9 O OR3N 10 O OL4P 11 O OL4N 12 O OR4P 13 O OR4N 14 I

PD

/RST

15 I/O DSDATA4

Master Clock Output/Crystal Oscillator Output. Analog Ground. Analog Power Supply. Connect to analog 3.3 V supply. DAC 3 Left Positive Output. DAC 3 Left Negative Output. DAC 3 Right Positive Output. DAC 3 Right Negative Output. DAC 4 Left Positive Output. DAC 4 Left Negative Output. DAC 4 Right Positive Output. DAC 4 Right Negative Output Power-Down Reset (Active Low).

DAC Serial Data Input 4. Data input to DAC4 data in/TDM DAC2 data out (dual-line

mode)/AUX DAC2 data out (to external DAC2). 16 I DGND 17 I DVDD 18 I/O DSDATA3

Digital Ground.

Digital Power Supply. Connect to digital 3.3 V supply.

DAC Serial Data Input 3. Data input to DAC3 data in/TDM DAC2 data in (dual-line

mode)/AUX ADC2 data in (from external ADC2). 19 I/O DSDATA2

DAC Serial Data Input 2. Data input to DAC2 data in/TDM DAC data out/AUX ADC1

data in (from external ADC1). 20 I DSDATA1 21 I/O DBCLK

DAC Serial Data Input 1. Data input to DAC1 data in/TDM DAC data in/TDM data in.

Bit Clock for DACs. 22 I/O DLRCLK LR Clock for DACs.

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

AGND

FILTR

AGND

AVDD

AGND

OR2N

OR2P

OL2N

OL2P

OR1N

OR1P

OL1N

OL1P

CLATCH

CCLK

DGND

06071-021

Rev. D | Page 9 of 32

AD1939

Pin No. In/Out Mnemonic Description

23 I VSUPPLY 5 V Input to Regulator, Emitter of Pass Transistor. 24 I VSENSE 3.3 V Output of Regulator, Collector of Pass Transistor. 25 O VDRIVE Drive for Base of Pass Transistor. 26 I/O ASDATA2

27 O ASDATA1 ADC Serial Data Output 1. Data Output from ADC1/TDM ADC data out/TDM data out. 28 I/O ABCLK Bit Clock for ADCs. 29 I/O ALRCLK LR Clock for ADCs. 30 I CIN Control Data Input (SPI). 31 I/O COUT Control Data Output (SPI). 32 I DVDD Digital Power Supply. Connect to digital 3.3 V supply. 33 I DGND Digital Ground. 34 I CCLK Control Clock Input (SPI). 35 I

36 O OL1P DAC 1 Left Positive Output. 37 O OL1N DAC 1 Left Negative Output. 38 O OR1P DAC 1 Right Positive Output. 39 O OR1N DAC 1 Right Negative Output. 40 O OL2P DAC 2 Left Positive Output. 41 O OL2N DAC 2 Left Negative Output. 42 O OR2P DAC 2 Right Positive Output. 43 O OR2N DAC 2 Right Negative Output. 44 I AGND Analog Ground. 45 I AVDD Analog Power Supply. Connect to analog 3.3 V supply. 46 I AGND Analog Ground. 47 O FILTR Voltage Reference Filter Capacitor Connection. Bypass with 10 μF||100 nF to AGND. 48 I AGND Analog Ground. 49 NC No Connect. 50 NC No Connect. 51 I AVDD Analog Power Supply. Connect to analog 3.3 V supply. 52 O CM

53 I ADC1LP ADC1 Left Positive Input. 54 I ADC1LN ADC1 Left Negative Input. 55 I ADC1RP ADC1 Right Positive Input. 56 I ADC1RN ADC1 Right Negative Input. 57 I ADC2LP ADC2 Left Positive Input. 58 I ADC2LN ADC2 Left Negative Input. 59 I ADC2RP ADC2 Right Positive Input. 60 I ADC2RN ADC2 Right Negative Input. 61 O LF PLL Loop Filter, Return to AVDD. 62 I AVDD Analog Power Supply. Connect to analog 3.3 V supply. 63 NC No Connect. 64 NC No Connect.

CLATCH

ADC Serial Data Output 2. Data Output from ADC2/TDM ADC data in/AUX DAC1 data out (to external DAC1).

Latch Input for Control Data (SPI).

Common-Mode Reference Filter Capacitor Connection. Bypass with 47 μF||100 nF to AGND.

Rev. D | Page 10 of 32

ANALOG DEVICES AD1939 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TEST CONDITIONS

ANALOG PERFORMANCE SPECIFICATIONS

CRYSTAL OSCILLATOR SPECIFICATIONS

DIGITAL INPUT/OUTPUT SPECIFICATIONS

POWER SUPPLY SPECIFICATIONS

DIGITAL FILTERS

TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS