ANALOG DEVICES AD1938 Service Manual

4 ADC/8 DAC with PLL,

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FEATURES

PLL generated or direct master clock Low EMI design 108 dB DAC/107 dB ADC dynamic range and SNR

−94 dB THD + N

3.3 V single supply Tolerance for 5 V logic inputs Supports 24 bits and 8 kHz to 192 kHz sample rates Differential ADC input Single-ended DAC output Log volume control with autoramp function SPI controllable for flexibility Software-controllable clickless mute Software power-down Right-justified, left-justified, I Master and slave modes up to 16-channel input/output 48-lead LQFP package

APPLICATIONS

Automotive audio systems Home Theater Systems Set-top boxes Digital audio effects processors

2

S-justified, and TDM modes

192 kHz, 24-Bit Codec

AD1938

GENERAL DESCRIPTION

The AD1938 is a high performance, single-chip codec that provides four analog-to-digital converters (ADCs) with input and eight digital-to-analog converters (DACs) with single-ended output using the Analog Devices, Inc., patented multibit sigma-delta (Σ-Δ) architecture. An SPI port is included, allowing a microcontroller to adjust volume and many other parameters.

The AD1938 operates from 3.3 V digital and analog supplies. The AD1938 is available in a 48-lead (single-ended output) LQFP package. Other members of this family include a differential DAC output and I

The AD1938 is designed for low EMI. This consideration is apparent in both the system and circuit design architectures. By using the on-board PLL to derive the master clock from the LR clock or from an external crystal, the AD1938 eliminates the need for a separate high frequency master clock and can also be used with a suppressed bit clock. The DACs and ADCs are designed using the latest Analog Devices continuous time architectures to further minimize EMI. By using 3.3 V supplies, power consumption is minimized, further reducing emissions.

2

C® control port version.

FUNCTIONAL BLOCK DIAGRAM

DIGITAL AUDIO INPUT/OUTPUT

AD1938

SERIAL DATA P ORT

ADC

ANALOG

AUDIO

INPUTS

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

ADC

PRECISION

VOLTAGE

REFERENCE

DIGITAL

FILTER

SDATA

OUT

TIMING MANAGEMENT

AND CONTROL

(CLOCK AND PLL )

SPI CONTROL PORT

CONTROL DAT A

INPUT/OUTPUT

DAC

SDATA

IN

CLOCKS

Figure 1.

DIGITAL

FILTER

AND

VOLUME

CONTROL

DAC

ANALOG AUDIO OUTPUTS

05582-001

AD1938

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REVISION HISTORY

7/08—Rev. 0 to Rev. A

Changes to Table 7 ............................................................................ 7

Changes to Figure 2 .......................................................................... 9

Changes to Table 10 .......................................................................... 9

Changes to Clock Signals Section ................................................ 13

Changes to Reset and Power-Down Section ............................... 14

Change to Serial Control Port Section ......................................... 14

Changes to Table 11 ........................................................................ 14

Changes to Figure 24 and Figure 25 ............................................. 22

Changes to Figure 26 ...................................................................... 23

Changes to Definitions Section .................................................... 24

Changes to Table 16 ........................................................................ 24

Change to Additional Modes Section .......................................... 29

Change to Figure 30 ....................................................................... 30

5/06—Revision 0: Initial Version

Rev. A | Page 2 of 32

AD1938

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SPECIFICATIONS

TEST CONDITIONS

Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications.

Supply voltages (AVDD, DVDD) 3.3 V

Temperature range

Master clock 12.288 MHz (48 kHz fS, 256 × fS mode)

Input sample rate 48 kHz

Measurement bandwidth 20 Hz to 20 kHz

Word width 24 bits

Load capacitance (digital output) 20 pF

Load current (digital output) ±1 mA or 1.5 kΩ to ½ DVDD supply

Input voltage high 2.0 V

Input voltage low 0.8 V

1

Functionally guaranteed at −40°C to +125°C case temperature.

ANALOG PERFORMANCE SPECIFICATIONS

Specifications guaranteed at an ambient temperature of 25°C.

Table 1.

Parameter Conditions Min Typ Max Unit

ANALOG-TO-DIGITAL CONVERTERS

ADC Resolution All ADCs 24 Bits Dynamic Range 20 Hz to 20 kHz, −60 dB input

No Filter (RMS) 98 102 dB

With A-Weighted Filter (RMS) 100 105 dB Total Harmonic Distortion + Noise −1 dBFS −96 −87 dB Full-Scale Input Voltage (Differential) 1.9 V rms Gain Error −10 +10 % Interchannel Gain Mismatch −0.25 +0.25 dB Offset Error −10 0 +10 mV Gain Drift 100 ppm/°C Interchannel Isolation −110 dB CMRR 100 mV rms, 1 kHz 55 dB 100 mV rms, 20 kHz 55 dB Input Resistance 14 kΩ Input Capacitance 10 pF Input Common-Mode Bias Voltage 1.5 V

DIGITAL-TO-ANALOG CONVERTERS

Dynamic Range 20 Hz to 20 kHz, −60 dB input

No Filter (RMS) 98 104 dB

With A-Weighted Filter (RMS) 100 106 dB

With A-Weighted Filter (Average) 108 dB Total Harmonic Distortion + Noise 0 dBFS

Single-Ended Version Two channels running −92 dB

Single-Ended Version Eight channels running −86 −75 dB Full-Scale Output Voltage 0.88 (2.48) V rms (V p-p) Gain Error −10 +10 % Interchannel Gain Mismatch −0.2 +0.2 dB Offset Error −25 −4 +25 mV Gain Drift −30 +30 ppm/°C

1

as specified in Tabl e 1 and Table 2

Rev. A | Page 3 of 32

AD1938

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Parameter Conditions Min Typ Max Unit

Interchannel Isolation 100 dB Interchannel Phase Deviation 0 Degrees Volume Control Step 0.375 dB Volume Control Range 95 dB De-emphasis Gain Error ±0.6 dB Output Resistance at Each Pin 100 Ω

REFERENCE

Internal Reference Voltage FILTR pin 1.50 V External Reference Voltage FILTR pin 1.32 1.50 1.68 V Common-Mode Reference Output CM pin 1.50 V

Specifications measured at a case temperature of 130°C.

Table 2.

Parameter Conditions Min Typ Max Unit

ANALOG-TO-DIGITAL CONVERTERS

ADC Resolution All ADCs 24 Bits Dynamic Range 20 Hz to 20 kHz, −60 dB input

No Filter (RMS) 95 102 dB

With A-Weighted Filter (RMS) 97 105 dB Total Harmonic Distortion + Noise −1 dBFS −96 −87 dB Full-Scale Input Voltage (Differential) 1.9 V rms Gain Error −10 +10 % Interchannel Gain Mismatch −0.25 +0.25 dB Offset Error −10 0 +10 mV

DIGITAL-TO-ANALOG CONVERTERS

Dynamic Range 20 Hz to 20 kHz, −60 dB input

No Filter (RMS) 98 104 dB

With A-Weighted Filter (RMS) 100 106 dB

With A-Weighted Filter (Average) 108 dB Total Harmonic Distortion + Noise 0 dBFS

Single-Ended Version Two channels running −92 dB

Single-Ended Version Eight channels running −86 −70 dB Full-Scale Output Voltage 0.8775 (2.482) V rms (V p-p) Gain Error −10 +10 % Interchannel Gain Mismatch −0.2 +0.2 dB Offset Error −25 −4 25 mV Gain Drift −30 30 ppm/°C

REFERENCE

Internal Reference Voltage FILTR pin 1.50 V External Reference Voltage FILTR pin 1.32 1.50 1.68 V Common-Mode Reference Output CM pin 1.50 V

CRYSTAL OSCILLATOR SPECIFICATIONS

Table 3.

Parameter Min Typ Max Unit

Transconductance 3.5 mmhos

Rev. A | Page 4 of 32

AD1938

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DIGITAL INPUT/OUTPUT SPECIFICATIONS

−40°C < TA < +130°C, DVDD = 3.3 V ± 10%.

Table 4.

Parameter Conditions/Comments Min Typ Max Unit

High Level Input Voltage (VIH) 2.0 V

High Level Input Voltage (VIH) MCLKI/XI pin 2.2 V

Low Level Input Voltage (VIL) 0.8 V

Input Leakage IIH @ VIH = 2.4 V 10 μA

I

High Level Output Voltage (VOH) IOH = 1 mA DVDD − 0.60 V

Low Level Output Voltage (VOL) IOL = 1 mA 0.4 V

Input Capacitance 5 pF

POWER SUPPLY SPECIFICATIONS

Table 5.

Parameter Conditions/Comments Min Ty p Max Unit

SUPPLIES

Voltage DVDD 3.0 3.3 3.6 V AVDD 3.0 3.3 3.6 V Digital Current Master clock = 256 fS

Normal Operation fS = 48 kHz 56 mA

f f

Power-Down fS = 48 kHz to 192 kHz 2.0 mA

Analog Current

Normal Operation 74 mA Power-Down 23 mA

DISSIPATION

Operation Master clock = 256 fS, 48 kHz

All Supplies 429 mW Digital Supply 185 mW Analog Supply 244 mW

Power-Down, All Supplies 83 mW

POWER SUPPLY REJECTION RATIO

Signal at Analog Supply Pins 1 kHz, 200 mV p-p 50 dB 20 kHz, 200 mV p-p 50 dB

@ VIL = 0.8 V 10 μA

IL

= 96 kHz 65 mA

S

= 192 kHz 95 mA

S

Rev. A | Page 5 of 32

AD1938

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DIGITAL FILTERS

Table 6.

Parameter Mode Factor Min Typ Max Unit

ADC DECIMATION FILTER

Pass Band 0.4375 fS 21 kHz Pass-Band Ripple ±0.015 dB Transition Band 0.5 fS 24 kHz Stop Band 0.5625 fS 27 kHz Stop-Band Attenuation 79 dB Group Delay 22.9844/fS 479 μs

DAC INTERPOLATION FILTER

Pass Band 48 kHz mode, typical @ 48 kHz 0.4535 fS 22 kHz 96 kHz mode, typical @ 96 kHz 0.3646 fS 35 kHz 192 kHz mode, typical @ 192 kHz 0.3646 fS 70 kHz Pass-Band Ripple 48 kHz mode, typical @ 48 kHz ±0.01 dB 96 kHz mode, typical @ 96 kHz ±0.05 dB 192 kHz mode, typical @ 192 kHz ±0.1 dB Transition Band 48 kHz mode, typical @ 48 kHz 0.5 fS 24 kHz 96 kHz mode, typical @ 96 kHz 0.5 fS 48 kHz 192 kHz mode, typical @ 192 kHz 0.5 fS 96 kHz Stop Band 48 kHz mode, typical @ 48 kHz 0.5465 fS 26 kHz 96 kHz mode, typical @ 96 kHz 0.6354 fS 61 kHz 192 kHz mode, typical @ 192 kHz 0.6354 fS 122 kHz Stop-Band Attenuation 48 kHz mode, typical @ 48 kHz 70 dB 96 kHz mode, typical @ 96 kHz 70 dB 192 kHz mode, typical @ 192 kHz 70 dB Group Delay 48 kHz mode, typical @ 48 kHz 25/fS 521 μs

96 kHz mode, typical @ 96 kHz 11/fS 115 μs 192 kHz mode, typical @ 192 kHz 8/fS 42 μs

All modes, typical @ 48 kHz

Rev. A | Page 6 of 32

AD1938

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TIMING SPECIFICATIONS

−40°C < TA < +130°C, DVDD = 3.3 V ± 10%.

Table 7.

Parameter Condition Comments Min Max Unit

INPUT MASTER CLOCK (MCLK) AND RESET

tMH MCLK duty cycle

tMH

f

MCLK frequency PLL mode, 256 fS reference 6.9 13.8 MHz

MCLK

f

Direct 512 fS mode 27.6 MHz

MCLK

t

PDR

t

PDRR

PLL

Lock time MCLK and LR clock input 10 ms 256 fS VCO Clock, Output Duty Cycle,

MCLKO/XO Pin

SPI PORT See Figure 11

t

CCLK high 35 ns

CCH

t

CCLK low 35 ns

CCL

f

CCLK frequency f

CCLK

t

CIN setup To CCLK rising 10 ns

CDS

t

CIN hold From CCLK rising 10 ns

CDH

t

CLS

t

CLH

t

CLH

t

COUT enable From CCLK falling 30 ns

COE

t

COUT delay From CCLK falling 30 ns

COD

t

COUT hold From CCLK falling, not shown in Figure 11 30 ns

COH

t

COUT tristate From CCLK falling 30 ns

COTS

DAC SERIAL PORT See Figure 24

t

DBCLK high Slave mode 10 ns

DBH

t

DBCLK low Slave mode 10 ns

DBL

t

DLRCLK setup To DBCLK rising, slave mode 10 ns

DLS

t

DLRCLK hold From DBCLK rising, slave mode 5 ns

DLH

t

DLRCLK skew From DBCLK falling, master mode −8 +8 ns

DLS

t

DSDATA setup To D B CLK rising 10 ns

DDS

t

DSDATA hold From DBCLK rising 5 ns

DDH

ADC SERIAL PORT See Figure 25

t

ABCLK high Slave mode 10 ns

ABH

t

ABCLK low Slave mode 10 ns

ABL

t

ALRCLK setup To ABCLK rising, slave mode 10 ns

ALS

t

ALRCLK hold From ABCLK rising, slave mode 5 ns

ALH

t

ALRCLK skew From ABCLK falling, master mode −8 +8 ns

ALS

t

ASDATA delay From ABCLK falling 18 ns

ABDD

AUXILIARY INTERFACE

t

AAUXDATA se t u p To AUXBC L K r ising 10 ns

AXDS

t

AAUXDATA hold From AUXBCLK rising 5 ns

AXDH

t

DAUXDATA delay From AUXBCLK falling 18 ns

DXDD

t

AUXBCLK high 10 ns

XBH

t

AUXBCLK low 10 ns

XBL

t

AUXLRCLK setup To AUXBCLK rising 10 ns

DLS

t

AUXLRCLK hold From AUXBCLK rising 5 ns

DLH

40 60 %

DAC/ADC clock source = PLL clock @ 256 f 384 f

, 512 fS, and 768 fS

S

DAC/ADC clock source = direct MCLK @ 512 f

,

S

40 60 %

S

(bypass on-chip PLL)

low

RST

recovery

RST

15 ns Reset to active output 4096 t

MCLK

40 60 %

= 1/t

CLATCH CLATCH CLATCH

setup hold high

CCLK

, only t

CCP

To CCLK rising 10 ns From CCLK falling 10 ns Not shown in Figure 11

Rev. A | Page 7 of 32

shown in Figure 11 10 MHz

CCP

10 ns

AD1938

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ABSOLUTE MAXIMUM RATINGS

Table 8.

Parameter Rating

Analog (AVDD) −0.3 V to +3.6 V Digital (DVDD) −0.3 V to +3.6 V Input Current (Except Supply Pins) ±20 mA Analog Input Voltage (Signal Pins) –0.3 V to AVDD + 0.3 V Digital Input Voltage (Signal Pins) −0.3 V to DVDD + 0.3 V Operating Temperature Range (Case) −40°C to +125°C Storage Temperature Range −65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

θJA represents thermal resistance, junction-to-ambient; θ represents the thermal resistance, junction-to-case. All characteristics are for a 4-layer board.

Table 9. Thermal Resistance

Package Type θJA θ

48-Lead LQFP 50.1 17 °C/W

ESD CAUTION

JC

Unit

JC

Rev. A | Page 8 of 32

AD1938

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AGND

MCLKI/XI

MCLKO/XO

AGND

AVDD

OL3

OR3

OL4

OR4

PD/RST

DSDATA4

DGND

AVDD48LF47ADC2RN46ADC2RP45ADC2LN44ADC2LP43ADC1RN42ADC1RP41ADC1LN40ADC1LP39CM38AVDD

1

2

3

4

5

6

7

8

9

10

11

12

13

DVDD

DSDATA314DSDATA215DSDATA1

AD1938

TOP VIEW

(Not to Scale)

SINGLE- ENDED

OUTPUT

16

17

18

DBCLK

20

DLRCLK

ASDATA219ASDATA1

21

ABCLK

37

36

AGND

35

FILTR

34

AGND

33

AVDD

32

AGND

31

OR2

30

OL2

29

OR1

28

OL1

27

CLATCH

26

CCLK

25

DGND

22

23

24

CIN

COUT

ALRCLK

05582-002

Figure 2. Pin Configuration, 48-Lead LQFP

Table 10. Pin Function Descriptions

Pin No. In/Out Mnemonic Description

1 I AGND Analog Ground.

2 I MCLKI/XI Master Clock Input/Crystal Oscillator Input.

3 O MCLKO/XO Master Clock Output/Crystal Oscillator Output.

4 I AGND Analog Ground.

5 I AVDD Analog Power Supply. Connect to analog 3.3 V supply.

6 O OL3 DAC 3 Left Output.

7 O OR3 DAC 3 Right Output.

8 O OL4 DAC 4 Left Output.

9 O OR4 DAC 4 Right Output.

10 I

PD

/RST

Power-Down Reset (Active Low).

11 I/O DSDATA4 DAC Input 4. Input to DAC L4 and DAC R4/DAC TDM Data Out 2/AUX ADC 1 Data In.

12 I DGND Digital Ground.

13 I DVDD Digital Power Supply. Connect to digital 3.3 V supply.

14 I/O DSDATA3 DAC Input 3. Input to DAC L3 and DAC R3/DAC TDM Data In 2/Aux DAC 2 Data Out.

15 I/O DSDATA2 DAC Input 2. Input to DAC L2 and DAC R2/DAC TDM Data Out/AUX ADC 1 Data In.

16 I DSDATA1 DAC Input 1. Input to DAC L1 and DAC R1/DAC TDM Data In/AUX ADC 2 Data In.

17 I/O DBCLK Bit Clock for DACs.

18 I/O DLRCLK LR Clock for DACs.

19 I/O ASDATA2 ADC Serial Data Output 2 (ADC L2 and ADC R2)/ADC TDM Data Input/Aux DAC 1 Data Out.

20 O ASDATA1 ADC Serial Data Output 1 (ADC L1 and ADC R1)/ADC TDM Data Output.

21 I/O ABCLK Bit Clock for ADCs.

22 I/O ALRCLK LR Clock for ADCs.

23 I CIN Control Data Input (SPI).

24 I/O COUT Control Data Output (SPI).

25 I DGND Digital Ground.

26 I CCLK Control Clock Input (SPI).

27 I

CLATCH

Latch Input for Control Data (SPI).

28 O OL1 DAC 1 Left Output.

Rev. A | Page 9 of 32

AD1938

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Pin No. In/Out Mnemonic Description

29 O OR1 DAC 1 Right Output. 30 O OL2 DAC 2 Left Output. 31 O OR2 DAC 2 Right Output. 32 I AGND Analog Ground. 33 I AVDD Analog Power Supply. Connect to analog 3.3 V supply. 34 I AGND Analog Ground. 35 O FILTR Voltage Reference Filter Capacitor Connection. Bypass with 10 μF||100 nF to AGND. 36 I AGND Analog Ground. 37 I AVDD Analog Power Supply. Connect to analog 3.3 V supply. 38 O CM Common-Mode Reference Filter Capacitor Connection. Bypass with 47 μF||100 nF to AGND. 39 I ADC1LP ADC1 Left Positive Input. 40 I ADC1LN ADC1 Left Negative Input. 41 I ADC1RP ADC1 Right Positive Input. 42 I ADC1RN ADC1 Right Negative Input. 43 I ADC2LP ADC2 Left Positive Input. 44 I ADC2LN ADC2 Left Negative Input. 45 I ADC2RP ADC2 Right Positive Input. 46 I ADC2RN ADC2 Right Negative Input. 47 O LF PLL Loop Filter, Return to AVDD. 48 I AVDD Analog Power Supply. Connect to analog 3.3 V supply.

Rev. A | Page 10 of 32

ANALOG DEVICES AD1938 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TEST CONDITIONS

ANALOG PERFORMANCE SPECIFICATIONS

CRYSTAL OSCILLATOR SPECIFICATIONS

DIGITAL INPUT/OUTPUT SPECIFICATIONS

POWER SUPPLY SPECIFICATIONS

DIGITAL FILTERS

TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS