ANALOG DEVICES AD1937 Service Manual

Four ADCs/Eight DACs with PLL,

A

www.BDTIC.com/ADI

FEATURES

PLL-generated clock or direct master clock Low EMI design 112 dB DAC/107 dB ADC dynamic range and SNR

−96 dB THD + N Single 3.3 V supply Tolerance for 5 V logic inputs Supports 24-bits and 8 kHz to 192 kHz sample rates Differential ADC input Differential DAC output Log volume control with autoramp function

2

I

C-controllable for flexibility Software-controllable clickless mute Software power-down Right-justified, left-justified, I Master and slave modes up to 16-channel input/output Available in a 64-lead LQFP AECQ-100 qualified

APPLICATIONS

Automotive audio systems Home theater systems Set-top boxes Digital audio effects processors

2

S, and TDM modes

192 kHz, 24-Bit Codec

AD1937

GENERAL DESCRIPTION

The AD1937 is a high performance, single-chip codec that provides four analog-to-digital converters (ADCs) with differential input and eight digital-to-analog converters (DACs) with differential output, using the Analog Devices, Inc., patented multibit sigmadelta (Σ-Δ) architecture. An I microcontroller to adjust volume and many other parameters. The AD1937 operates from 3.3 V digital and analog supplies. The AD1937 is available in a 64-lead (differential output) LQFP.

The AD1937 is designed for low EMI. This consideration is apparent in both the system and circuit design architectures. By using the on-board PLL to derive the master clock from the LR (frame) clock or from an external crystal, the AD1937 eliminates the need for a separate high frequency master clock and can also be used with a suppressed bit clock. The DACs and ADCs are designed using the latest Analog Devices continuous time architecture to further minimize EMI. By using 3.3 V supplies, power consumption is minimized and further reduces emissions.

2

C® port is included, allowing a

FUNCTIONAL BLOCK DIAGRAM

DIGITAL AUDIO INPUT/OUTPUT

AD1937

ADC

NALOG

AUDIO

INPUTS

ADC

PRECISION

VOLTAGE

REFERENCE

DIGITAL

FILTER

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

SERIAL DATA PORT

SDATA

OUT

TIMING MANAGEMENT

AND CONTROL

(CLOCK AND PLL )

CONTROL PORT

CONTROL DAT A

INPUT/OUTPUT

DAC

SDATA

IN

CLOCKS

I2C

Figure 1.

DIGITAL

FILTER

AND

VOLUME

CONTROL

DAC

ANALOG AUDIO OUTPUTS

07414-001

AD1937

www.BDTIC.com/ADI

REVISION HISTORY

9/08—Revision 0: Initial Version

Rev. 0 | Page 2 of 36

AD1937

www.BDTIC.com/ADI

SPECIFICATIONS

TEST CONDITIONS

Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications.

Table 1.

Parameter Value

Supply Voltages (AVDD, DVDD) 3.3 V Temperature As specified in Table 2 and Table 3 Master Clock 12.288 MHz (48 kHz fS, 256 × fS mode) Input Sample Rate 48 kHz Measurement Bandwidth 20 Hz to 20 kHz Word Width 24 bits Load Capacitance (Digital Output) 20 pF Load Current (Digital Output) ±1 mA or 1.5 kΩ to ½ DVDD supply Input Voltage High 2.0 V Input Voltage Low 0.8 V

ANALOG PERFORMANCE SPECIFICATIONS

Specifications guaranteed at a TA of 25°C.

Table 2.

Parameter Conditions/Comments Min Typ Max Unit

ANALOG-TO-DIGITAL CONVERTERS

ADC Resolution All ADCs 24 Bits Dynamic Range 20 Hz to 20 kHz, −60 dB input

No Filter (RMS) 96 102 dB

With A-Weighted Filter (RMS) 98 105 dB Total Harmonic Distortion + Noise −1 dBFS −96 −87 dB Full-Scale Input Voltage (Differential) 1.9 V rms Gain Error −10 +10 % Interchannel Gain Mismatch −0.25 +0.25 dB Offset Error −10 0 +10 mV Gain Drift 100 ppm/°C Interchannel Isolation −110 dB CMRR 100 mV rms, 1 kHz 55 dB 100 mV rms, 20 kHz 55 dB Input Resistance 14 kΩ Input Capacitance 10 pF Input Common-Mode Bias Voltage 1.5 V

DIGITAL-TO-ANALOG CONVERTERS

DAC Resolution All DACs 24 Bits Dynamic Range 20 Hz to 20 kHz, −60 dB input

No Filter (RMS) 102 107 dB

With A-Weighted Filter (RMS) 105 110 dB

With A-Weighted Filter (Average) 112 dB

Rev. 0 | Page 3 of 36

AD1937

www.BDTIC.com/ADI

Parameter Conditions/Comments Min Typ Max Unit

Total Harmonic Distortion + Noise 0 dBFS

Two channels running −94 dB

Eight channels running −86 −76 dB Full-Scale Output Voltage 1.76 (4.96) V rms (V p-p) Gain Error −10 +10 % Interchannel Gain Mismatch −0.2 +0.2 dB Offset Error −25 −6 +25 mV Gain Drift −30 +30 ppm/°C Interchannel Isolation 100 dB Interchannel Phase Deviation 0 Degrees Volume Control Step 0.375 dB Volume Control Range 95 dB De-emphasis Gain Error ±0.6 dB Output Resistance at Each Pin 100 Ω

REFERENCE

Internal Reference Voltage FILTR pin 1.50 V External Reference Voltage FILTR pin 1.32 1.50 1.68 V Common-Mode Reference Output CM pin 1.50 V

REGULATOR

Input Supply Voltage VSUPPLY pin 4.5 5 5.5 V Regulated Output Voltage VSENSE pin 3.19 3.37 3.55 V

Rev. 0 | Page 4 of 36

AD1937

www.BDTIC.com/ADI

Specifications measured at a TC of 130°C.

Table 3.

Parameter Conditions/Comments Min Typ Max Unit

ANALOG-TO-DIGITAL CONVERTERS

ADC Resolution All ADCs 24 Bits Dynamic Range 20 Hz to 20 kHz, −60 dB input

No Filter (RMS) 93 102 dB

With A-Weighted Filter (RMS) 96 104 dB Total Harmonic Distortion + Noise −1 dBFS −96 −87 dB Full-Scale Input Voltage (Differential) 1.9 V rms Gain Error −10 +10 % Interchannel Gain Mismatch −0.25 +0.25 dB Offset Error −10 0 +10 mV

DIGITAL-TO-ANALOG CONVERTERS

DAC Resolution All DACs 24 Bits Dynamic Range 20 Hz to 20 kHz, −60 dB input

No Filter (RMS) 101 107 dB

With A-Weighted Filter (RMS) 104 110 dB

With A-Weighted Filter (Average) 112 dB Total Harmonic Distortion + Noise 0 dBFS

Two channels running −94 dB

Eight channels running −86 −70 dB Full-Scale Output Voltage 1.76 (4.96) V rms (V p-p) Gain Error −10 +10 % Interchannel Gain Mismatch −0.2 +0.2 dB Offset Error −25 −6 +25 mV Gain Drift −30 +30 ppm/°C

REFERENCE

Internal Reference Voltage FILTR pin 1.50 V External Reference Voltage FILTR pin 1.32 1.50 1.68 V Common-Mode Reference Output CM pin 1.50 V

REGULATOR

Input Supply Voltage VSUPPLY pin 4.5 5 5.5 V Regulated Output Voltage VSENSE pin 3.2 3.43 3.65 V

CRYSTAL OSCILLATOR SPECIFICATIONS

Table 4.

Parameter Min Typ Max Unit

Transconductance 3.5 mmhos

Rev. 0 | Page 5 of 36

AD1937

www.BDTIC.com/ADI

DIGITAL SPECIFICATIONS

−40°C < TA < +130°C, DVDD = 3.3 V ± 10%.

Table 5.

Parameter Conditions/Comments Min Typ Max Unit

INPUT

High Level Input Voltage (VIH) 2.0 V MCLKI/MCLKXI pin 2.2 V Low Level Input Voltage (VIL) 0.8 V Input Leakage IIH @ VIH = 2.4 V 10 μA I Input Capacitance 5 pF

OUTPUT

High Level Output Voltage (VOH) IOH = 1 mA DVDD − 0.60 V Low Level Output Voltage (VOL) IOL = 1 mA 0.4 V

POWER SUPPLY SPECIFICATIONS

Table 6.

Parameter Conditions/Comments Min Typ Max Unit

SUPPLIES

Voltage DVDD 3.0 3.3 3.6 V AVDD 3.0 3.3 3.6 V VSUPPLY 4.5 5.0 5.5 V Digital Current Master clock = 256 f

Normal Operation fS = 48 kHz 56 mA

f f

Power-Down fS = 48 kHz to 192 kHz 2.0 mA

Analog Current

Normal Operation 74 mA Power-Down 23 mA

DISSIPATION

Operation Master clock = 256 fS, 48 kHz

All Supplies 429 mW Digital Supply 185 mW

Analog Supply 244 mW

Power-Down, All Supplies 83 mW

POWER SUPPLY REJECTION RATIO

Signal at Analog Supply Pins 1 kHz, 200 mV p-p 50 dB 20 kHz, 200 mV p-p 50 dB

@ VIL = 0.8 V 10 μA

IL

S

= 96 kHz 65 mA

S

= 192 kHz 95 mA

S

Rev. 0 | Page 6 of 36

AD1937

www.BDTIC.com/ADI

DIGITAL FILTERS

Table 7.

Parameter Mode Factor Min Typ Max Unit

ADC DECIMATION FILTER

Pass Band 0.4375 × f

All modes, typical @ 48 kHz

S

Pass-Band Ripple ±0.015 dB Transition Band 0.5 × f Stop Band 0.5625 × f

S

Stop-Band Attenuation 79 dB Group Delay 22.9844 ÷ f

DAC INTERPOLATION FILTER

Pass Band 48 kHz mode, typical @ 48 kHz 0.4535 × f 96 kHz mode, typical @ 96 kHz 0.3646 × f 192 kHz mode, typical @ 192 kHz 0.3646 × f

S

Pass-Band Ripple 48 kHz mode, typical @ 48 kHz ±0.01 dB 96 kHz mode, typical @ 96 kHz ±0.05 dB 192 kHz mode, typical @ 192 kHz ±0.1 dB Transition Band 48 kHz mode, typical @ 48 kHz 0.5 × f 96 kHz mode, typical @ 96 kHz 0.5 × f 192 kHz mode, typical @ 192 kHz 0.5 × f Stop Band 48 kHz mode, typical @ 48 kHz 0.5465 × f 96 kHz mode, typical @ 96 kHz 0.6354 × f 192 kHz mode, typical @ 192 kHz 0.6354 × f

S

Stop-Band Attenuation 48 kHz mode, typical @ 48 kHz 70 dB 96 kHz mode, typical @ 96 kHz 70 dB 192 kHz mode, typical @ 192 kHz 70 dB Group Delay 48 kHz mode, typical @ 48 kHz 25 ÷ f

96 kHz mode, typical @ 96 kHz 11 ÷ f 192 kHz mode, typical @ 192 kHz 8 ÷ f

S

21 kHz

24 kHz 27 kHz

479 μs

S

22 kHz 35 kHz 70 kHz

24 kHz 48 kHz 96 kHz 26 kHz 61 kHz 122 kHz

521 μs 115 μs 42 μs

Rev. 0 | Page 7 of 36

AD1937

www.BDTIC.com/ADI

TIMING SPECIFICATIONS

−40°C < TA < +130°C, DVDD = 3.3 V ± 10%.

Table 8.

Parameter Condition Comments Min Max Unit

INPUT MASTER CLOCK (MCLK) AND RESET

tMH MCLK duty cycle

t

MH

f

MCLK frequency PLL mode, 256 fS reference 6.9 13.8 MHz

MCLK

f

MCLK

t

PDR

t

PDRR

PLL

Lock Time MCLK or LRCLK 10 ms 256 fS VCO Clock, Output Duty Cycle,

MCLKO/MCLKXO Pin

I2C See Figure 13 and Figure 14

f

SCL clock frequency 400 kHz

SCL

t

SCL low 1.3 μs

SCLL

t

SCL high 0.6 μs

SCLH

t

Setup time (start condition) Relevent for repeated start condition 0.6 μs

SCS

t

Hold time (start condition) First clock generated after this period 0.6 μs

SCH

t

Setup time (stop condition) 0.6 μs

SSH

tDS Data setup time 100 ns tSR SDA and SCL rise time 300 ns tSF SDA and SCL fall time 300 ns t

Bus-free time Between stop and start 1.3 μs

BFT

DAC SERIAL PORT See Figure 2

t

DBH

t

DBL

t

DLS

DLRCLK skew From DBCLK falling, master mode −8 +8 ns t

DLH

t

DDS

t

DDH

ADC SERIAL PORT See Figure 3

t

ABH

t

ABL

t

ALRCLK setup To ABCLK rising, slave mode 10 ns

ALS

ALRCLK skew From ABCLK falling, master mode −8 +8 ns t

ALH

t

ABDD

AUXILIARY INTERFACE

t

AXDS

t

AXDH

t

DXDD

t

XBH

t

XBL

t

DLS

t

DLH

DAC/ADC clock source = PLL clock

, 384 fS, 512 fS, and 768 f

@ 256 f

S

DAC/ADC clock source = direct MCLK

(bypass on-chip PLL)

@ 512 f

S

40 60 %

Direct 512 fS mode 27.6 MHz Low 15 ns Recovery Reset to active output 4096 t

MCLK

40 60 %

DBCLK high Slave mode 10 ns DBCLK low Slave mode 10 ns DLRCLK setup To DBCLK rising, slave mode 10 ns

DLRCLK hold From DBCLK rising, slave mode 5 ns DS DATA setup To D BCLK rising 10 n s DSDATA hold From DBCLK rising 5 ns

ABCLK high Slave mode 10 ns ABCLK low Slave mode 10 ns

ALRCLK hold From ABCLK rising, slave mode 5 ns ASDATA delay From ABCLK falling, any mode 18 ns

AAUXDATA s etu p To AU XBCLK rising 10 n s AAUXDATA hold From AUXBCLK rising 5 ns DAUXDATA delay From AUXBCLK falling 18 ns AUXBCLK high 10 ns AUXBCLK low 10 ns AUXLRCLK setup To AUXBCLK rising 10 ns AUXLRCLK hold From AUXBCLK rising 5 ns

Rev. 0 | Page 8 of 36

AD1937

www.BDTIC.com/ADI

TIMING DIAGRAMS

t

DBH

DBCLK

t

DBL

t

DDS

t

DLH

t

DDH

t

ALH

07414-025

LEFT-JUSTIFIED

2

I

S-JUSTIFIED

RIGHT-JUST IFIED

DLRCLK

DSDATAx

MODE

DSDATAx

MODE

DSDATAx

MODE

ABCLK

ALRCLK

t

ABH

t

DLS

t

DDS

MSB

t

DDH

MSB – 1

t

DDS

MSB

t

DDH

t

DDS

MSB LSB

t

DDH

Figure 2. DAC Serial Timing

t

ABL

t

ALS

LEFT-JUSTIFIED

2

I

S-JUSTIFIED

RIGHT-JUST IFIED

ASDATAx

MODE

ASDATAx

MODE

ASDATAx

MODE

t

ABDD

MSB

t

ABDD

MSB – 1

MSB

Figure 3. ADC Serial Timing

t

ABDD

MSB

LSB

7414-026

Rev. 0 | Page 9 of 36

AD1937

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

Table 9.

Parameter Rating

Analog (AVDD) −0.3 V to +3.6 V Digital (DVDD) −0.3 V to +3.6 V VSUPPLY −0.3 V to +6.0 V Input Current (Except Supply Pins) ±20 mA Analog Input Voltage (Signal Pins) –0.3 V to AVDD + 0.3 V Digital Input Voltage (Signal Pins) −0.3 V to DVDD + 0.3 V Operating Temperature Range (Case) −40°C to +125°C Storage Temperature Range −65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

θJA represents junction-to-ambient thermal resistance;

represents the junction-to-case thermal resistance.

θ

JC

All characteristics are for a 4-layer board.

Table 10.

Package Type θ

64-Lead LQFP 47 11.1 °C/W

JA

θ

JC

Unit

ESD CAUTION

Rev. 0 | Page 10 of 36

AD1937

www.BDTIC.com/ADI

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AGND

MCLKI/MCL KXI

MCLKO/MCLKXO

AGND

AVDD

DAC3LP

DAC3LN

DAC3RP

DAC3RN

DAC4LP

DAC4LN

DAC4RP

DAC4RN

PD/RST

DSDATA4

DGND

NC = NO CONNECT

NC64NC63AVDD62LF61ADC2RN60ADC2RP59ADC2LN58ADC2LP57ADC1RN56ADC1RP55ADC1LN54ADC1LP53CM52AVDD51NC50NC

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

DVDD

20

DSDATA318DSDATA219DSDATA1

21

AD1937

TOP VIEW

(Not to Scale)

DIFFERENTIAL OUTPUT

22

23

24

25

DBCLK

DLRCLK

VDRIVE

VSENSE

VSUPPLY

ASDATA226ASDATA1

27

28

ABCLK

Figure 4. Pin Configuration

49

48

AGND

47

FILTR

46

AGND

45

AVDD

44

AGND

43

DAC2RN

42

DAC2RP

41

DAC2LN

40

DAC2LP

39

DAC1RN

38

DAC1RP

37

DAC1LN

36

DAC1LP

35

ADDR1

34

SCL

33

DGND

29

30

31

32

SDA

DVDD

ADDR0

ALRCLK

07414-002

Table 11. Pin Function Descriptions

Pin No. Type

1

Mnemonic Description

1, 4, 44, 46, 48 I AGND Analog Ground. 2 I MCLKI/MCLKXI Master Clock Input/Crystal Oscillator Input. 3 O MCLKO/MCLKXO Master Clock Output/Crystal Oscillator Output. 5, 45, 51, 62 I AVDD Analog Power Supply. Connect this pin to analog 3.3 V supply. 6 O DAC3LP DAC3 Left Positive Output. 7 O DAC3LN DAC3 Left Negative Output. 8 O DAC3RP DAC3 Right Positive Output. 9 O DAC3RN DAC3 Right Negative Output. 10 O DAC4LP DAC4 Left Positive Output. 11 O DAC4LN DAC4 Left Negative Output. 12 O DAC4RP DAC4 Right Positive Output. 13 O DAC4RN DAC4 Right Negative Output 14 I

PD

/RST

15 I/O DSDATA4

Power-Down Reset (Active Low). DAC Serial Data Input 4. Data input to DAC4 data in/TDM DAC2 data out (dual-line mode)/

AUX DAC2 data out (to external DAC2). 16, 33 I DGND Digital Ground. 17, 32 I DVDD Digital Power Supply. Connect this pin to digital 3.3 V supply. 18 I/O DSDATA3

DAC Serial Data Input 3. Data input to DAC3 data in/TDM DAC2 data in (dual-line mode)/AUX

ADC2 data in (from external ADC2). 19 I/O DSDATA2

DAC Serial Data Input 2. Data input to DAC2 data in/TDM DAC data out/AUX ADC1 data in

(from external ADC1). 20 I DSDATA1 DAC Serial Data Input 1. Data input to DAC1 data in/TDM DAC data in/TDM data in. 21 I/O DBCLK Bit Clock for DACs. Can be programmed as input or output in all modes. 22 I/O DLRCLK Frame Clock for DACs. Can be programmed as input or output in all modes.

Rev. 0 | Page 11 of 36

ANALOG DEVICES AD1937 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TEST CONDITIONS

ANALOG PERFORMANCE SPECIFICATIONS

CRYSTAL OSCILLATOR SPECIFICATIONS

DIGITAL SPECIFICATIONS

POWER SUPPLY SPECIFICATIONS

DIGITAL FILTERS

TIMING SPECIFICATIONS

TIMING DIAGRAMS

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS