ANALOG DEVICES AD1934 Service Manual

8-Channel DAC with PLL and

FEATURES

PLL generated or direct master clock Low EMI design 108 dB DAC dynamic range and SNR

−94 dB THD + N Single 3.3 V supply Tolerance for 5 V logic inputs Supports 24 bits and 8 kHz to 192 kHz sample rates Single-ended DAC output Log volume control with autoramp function SPI® controllable for flexibility Software-controllable clickless mute Software power-down Right-justified, left-justified, I Master and slave modes up to 16-channel in/out 48-lead LQFP Qualified for automotive applications

APPLICATIONS

Automotive audio systems Home theater systems Set-top boxes Digital audio effects processors

2

S, and TDM modes

Single-Ended Outputs, 192 kHz, 24 Bits

AD1934

GENERAL DESCRIPTION

The AD1934 is a high performance, single chip that provides eight digital-to-analog converters (DACs) with single-ended output using the Analog Devices, Inc., patented multibit sigmadelta (Σ-Δ) architecture. An SPI port is included, allowing a microcontroller to adjust volume and many other parameters. The AD1934 operates from 3.3 V digital and analog supplies. The AD1934 is available in a 48-lead (single-ended output) LQFP. Other members of this family include a differential DAC output version.

The AD1934 is designed for low EMI. This consideration is apparent in both the system and circuit design architectures. By using the on-board PLL to derive the master clock from the LR clock or from an external crystal, the AD1934 eliminates the need for a separate high frequency master clock and can also be used with a suppressed bit clock. The DACs are designed using the latest Analog Devices continuous time architectures to further minimize EMI. By using 3.3 V supplies, power consumption is minimized, further reducing emissions.

FUNCTIONAL BLOCK DIAGRAM

AD1934

DIGITAL AUDIO INPUT/OUTPUT

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

SERIAL

DATA PORT

PRECISION

VOLTAGE

REFERENCE

CLOCKS

SDATAIN

TIMING MANAGEMENT

(CLOCK AND PLL )

AND CONTROL

CONTROL PO RT

SPI

CONTROL DAT A

INPUT/OUTPUT

Figure 1.

DIGITAL

FILTER

AND

VOLUME

CONTROL

6.144MHz

DAC

ANALOG AUDIO OUTPUTS

6106-001

AD1934

REVISION HISTORY

7/11—Rev. B to Rev. C

Deleted References to I Changes to Figure 2 and Table 10, DSDATAx/AUXDATA1 Pin

Descriptions ...................................................................................... 9

1/11—Rev. A to Rev. B

Added Automotive Information.................................. Throughout

Change to Table 2, Introductory Text ............................................ 4

Change to Table 4, Introductory Text ............................................ 4

Change to Table 7, Introductory Text ............................................ 6

2

C ............................................. Throughout

Ordering Guide .......................................................................... 26

Automotive Products................................................................. 26

Changes to Ordering Guide.......................................................... 26

9/09—Rev. 0 to Rev. A

Change to Title...................................................................................1

Change to Table 11 ......................................................................... 13

Change to Power Supply and Voltage Reference Section.......... 14

Updated Outline Dimensions....................................................... 26

Changes to Ordering Guide.......................................................... 26

8/07—Revision 0: Initial Version

Rev. C | Page 2 of 28

AD1934

SPECIFICATIONS

TEST CONDITIONS

Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications.

Supply Voltages (AVDD, DVDD) 3.3 V Temperature Range Master Clock 12.288 MHz (48 kHz f Input Sample Rate 48 kHz Measurement Bandwidth 20 Hz to 20 kHz Word Width 24 bits Load Capacitance (Digital Output) 20 pF Load Current (Digital Output) ±1 mA or 1.5 kΩ to ½ DVDD supply Input Voltage HI 2.0 V Input Voltage LO 0.8 V

1

Functionally guaranteed at −40°C to +125°C case temperature.

ANALOG PERFORMANCE SPECIFICATIONS

Specifications guaranteed at 25°C (ambient).

Table 1.

Parameter Test Conditions/Comments Min Typ Max Unit

DIGITAL-TO-ANALOG CONVERTERS

Dynamic Range 20 Hz to 20 kHz, −60 dB input

No Filter (RMS) 98 104 dB With A-Weighted Filter (RMS) 100 106 dB With A-Weighted Filter (Average) 108 dB

Total Harmonic Distortion + Noise 0 dBFS

Single-Ended Version Two channels running −92 dB

Eight channels running −86 −75 dB Full-Scale Output Voltage 0.88 (2.48) V rms (V p-p) Gain Error −10 +10 % Interchannel Gain Mismatch −0.2 +0.2 dB Offset Error −16 −4 +16 mV Gain Drift −30 +30 ppm/°C Interchannel Isolation 100 dB Interchannel Phase Deviation 0 Degrees Volume Control Step 0.375 dB Volume Control Range 95 dB De-emphasis Gain Error ±0.6 dB Output Resistance at Each Pin 100 Ω

REFERENCE

Internal Reference Voltage FILTR pin 1.50 V External Reference Voltage FILTR pin 1.32 1.50 1.68 V Common-Mode Reference Output CM pin 1.50 V

1

As specified in Table 1 and Table 2

, 256 × fS mode)

S

Rev. C | Page 3 of 28

AD1934

Specifications measured at 125°C (case).

Table 2.

Parameter Test Conditions/Comments Min Typ Max Unit

DIGITAL-TO-ANALOG CONVERTERS

Dynamic Range 20 Hz to 20 kHz, −60 dB input

No Filter (RMS) 98 104 dB With A-Weighted Filter (RMS) 100 106 dB With A-Weighted Filter (Average) 108 dB

Total Harmonic Distortion + Noise 0 dBFS

Single-Ended Version Two channels running −92 dB

Eight channels running −86 −70 dB Full-Scale Output Voltage 0.8775 (2.482) V rms (V p-p) Gain Error −10 +10 % Interchannel Gain Mismatch −0.2 +0.2 dB Offset Error −16 −4 +16 mV Gain Drift −30 +30 ppm/°C

REFERENCE

Internal Reference Voltage FILTR pin 1.50 V External Reference Voltage FILTR pin 1.32 1.50 1.68 V Common-Mode Reference Output CM pin 1.50 V

CRYSTAL OSCILLATOR SPECIFICATIONS

Table 3.

Parameter Min Typ Max Unit

Transconductance 3.5 mmhos

DIGITAL INPUT/OUTPUT SPECIFICATIONS

−40°C < TC < 125°C, DVDD = 3.3 V ± 10%.

Table 4.

Parameter Test Conditions/Comments Min Typ Max Unit

Input Voltage HI (VIH) 2.0 V Input Voltage HI (VIH) MCLKI pin 2.2 V Input Voltage LO (VIL) 0.8 V Input Leakage IIH @ VIH = 2.4 V 10 μA I High Level Output Voltage (VOH) IOH = 1 mA DVDD − 0.60 V Low Level Output Voltage (VOL) IOL = 1 mA 0.4 V Input Capacitance 5 pF

@ VIL = 0.8 V 10 μA

IL

Rev. C | Page 4 of 28

AD1934

POWER SUPPLY SPECIFICATIONS

Table 5.

Parameter Test Conditions/Comments Min Ty p Max Unit SUPPLIES

Voltage DVDD 3.0 3.3 3.6 V AVDD 3.0 3.3 3.6 V Digital Current MCLK = 256 fS

Normal Operation fS = 48 kHz 56 mA f f Power-Down fS = 48 kHz to 192 kHz 2.0 mA

Analog Current

Normal Operation 74 mA Power-Down 23 mA

DISSIPATION

Operation MCLK = 256 fS, 48 kHz

All Supplies 429 mW Digital Supply 185 mW Analog Supply 244 mW

Power-Down, All Supplies 83 mW

POWER SUPPLY REJECTION RATIO

Signal at Analog Supply Pins 1 kHz, 200 mV p-p 50 dB 20 kHz, 200 mV p-p 50 dB

= 96 kHz 65 mA

S

= 192 kHz 95 mA

S

Rev. C | Page 5 of 28

AD1934

DIGITAL FILTERS

Table 6.

Parameter Mode Factor Min Typ Max Unit

DAC INTERPOLATION FILTER

Pass Band 48 kHz mode, typ @ 48 kHz 0.4535 fS 22 kHz 96 kHz mode, typ @ 96 kHz 0.3646 fS 35 kHz 192 kHz mode, typ @ 192 kHz 0.3646 fS 70 kHz Pass-Band Ripple 48 kHz mode, typ @ 48 kHz ±0.01 dB 96 kHz mode, typ @ 96 kHz ±0.05 dB 192 kHz mode, typ @ 192 kHz ±0.1 dB Transition Band 48 kHz mode, typ @ 48 kHz 0.5 fS 24 kHz 96 kHz mode, typ @ 96 kHz 0.5 fS 48 kHz 192 kHz mode, typ @ 192 kHz 0.5 fS 96 kHz Stop Band 48 kHz mode, typ @ 48 kHz 0.5465 fS 26 kHz 96 kHz mode, typ @ 96 kHz 0.6354 fS 61 kHz 192 kHz mode, typ @ 192 kHz 0.6354 fS 122 kHz Stop-Band Attenuation 48 kHz mode, typ @ 48 kHz 70 dB 96 kHz mode, typ @ 96 kHz 70 dB 192 kHz mode, typ @ 192 kHz 70 dB Group Delay 48 kHz mode, typ @ 48 kHz 25/fS 521 μs

96 kHz mode, typ @ 96 kHz 11/fS 115 μs 192 kHz mode, typ @ 192 kHz 8/fS 42 μs

TIMING SPECIFICATIONS

−40°C < TC < 125°C, DVDD = 3.3 V ± 10%.

Table 7.

Parameter Condition Comments Min Max Unit

INPUT MASTER CLOCK (MCLK) AND RESET

tMH MCLK duty cycle

tMH

f

MCLK frequency PLL mode, 256 fS reference 6.9 13.8 MHz

MCLK

f

Direct 512 fS mode 27.6 MHz

MCLK

t

PDR

t

PDRR

PLL

Lock Time MCLK and LRCLK input 10 ms 256 fS VCO Clock, Output Duty Cycle

MCLKO Pin

SPI PORT See Figure 9

t

CCLK high 35 ns

CCH

t

CCLK low 35 ns

CCL

f

CCLK frequency f

CCLK

t

CDATA setup To CCLK rising 10 ns

CDS

t

CDATA hold From CCLK rising 10 ns

CDH

t

CLS

t

CLH

t

CLHIGH

t

COUT enable From CCLK falling 30 ns

COE

t

COUT delay From CCLK falling 30 ns

COD

t

COUT hold From CCLK falling, not shown in Figure 9 30 ns

COH

t

COUT tri-state From CCLK falling 30 ns

COTS

40 60 %

DAC clock source = PLL clock @ 256 f

, 512 fS, 768 fS

384 f

S

DAC clock source = direct MCLK @ 512 f

,

S

40 60 %

S

(bypass on-chip PLL)

low

RST

recovery

RST

15 ns Reset to active output 4096 t

MCLK

40 60 %

= 1/t

CLATCH CLATCH CLATCH

setup hold high

CCLK

CCP

, only t

To CCLK rising 10 ns From CCLK falling 10 ns Not shown in Figure 9 10 ns

Rev. C | Page 6 of 28

shown in Figure 9 10 MHz

CCP

AD1934

Parameter Condition Comments Min Max Unit

DAC SERIAL PORT See Figure 16

t

DBCLK high Slave mode 10 ns

DBH

t

DBCLK low Slave mode 10 ns

DBL

t

DLRCLK setup To DBCLK rising, slave mode 10 ns

DLS

t

DLRCLK hold From DBCLK rising, slave mode 5 ns

DLH

t

DLRCLK skew From DBCLK falling, master mode −8 +8 ns

DLS

t

DS DATA setup To D BCLK rising 10 ns

DDS

t

DSDATA hold From DBCLK rising 5 ns

DDH

AUXTDM SERIAL PORT See Figure 17

t

AUXTDMBCLK high Slave mode 10 ns

ABH

t

AUXTDMBCLK low Slave mode 10 ns

ABL

t

AUXTDMLRCLK setup To AUXTDMBCLK rising, slave mode 10 ns

ALS

t

AUXTDMLRCLK hold From AUXTDMBCLK rising, slave mode 5 ns

ALH

t

AUXTDMLRCLK skew From AUXTDMBCLK falling, master mode −8 +8 ns

ALS

t

DSDATA setup To AUXTDMBCLK, not shown in Figure 17 10 ns

DDS

t

DSDATA hold

DDH

From AUXTDMBCLK rising, not shown in Figure 17

AUXILIARY INTERFACE

t

AUXDATA delay From AUXBCLK falling 18 ns

DXDD

t

AUXBCLK high 10 ns

XBH

t

AUXBCLK low 10 ns

XBL

t

AUXLRCLK setup To AUXBCLK rising 10 ns

DLS

t

AUXLRCLK hold From AUXBCLK rising 5 ns

DLH

5 ns

Rev. C | Page 7 of 28

AD1934

ABSOLUTE MAXIMUM RATINGS

Table 8.

Parameter Rating

Analog (AVDD) −0.3 V to +3.6 V Digital (DVDD) −0.3 V to +3.6 V Input Current (Except Supply Pins) ±20 mA Analog Input Voltage (Signal Pins) −0.3 V to AVDD + 0.3 V Digital Input Voltage (Signal Pins) −0.3 V to DVDD + 0.3 V Operating Temperature Range (Case) −40°C to +125°C Storage Temperature Range −65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

θJA represents thermal resistance, junction-to-ambient;

represents the thermal resistance, junction-to-case.

θ

JC

All characteristics are for a 4-layer board.

Table 9. Thermal Resistance

Package Type θJA θ

48-Lead LQFP 50.1 17 °C/W

Unit

JC

ESD CAUTION

Rev. C | Page 8 of 28

AD1934

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

AGND

AVDD

OL3

OR3

OL4

OR4

PD/RST

DGND

2

3

4

5

6

7

8

9

10

11

12

MCLKI/XI

MCLKO/XO

DSDATA4

NC = NO CONNECT

AVDD48LF47NC46NC45NC44NC43NC42NC41NC40NC39CM38AVDD

AD1934

TOP VIEW

(Not to Scale)

SINGLE- ENDED

OUTPUT

13

DVDD

16

DSDATA314DSDATA215DSDATA1

17

18

19NC20

21

DBCLK

DLRCLK

AUXDATA1

AUXTDMBCLK

37

36

AGND

35

FILTR

34

AGND

33

AVDD

32

AGND

31

OR2

30

OL2

29

OR1

28

OL1

27

CLATCH

26

CCLK

25

DGND

22

23

24

CIN

COUT

06106-020

AUXTDML RCLK

Figure 2. Pin Configuration

Table 10. Pin Function Description

Pin No. Input/Output Mnemonic Description

1 I AGND Analog Ground. 2 I MCLKI/XI Master Clock Input/Crystal Oscillator Input. 3 O MCLKO/XO Master Clock Output/Crystal Oscillator Output. 4 I AGND Analog Ground. 5 I AVDD Analog Power Supply. Connect to analog 3.3 V supply. 6 O OL3 DAC 3 Left Output. 7 O OR3 DAC 3 Right Output. 8 O OL4 DAC 4 Left Output. 9 O OR4 DAC 4 Right Output. 10 I

PD

/RST

11 I/O DSDATA4

Power-Down Reset (Active Low). DAC Serial Data Input 4. Data input to DAC4 data in/TDM DAC2 data out (dual-line

mode)/AUX DAC2 data out (to external DAC2). 12 I DGND Digital Ground. 13 I DVDD Digital Power Supply. Connect to digital 3.3 V supply. 14 I/O DSDATA3

DAC Serial Data Input 3. Data input to DAC3 data in/TDM DAC2 data in (dual-line

mode)/AUX not used. 15 I/O DSDATA2 DAC Serial Data Input 2. Data input to DAC2 data in/TDM DAC2 data out/AUX not used. 16 I DSDATA1 DAC Serial Data Input 1. Data input to DAC1 data in/TDM DAC data in/AUX TDM data in. 17 I/O DBCLK Bit Clock for DACs (Regular Stereo, TDM, or Daisy-Chain TDM Mode). 18 I/O DLRCLK LR Clock for DACs (Regular Stereo, TDM, or Daisy-Chain TDM Mode). 19 O AUXDATA1 AUX DAC1 data out (to external DAC1). 20 NC No Connect. 21 I/O AUXTDMBCLK Auxiliary Mode Only DAC TDM Bit Clock. 22 I/O AUXTDMLRCLK Auxiliary Mode Only DAC LR TDM Clock. 23 I CIN/ADR0 Control Data Input (SPI). 24 I/O COUT/SDA Control Data Output (SPI). 25 I DGND Digital Ground.

Rev. C | Page 9 of 28

ANALOG DEVICES AD1934 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TEST CONDITIONS

ANALOG PERFORMANCE SPECIFICATIONS

CRYSTAL OSCILLATOR SPECIFICATIONS

DIGITAL INPUT/OUTPUT SPECIFICATIONS

POWER SUPPLY SPECIFICATIONS

DIGITAL FILTERS

TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS