ANALOG DEVICES AD1933 Service Manual

8-Channel DAC with PLL and

T

Data Sheet

FEATURES

PLL generated or direct master clock Low EMI design DAC with 110 dB dynamic range and SNR

−96 dB THD + N

3.3 V single supply Tolerance for 5 V logic inputs Supports 24 bits and 8 kHz to 192 kHz sample rates Differential DAC output Log volume control with autoramp function SPI® controllable for flexibility Software-controllable clickless mute Software power-down Right-justified, left-justified, I Master and slave modes up to 16-channel input/output 64-lead LQFP Qualified for automotive applications

APPLICATIONS

Automotive audio systems Home Theater Systems Set-top boxes Digital audio effects processors

2

S, and TDM modes

Differential Outputs, 192 kHz, 24 Bits

AD1933

GENERAL DESCRIPTION

The AD1933 is a high performance, single chip that provides eight digital-to-analog converters (DACs) with differential output using the Analog Devices, Inc., patented multibit sigmadelta (Σ-Δ) architecture. An SPI port is included, allowing a microcontroller to adjust volume and many other parameters. The AD1933 operates from 3.3 V digital and analog supplies. The AD1933 is available in a 64-lead (differential output) LQFP. Other members of this family include a single-ended DAC output version.

The AD1933 is designed for low EMI. This consideration is apparent in both the system and circuit design architectures. By using the on-board PLL to derive the master clock from the LR clock or from an external crystal, the AD1933 eliminates the need for a separate high frequency master clock and can also be used with a suppressed bit clock. The DACs are designed using the latest Analog Devices continuous time architectures to further minimize EMI. By using 3.3 V supplies, power consumption is minimized, further reducing emissions.

FUNCTIONAL BLOCK DIAGRAM

AD1933

DIGITAL AUDIO INPUT/OUTPU

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

SERIAL

DATA PORT

PRECISION

VOLTAGE

REFERENCE

CLOCKS

SDATAIN

TIMING MANAGEMENT

AND CONTROL

(CLOCK AND PULL)

CONTROL PORT

SPI

CONTRO L DATA

INPUT/OUTPUT

DAC

DIGITAL

FILTER

AND

VOLUME

CONTROL

6.144MHz

Figure 1.

DAC

ANALOG AUDIO OUTPUTS

06624-001

AD1933 Data Sheet

REVISION HISTORY

10/11—Rev. C to Rev. D

Changes to Pin 14 in Figure 2 and Table 10.................................. 8

Changes to Ordering Guide.......................................................... 25

Added Automotive Products Section .......................................... 25

7/11—Rev. B to Rev. C

Deleted Reference to I Changes to Tabl e 10, DSDATAx/AUX DATA1 Pin

Descriptions ...................................................................................... 8

1/11—Rev. A to Rev. B

Changes to Features.......................................................................... 1

Ch a nge t o Ta b le Sum mar y, Ta bl e 2 a n d

Table Summary, Table 4................................................................... 4

Changes to Table Summary, Table 7 .............................................. 6

9/09—Rev. 0 to Rev. A

Change to Title.................................................................................. 1

Change to Table 10 ........................................................................... 9

Change to Power Supply and Voltage Reference Section.......... 13

Updated Outline Dimensions....................................................... 25

Changes to Ordering Guide.......................................................... 25

10/07—Revision 0: Initial Version

2

C............................................... Throughout

Rev. D | Page 2 of 28

Data Sheet AD1933

SPECIFICATIONS

TEST CONDITIONS

Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications.

Supply voltages (AVDD, DVDD) 3.3 V

Temp e rat u re r ang e

Master clock 12.288 MHz (48 kHz f

Input sample rate 48 kHz

Measurement bandwidth 20 Hz to 20 kHz

Word width 24 bits

Load capacitance (digital output) 20 pF

Load current (digital output) ±1 mA or 1.5 kΩ to ½ DVDD supply

Input voltage high 2.0 V

Input voltage low 0.8 V

1

Functionally guaranteed at −40°C to +125°C case temperature.

ANALOG PERFORMANCE SPECIFICATIONS

Specifications guaranteed at an ambient temperature of 25°C.

1

As specified in Tabl e 1 and Ta b le 2

, 256 × fS mode)

S

Table 1.

Parameter Test Conditions/Comments Min Typ Max Unit

DIGITAL-TO-ANALOG CONVERTERS

Dynamic Range 20 Hz to 20 kHz, −60 dB input

No Filter (RMS) 102 107 dB With A-Weighted Filter (RMS) 105 110 dB With A-Weighted Filter (Avg) 112 dB

Total Harmonic Distortion + Noise 0 dBFS

Differential Version Two channels running −96 dB

Eight channels running −86 −76 dB Full-Scale Output Voltage 1.76 (4.96) V rms (V p-p) Gain Error −10 +10 % Interchannel Gain Mismatch −0.2 +0.2 dB Offset Error −25 −6 +25 mV Gain Drift −30 +30 ppm/°C Interchannel Isolation 100 dB Interchannel Phase Deviation 0 Degrees Volume Control Step 0.375 dB Volume Control Range 95 dB De-emphasis Gain Error ±0.6 dB Output Resistance at Each Pin 100 Ω

REFERENCE

Internal Reference Voltage FILTR pin 1.50 V External Reference Voltage FILTR pin 1.32 1.50 1.68 V Common-Mode Reference Output CM pin 1.50 V

REGULATOR

Input Supply Voltage VSUPPLY pin 4.5 5.0 5.5 V Regulated Supply Voltage VSENSE pin 3.19 3.37 3.55 V

Rev. D | Page 3 of 28

AD1933 Data Sheet

Specifications measured at a case temperature of 125°C.

Table 2.

Parameter Test Conditions/Comments Min Typ Max Unit

DIGITAL-TO-ANALOG CONVERTERS

Dynamic Range 20 Hz to 20 kHz, −60 dB input

No Filter (RMS) 101 107 dB With A-Weighted Filter (RMS) 104 110 dB With A-Weighted Filter (Average) 112 dB

Total Harmonic Distortion + Noise 0 dBFS

Differential Version Two channels running −94 dB

Eight channels running −86 −70 dB Full-Scale Output Voltage 1.76 (4.96) V rms (V p-p) Gain Error −10 +10 % Interchannel Gain Mismatch −0.2 +0.2 dB Offset Error −25 −6 +25 mV Gain Drift −30 +30 ppm/°C

REFERENCE

Internal Reference Voltage FILTR pin 1.50 V External Reference Voltage FILTR pin 1.32 1.50 1.68 V Common-Mode Reference Output CM pin 1.50 V

REGULATOR

Input Supply Voltage VSUPPLY pin 4.5 5.0 5.5 V Regulated Supply Voltage VSENSE pin 3.2 3.43 3.65 V

CRYSTAL OSCILLATOR SPECIFICATIONS

Table 3.

Parameter Min Typ Max Unit

Transconductance 3.5 mmhos

DIGITAL INPUT/OUTPUT SPECIFICATIONS

−40°C < TC < +125°C, DVDD = 3.3 V ± 10%.

Table 4.

Parameter Test Conditions/Comments Min Typ Max Unit

High Level Input Voltage (VIH) 2.0 V High Level Input Voltage (VIH) MCLKI/XI pin 2.2 V Low Level Input Voltage (VIL) 0.8 V Input Leakage IIH @ VIH = 2.4 V 10 μA I High Level Output Voltage (VOH) IOH = 1 mA DVDD − 0.60 V Low Level Output Voltage (VOL) IOL = 1 mA 0.4 V Input Capacitance 5 pF

@ VIL = 0.8 V 10 μA

IL

Rev. D | Page 4 of 28

Data Sheet AD1933

POWER SUPPLY SPECIFICATIONS

Table 5.

Parameter Test Conditions/Comments Min Ty p Max Unit SUPPLIES

Voltage DVDD 3.0 3.3 3.6 V AVDD 3.0 3.3 3.6 V VSUPPLY 4.5 5.0 5.5 V Digital Current Master clock = 256 fS

Normal Operation fS = 48 kHz 56 mA f f Power-Down fS = 48 kHz to 192 kHz 2.0 mA

Analog Current

Normal Operation 74 mA Power-Down 23 mA

DISSIPATION

Operation Master clock = 256 fS, 48 kHz

All Supplies 429 mW Digital Supply 185 mW Analog Supply 244 mW

Power-Down, All Supplies 83 mW

POWER SUPPLY REJECTION RATIO

Signal at Analog Supply Pins 1 kHz, 200 mV p-p 50 dB 20 kHz, 200 mV p-p 50 dB

= 96 kHz 65 mA

S

= 192 kHz 95 mA

S

DIGITAL FILTERS

Table 6.

Parameter Mode Factor Min Typ Max Unit

DAC INTERPOLATION FILTER

Pass Band 48 kHz mode, typical @ 48 kHz 0.4535 fS 22 kHz 96 kHz mode, typical @ 96 kHz 0.3646 fS 35 kHz 192 kHz mode, typical @ 192 kHz 0.3646 fS 70 kHz Pass-Band Ripple 48 kHz mode, typical @ 48 kHz ±0.01 dB 96 kHz mode, typical @ 96 kHz ±0.05 dB 192 kHz mode, typical @ 192 kHz ±0.1 dB Transition Band 48 kHz mode, typical @ 48 kHz 0.5 fS 24 kHz 96 kHz mode, typical @ 96 kHz 0.5 fS 48 kHz 192 kHz mode, typical @ 192 kHz 0.5 fS 96 kHz Stop Band 48 kHz mode, typical @ 48 kHz 0.5465 fS 26 kHz 96 kHz mode, typical @ 96 kHz 0.6354 fS 61 kHz 192 kHz mode, typical @ 192 kHz 0.6354 fS 122 kHz Stop-Band Attenuation 48 kHz mode, typical @ 48 kHz 70 dB 96 kHz mode, typical @ 96 kHz 70 dB 192 kHz mode, typical @ 192 kHz 70 dB

Group Delay 48 kHz mode, typical @ 48 kHz 25/fS 521 μs 96 kHz mode, typical @ 96 kHz 11/fS 115 μs 192 kHz mode, typical @ 192 kHz 8/fS 42 μs

Rev. D | Page 5 of 28

AD1933 Data Sheet

TIMING SPECIFICATIONS

−40°C < TC < +125°C, DVDD = 3.3 V ± 10%.

Table 7.

Parameter Condition Comments Min Max Unit

INPUT MASTER CLOCK (MCLK) AND RESET

tMH MCLK duty cycle

tMH

f

MCLK frequency PLL mode, 256 fS reference 6.9 13.8 MHz

MCLK

f

Direct 512 fS mode 27.6 MHz

MCLK

t

PDR

t

PDRR

PLL

Lock Time MCLK and LR clock input 10 ms 256 fS VCO Clock, Output Duty Cycle

MCLKO/XO Pin

SPI PORT See Figure 9

t

CCLK high 35 ns

CCH

t

CCLK low 35 ns

CCL

f

CCLK frequency f

CCLK

t

CIN setup To CCLK rising 10 ns

CDS

t

CIN hold From CCLK rising 10 ns

CDH

t

CLS

t

CLH

t

CLHIGH

t

COUT enable From CCLK falling 30 ns

COE

t

COUT delay From CCLK falling 30 ns

COD

t

COUT hold From CCLK falling, not shown in Figure 9 30 ns

COH

t

COUT tristate From CCLK falling 30 ns

COTS

DAC SERIAL PORT See Figure 16

t

DBCLK high Slave mode 10 ns

DBH

t

DBCLK low Slave mode 10 ns

DBL

t

DLRCLK setup To DBCLK rising, slave mode 10 ns

DLS

t

DLRCLK hold From DBCLK rising, slave mode 5 ns

DLH

t

DLRCLK skew From DBCLK falling, master mode −8 +8 ns

DLS

t

DSDATA setup To DBCLK rising 10 ns

DDS

t

DSDATA hold From DBCLK rising 5 ns

DDH

AUXTDM SERIAL PORT See Figure 17

t

AUXTDMBCLK high Slave mode 10 ns

ABH

t

AUXTDMBCLK low Slave mode 10 ns

ABL

t

AUXTDMLRCLK setup To AUXTDMBCLK rising, slave mode 10 ns

ALS

t

AUXTDMLRCLK hold From AUXTDMBCLK rising, slave mode 5 ns

ALH

t

AUXTDMLRCLK skew From AUXTDMBCLK falling, master mode −8 +8 ns

ALS

t

DSDATA setup To AUXTDMBCLK, not shown in Figure 17 10 ns

DDS

t

DSDATA hold From AUXTDMBCLK rising, not shown in Figure 17 5 ns

DDH

AUXILIARY INTERFACE

t

AUXDATA delay From AUXBCLK falling 18 ns

DXDD

t

AUXBCLK high 10 ns

XBH

t

AUXBCLK low 10 ns

XBL

t

AUXLRCLK setup To AUXBCLK rising 10 ns

DLS

t

AUXLRCLK hold From AUXBCLK rising 5 ns

DLH

DAC clock source = PLL clock @ 256 f

, and 768 fS

512 f

S

DAC clock source = direct MCLK @ 512 f

, 384 fS,

S

40 60 %

(bypass on-chip PLL)

low

RST

recovery

RST

15 ns Reset to active output 4096 t

MCLK

40 60 %

= 1/t

CLATCH CLATCH CLATCH

setup hold high

CCLK

CCP

, only t

To CCLK rising 10 ns From CCLK falling 10 ns Not shown in Figure 9 10 ns

shown in Figure 9 10 MHz

CCP

Rev. D | Page 6 of 28

Data Sheet AD1933

ABSOLUTE MAXIMUM RATINGS

Table 8.

Parameter Rating

Analog (AVDD) −0.3 V to +3.6 V Digital (DVDD) −0.3 V to +3.6 V VSUPPLY −0.3 V to +6.0 V Input Current (Except Supply Pins) ±20 mA Analog Input Voltage (Signal Pins) −0.3 V to AVDD + 0.3 V Digital Input Voltage (Signal Pins) −0.3 V to DVDD + 0.3 V Operating Temperature Range (Case) −40°C to +125°C Storage Temperature Range −65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

θJA represents thermal resistance, junction-to-ambient;

represents thermal resistance, junction-to-case. All

θ

JC

characteristics are for a 4-layer board.

Table 9. Thermal Resistance

Package Type θJA θ

64-Lead LQFP 47 11.1 °C/W

Unit

JC

ESD CAUTION

Rev. D | Page 7 of 28

AD1933 Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

AGND

AVDD

OL3P

OL3N

OR3P

OR3N

OL4P

OL4N

OR4P

OR4N

RST

DGND

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

MCLKI/XI

MCLKO/XO

DSDATA4

NC = NO CONNECT

NC64NC63AVDD62LF61NC60NC59NC58NC57NC56NC55NC54NC53CM52AVDD51NC50NC

AD1933

TOP VIEW

(Not to Scale)

DIFFERENT IAL

OUTPUT

17

DVDD

20

DSDATA318DSDATA219DSDATA1

21

22

23

24

25

26NC27

28

29

30

CIN

DBCLK

DLRCLK

VDRIVE

VSENSE

VSUPPLY

AUXDATA1

AUXTDMBCLK

COUT31DVDD

AUXTDMLRCLK

Figure 2. Pin Configuration

49

48

AGND

47

FILTR

46

AGND

45

AVDD

44

AGND

43

OR2N

42

OR2P

41

OL2N

40

OL2P

39

OR1N

38

OR1P

37

OL1N

36

OL1P

35

CLATCH

34

CCLK

33

DGND

32

06624-002

Table 10. Pin Function Descriptions

Pin No. Input/Output Mnemonic Description

1 I AGND Analog Ground. 2 I MCLKI/XI Master Clock Input/Crystal Oscillator Input. 3 O MCLKO/XO Master Clock Output/Crystal Oscillator Output. 4 I AGND Analog Ground. 5 I AVDD Analog Power Supply. Connect to analog 3.3 V supply. 6 O OL3P DAC 3 Left Positive Output. 7 O OL3N DAC 3 Left Negative Output. 8 O OR3P DAC 3 Right Positive Output. 9 O OR3N DAC 3 Right Negative Output. 10 O OL4P DAC 4 Left Positive Output. 11 O OL4N DAC 4 Left Negative Output. 12 O OR4P DAC 4 Right Positive Output. 13 O OR4N DAC 4 Right Negative Output. 14 I

RST

15 I/O DSDATA4

Reset (Active Low). DACSerial Data Input 4. Input to DAC4 data in/TDM DAC2 data out (dual-line mode)/AUX

DAC2 data out (to external DAC2). 16 I DGND Digital Ground. 17 I DVDD Digital Power Supply. Connect to digital 3.3 V supply. 18 I/O DSDATA3

DAC Serial Data Input 3. Data input to DAC3 in/TDM DAC2 data in (dual-line mode)/AUX

not used. 19 I/O DSDATA2 DAC Serial Data Input 2. Data input to DAC2 data in/TDM DAC data out/AUX not used. 20 I DSDATA1 DAC Serial Data Input 1. Data input to DAC1 data in/TDM DAC data in/AUX TDM data in. 21 I/O DBCLK Bit Clock for DACs. Regular stereo, TDM, or daisy-chain TDM mode. 22 I/O DLRCLK LR Clock for DACs. Regular stereo, TDM, or daisy-chain TDM mode.

Rev. D | Page 8 of 28

Data Sheet AD1933

Pin No. Input/Output Mnemonic Description

23 I VSUPPLY 5 V Input to Regulator, Emitter of Pass Transistor. 24 I VSENSE 3.3 V Output of Regulator, Collector of Pass Transistor. 25 O VDRIVE Drive for Base of Pass Transistor. 26 O AUXDATA1 AUX DAC1 data out (to external DAC1). 27, 49, 50,

63, 64 28 I/O AUXTDMBCLK Auxiliary Mode Only DAC TDM Bit Clock. 29 I/O AUXTDMLRCLK Auxiliary Mode Only DAC LR TDM Clock. 30 I CIN Control Data Input (SPI). 31 I/O COUT Control Data Output (SPI). 32 I DVDD Digital Power Supply. Connect to digital 3.3 V supply. 33 I DGND Digital Ground. 34 I CCLK Control Clock Input (SPI). 35 I

36 O OL1P DAC 1 Left Positive Output. 37 O OL1N DAC 1 Left Negative Output. 38 O OR1P DAC 1 Right Positive Output. 39 O OR1N DAC 1 Right Negative Output. 40 O OL2P DAC 2 Left Positive Output. 41 O OL2N DAC 2 Left Negative Output. 42 O OR2P DAC 2 Right Positive Output. 43 O OR2N DAC 2 Right Negative Output. 44 I AGND Analog Ground. 45 I AVDD Analog Power Supply. Connect to analog 3.3 V supply. 46 I AGND Analog Ground. 47 O FILTR Voltage Reference Filter Capacitor Connection. Bypass with 10 μF||100 nF to AGND. 48 I AGND Analog Ground. 51 I AVDD Analog Power Supply. Connect to analog 3.3 V supply. 52 O CM

53 to 60 I NC Must Be Tied to Common Mode, Pin 52. Alternately, ac-couple these pins to ground. 61 O LF PLL Loop Filter, Return to AVDD. 62 I AVDD Analog Power Supply. Connect to analog 3.3 V supply.

NC No Connect.

CLATCH

Latch Input for Control Data (SPI).

Common-Mode Reference Filter Capacitor Connection. Bypass with 47 μF||100 nF to AGND.

Rev. D | Page 9 of 28

ANALOG DEVICES AD1933 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TEST CONDITIONS

ANALOG PERFORMANCE SPECIFICATIONS

CRYSTAL OSCILLATOR SPECIFICATIONS

DIGITAL INPUT/OUTPUT SPECIFICATIONS

DIGITAL FILTERS

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS