Analog Devices AD1865R-J, AD1865R, AD1865N-J Datasheet
Complete Dual 18-Bit
a
FEATURES
Dual Serial Input, Voltage Output DACs
No External Components Required
110 dB SNR
0.003% THD+N
Operates at 16 ⴛ Oversampling per Channel
ⴞ5 Volt Operation
Cophased Outputs
116 dB Channel Separation
Pin Compatible with AD1864
DIP or SOIC Packaging
APPLICATIONS
Multichannel Audio Applications
Compact Disc Players
Multivoice Keyboard Instruments
DAT Players and Recorders
Digital Mixing Consoles
Multimedia Workstations
PRODUCT DESCRIPTION
The AD1865 is a complete, dual 18-bit DAC offering excellent
THD+N and SNR while requiring no external components. Two
complete signal channels are included. This results in cophased
voltage or current output signals and eliminates the need for
output demultiplexing circuitry. The monolithic AD1865 chip
includes CMOS logic elements, bipolar and MOS linear elements and laser-trimmed thin-film resistor elements, all fabricated on Analog Devices’ ABCMOS process.
The DACs on the AD1865 chip employ a partially segmented
architecture. The first four MSBs of each DAC are segmented
into 15 elements. The 14 LSBs are produced using standard R-2R
techniques. Segment and R-2R resistors are laser trimmed to provide extremely low total harmonic distortion. This architecture
minimizes errors at major code transitions resulting in low output glitch and eliminating the need for an external deglitcher.
When used in the current output mode, the AD1865 provides
two ±1 mA output signals.
Each channel is equipped with a high performance output amplifier. These amplifiers achieve fast settling and high slew rate,
producing ±3 V signals at load currents up to 8 mA. Each out-
put amplifier is short-circuit protected and can withstand indefinite short circuits to ground.
The AD1865 was designed to balance two sets of opposing requirements, channel separation and DAC matching. High channel separation is the result of careful layout. At the same time,
both channels of the AD1865 have been designed to ensure
matched gain and linearity as well as tracking over time and
temperature. This assures optimum performance when used in
stereo and multi-DAC per channel applications.
*Protected by U.S. Patents Nos.: RE 30,586; 3,961,326; 4,141,004;
4,349,811; 4,855,618; 4,857,862.
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Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
16 ⴛ FS Audio DAC
AD1865*
FUNCTIONAL BLOCK DIAGRAM
(DIP Package)
–V
S
TRIM
MSB
I
OUT
AGND
SJ
R
V
OUT
+V
DR
LR
CLK
1
2
REFERENCE
3
4
5
6
7
F
8
9
L
10
18-BIT
LATCH
11
12
AD1865
REFERENCE
18-BIT
18-BIT
D/A
D/A
NC = NO CONNECT
LATCH
A versatile digital interface allows the AD1865 to be directly
connected to standard digital filter chips. This interface employs
five signals: Data Left (DL), Data Right (DR), Latch Left (LL),
Latch Right (LR) and Clock (CLK). DL and DR are the serial
input pins for the left and right DAC input registers. Input data
bits are clocked into the input register on the rising edge of
CLK. A low-going latch edge updates the respective DAC output. For systems using only a single latch signal, LL and LR
may be connected together. For systems using only one DATA
signal, DR and DL may be connected together.
The AD1865 operates with ±5 V power supplies. The digital
supply, V
–V
S
, can be separated from the analog supplies, VS and
L
, for reduced digital feedthrough. Separate analog and digital
ground pins are also provided. The AD1865 typically dissipates
only 225 mW, with a maximum power dissipation of 260 mW.
The AD1865 is packaged in both a 24-pin plastic DIP and a
28-pin SOIC package. Operation is guaranteed over the temper-
ature range of –25°C to +70°C and over the voltage supply
range of ±4.75 V to ±5.25 V.
PRODUCT HIGHLIGHTS
11. The AD1865 is a complete dual 18-bit audio DAC.
12. 110 dB signal-to-noise ratio for low noise operation.
13. THD+N is typically 0.003%.
14. Interchannel gain and midscale matching.
15. Output voltages and currents are cophased.
16. Low glitch for improved sound quality.
17. Both channels are 100% tested at 16 × F
18. Low Power—only 225 mW typ, 260 mW max.
19. Five-wire interface for individual DAC control.
10. 24-pin DIP or 28-pin SOIC packages available.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703
18-BIT
24
+V
S
TRIM
23
MSB
22
I
21
OUT
AGND
20
SJ
19
R
18
F
V
17
OUT
16
NC
DL
15
14
LL
13
DGND
.
S
(TA = +25ⴗC, +VL = +VS = +5 V and –VS = –5 V, FS = 705.6 kHz, no MSB adjustment
AD1865–SPECIFICATIONS
or deglitcher)
Parameter Min Typ Max Unit
RESOLUTION 18 Bits
DIGITAL INPUTS V
IH
V
IL
I
, VIH = +V
IH
I
, V
IL
L
= 0.4 V –10 µA
IL
2.0 +V
0.8 V
1.0 µA
L
V
Clock Input Frequency 13.5 MHz
ACCURACY
Gain Error 0.2 1.0 % of FSR
Interchannel Gain Matching 0.3 0.8 % of FSR
Midscale Error 4 mV
Interchannel Midscale Matching 5 mV
Gain Linearity (0 dB to –90 dB) <2 dB
DRIFT (0°C to +70°C)
Gain Drift ±25 ppm of FSR/°C
Midscale Drift ±4 ppm of FSR/°C
TOTAL HARMONIC DISTORTION + NOISE*
0 dB, 990.5 Hz AD1865N, R 0.004 0.006 %
AD1865N-J, R-J 0.003 0.004 %
20 dB, 990.5 Hz AD1865N, R 0.010 0.040 %
AD1865N-J, R-J 0.010 0.020 %
–60 dB, 990.5 Hz AD1865N, R 1.0 4.0 %
AD1865N-J, R-J 1.0 2.0 %
CHANNEL SEPARATION*
0 dB, 990.5 Hz 110 116 dB
SIGNAL-TO-NOISE RATIO* (20 Hz to 30 kHz) 107 110 dB
D-RANGE* (With A-Weight Filter)
–60 dB, 990.5 Hz AD1865N, R 88 100 dB
AD1865N-J, R-J 94 100 dB
OUTPUT
Voltage Output Configuration
Output Range (±1%) ⴞ2.94 ±3.0 ⴞ3.06 V
Output Impedance 0.1 Ω
Load Current ±8mA
Short Circuit Duration Indefinite to Common
Current Output Configuration
Bipolar Output Range (±30%) ±1mA
Output Impedance (±30%) 1.7 kΩ
POWER SUPPLY
and +V
+V
L
–V
S
+I, +V
S
and +VS = +5 V 22 26 mA
L
4.75 5.0 5.25 V
–5.25 –5.0 –4.75 V
–I, –VS = –5 V –23 –26 mA
POWER DISSIPATION, +VL = +VS = +5 V, –VS = –5 V 225 260 mW
TEMPERATURE RANGE
Specification 0 +25 +70 °C
Operation –25 +70 °C
Storage –60 +100 °C
WARMUP TIME 1 min
Specifications shown in boldface are tested on production units at final test without optional MSB adjustment.
*Tested in accordance with EIAJ Test Standard CP-307 with 18-bit data.
Specifications subject to change without notice.
–2–
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AD1865
WARNING!
ESD SENSITIVE DEVICE
14
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
13
TOP VIEW
(Not to Scale)
AD1865
+V
S
NC
TRIM
MSB
SJ
DL
LL
DGND
AGND
V
OUT
I
OUT
R
F
–V
S
I
OUT
+V
L
V
OUT
TRIM
MSB
LR
CLK
DR
AGND
SJ
R
F
LEFT
CHANNEL
RIGHT
CHANNEL
NC = NO CONNECT
ABSOLUTE MAXIMUM RATINGS*
VL to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 6.0 V
V
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 6.0 V
S
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . –6.0 V to 0 V
–V
S
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3 V
Digital Inputs to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 to V
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
L
Short Circuit Protection . . . . . . . . Indefinite Short to Ground
Soldering (10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1865 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
PINOUT
(24-Pin DIP Package)
Temperature Package
Model Range THD+N @ FS Option*
AD1865N –25°C to +70°C 0.006% N-24A
AD1865N-J –25°C to +70°C 0.004% N-24A
AD1865R –25°C to +70°C 0.006% R-28
AD1865R-J –25°C to +70°C 0.004% R-28
*N = Plastic DIP, R = Small Outline IC Package.
DIP SOIC
1122 –V
12 23 TRIM Right Channel Trim Network Connection
13 24 MSB Right Channel Trim Potentiometer
1426 I
15 28 AGND Analog Common Pin
16 11 SJ Right Channel Amplifier Summing Junction
17 12R
18 13V
19 14+V
10 15 DR Right Channel Data Input Pin
11 16 LR Right Channel Latch Pin
12 17 CLK Clock Input Pin
13 18 DGND Digital Common Pin
14 19 LL Left Channel Latch Pin
15 10 DL Left Channel Data Input Pin
16 11, 16, 18 NC No Internal Connection*
17 12 V
18 13 R
19 14 SJ Left Channel Amplifier Summing Junction
20 15 AGND Analog Common Pin
21 17 I
22 19 MSB Left Channel Trim Potentiometer
23 20 TRIM Left Channel Trim Network Connection
24 21 +V
*Pin 16 has no internal connection; –VL from AD1864 DIP socket can be safely
applied.
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25, 27
PIN DESIGNATIONS
Negative Analog Supply
S
Wiper Connection
Right Channel Output Current
OUT
Right Channel Feedback Resistor
F
Right Channel Output Voltage
OUT
Positive Digital Supply
L
Left Channel Output Voltage
OUT
Left Channel Feedback Resistor
F
OUT
S
Left Channel Output Current
Wiper Connection
Positive Analog Supply
–3–
(28-Pin SOIC Package)
V
OUT
+V
DR
CLK
DGND
NC
V
OUT
SJ
1
R
F
2
3
4
L
5
LR
6
7
8
LL
9
DL
10
11
12
R
13
F
SJ
14
AD1865
TOP VIEW
(Not to Scale)
NC = NO CONNECT
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AGND
NC
I
OUT
NC
MSB
TRIM
–V
S
+V
S
TRIM
MSB
NC
I
OUT
NC
AGND
AD1865
TOTAL HARMONIC DISTORTION + NOISE
Total harmonic distortion plus noise (THD+N) is defined as
the ratio of the square root of the sum of the squares of the amplitudes of the harmonics and noise to the value of the fundamental input frequency. It is usually expressed in percent.
THD+N is a measure of the magnitude and distribution of linearity error, differential linearity error, quantization error and
noise. The distribution of these errors may be different, depending on the amplitude of the output signal. Therefore, to be most
useful, THD+N should be specified for both large (0 dB) and
small (–20 dB, –60 dB) signal amplitudes. THD+N measurements for the AD1865 are made using the first 19 harmonics
and noise out to 30 kHz.
SIGNAL-TO-NOISE RATIO
The signal-to-noise ratio is defined as the ratio of the amplitude
of the output when a full-scale code is entered to the amplitude
of the output when a midscale code is entered. It is measured
using a standard A-Weight filter. SNR for the AD1865 is measured for noise components out to 30 kHz.
CHANNEL SEPARATION
Channel separation is defined as the ratio of the amplitude of a
full-scale signal appearing on one channel to the amplitude of
that same signal which couples onto the adjacent channel. It is
usually expressed in dB. For the AD1865 channel separation is
measured in accordance with EIAJ Standard CP-307, Section
5.5.
D-RANGE DISTORTION
D-Range distortion is equal to the value of the total harmonic
distortion + noise (THD+N) plus 60 dB when a signal level of
–60 dB below full scale is reproduced. D-Range is tested with a
1 kHz input sine wave. This is measured with a standard A-Weight
filter as specified by EIAJ Standard CP-307.
INTERCHANNEL MIDSCALE MATCHING
The midscale matching specification indicates how closely the
amplitudes of the output signals of the two channels match
when the twos complement input code representing half scale is
loaded into the input register of both channels. It is expressed in
mV and is measured with half-scale output signals.
FUNCTIONAL DESCRIPTION
The AD1865 is a complete, monolithic, dual 18-bit audio DAC.
No external components are required for operation. As shown in
the block diagram, each chip contains two voltage references,
two output amplifiers, two 18-bit serial input registers and two
18-bit DACs.
The voltage reference section provides a reference voltage for
each DAC circuit. These voltages are produced by low-noise
bandgap circuits. Buffer amplifiers are also included. This combination of elements produces reference voltages that are unaffected by changes in temperature and age.
The output amplifiers use both MOS and bipolar devices and
incorporate an all NPN output stage. This design technique
produces higher slew rate and lower distortion than previous
techniques. Frequency response is also improved. When combined with the appropriate on-chip feedback resistor, the output
op amps convert the output current to output voltages.
The 18-bit D/A converters use a combination of segmented decoder and R-2R architecture to achieve consistent linearity and
differential linearity. The resistors which form the ladder structure are fabricated with silicon chromium thin film. Laser trimming of these resistors further reduces linearity errors resulting
in low output distortion.
The input registers are fabricated with CMOS logic gates.
These gates allow the achievement of fast switching speeds and
low power consumption, contributing to the low glitch and low
power dissipation of the AD1865.
GAIN ERROR
The gain error specification indicates how closely the output of
a given channel matches the ideal output for given input data. It
is expressed in % of FSR and is measured with a full-scale output signal.
INTERCHANNEL GAIN MATCHING
The gain matching specification indicates how closely the amplitudes of the output signals match when producing identical input data. It is expressed in % of FSR (Full-Scale Range = 6 V
for the AD1865) and is measured with full-scale output signals.
MIDSCALE ERROR
Midscale error is the deviation of the actual analog output of a
given channel from the ideal output (0 V) when the twos
complement input code representing half scale is loaded into the
input register of the DAC. It is expressed in mV and is measured with half-scale output signals.
–V
S
TRIM
MSB
I
OUT
AGND
SJ
R
V
OUT
+V
DR
LR
CLK
1
2
REFERENCE
3
4
5
6
7
F
8
9
L
10
18-BIT
LATCH
11
12
AD1865
REFERENCE
18-BIT
18-BIT
D/A
D/A
NC = NO CONNECT
AD1865 Block Diagram (DIP Package)
18-BIT
LATCH
24
+V
S
TRIM
23
MSB
22
I
21
OUT
AGND
20
SJ
19
R
18
F
V
17
OUT
16
NC
15
DL
14
LL
13
DGND
–4–
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