Analog Devices AD14060BF-4, AD14060LBF-4 Datasheet

Quad-SHARC
®
a
PERFORMANCE FEATURES
...
ADSP-21060 Core Processor ( 480 MFLOPS Peak, 320 MFLOPS Sustained 25 ns Instruction Rate, Single-Cycle
Instruction Execution–Each of Four Processors 16 Mbit Shared SRAM (Internal to SHARCs) 4 Gigawords Addressable Off-Module Memory Twelve 40 Mbyte/s Link Ports (Three per SHARC) Four 40 Mbit/s Independent Serial Ports (One from
Each SHARC) One 40 Mbit/s Common Serial Port 5 V and 3.3 V Operation 32-Bit Single Precision and 40-Bit Extended
Precision IEEE Floating Point Data Formats, or
32-Bit Fixed Point Data Format IEEE JTAG Standard 1149.1 Test Access Port and
On-Chip Emulation PACKAGING FEATURES
308-Lead Ceramic Quad Flatpack (CQFP)
2.05" (52 mm) Body Size Cavity Up or Down, Configurable Low Profile, 0.160" Height Hermetic 25 Mil (0.65 mm) Lead Pitch 29 Grams (typical)
= 0.368C/W
u
JC
34)
CPA SPORT 1 TDI
EBOOT,
AD14060/
AD14060L
EBOOT,
CPA SPORT 1
TDO
DSP Multiprocessor Family
AD14060/AD14060L

FUNCTIONAL BLOCK DIAGRAM

2,0
CS
TIMEXP
SHARC_A
(ID
LBOOT, BMS
EMU
CLKIN
EMU
CLKIN
LBOOT, BMS
SHARC_D
(ID
CS
TIMEXP
2-0
LINK 1
2-0
LINK 0
IRQ
LINK 1
LINK 3
LINK 4
FLAG
LINK 2
= 1)
2-0
RESET
RESET
= 4)
LINK 3
LINK 5
TDO
1
3
SPORT 0
TCK, TMS, TRST
FLAG
FLAG
SHARC BUS (
SBTS, HBR, HBG, REDY, BR
SPORT 0
LINK 4
ADDR
1
3
FLAG
FLAG
LINK 0
TCK, TMS, TRST
LINK 2 LINK 5
2,0
2-0
TDI
IRQ
FLAG
31-0
,
DATA
CS
LINK 0 LINK 2 LINK 5 TDI
47-0,
LINK 0 LINK 2 LINK 5 TDO
EBOOT,
MS
EBOOT,
LINK 1
TIMEXP
SHARC_B
(ID
2-0
LBOOT, BMS
EMU
CLKIN
RESET
,
RD, WR, PAGE, ADRCLK, SW, ACK,
3-0
, RPBA, DMAR
6-1
EMU
CLKIN
RESET
LBOOT, BMS
SHARC_C
(ID
2-0
CS
TIMEXP
LINK 1
LINK 3
= 2)
= 3)
LINK 3
2,0
2-0
IRQ
LINK 4
FLAG
SPORT 1
1
SPORT 0
TCK, TMS, TRST
FLAG
, DMAG
1.2
1
FLAG
SPORT 0
TCK, TMS, TRST
SPORT 1
2,0
2-0
LINK 4
IRQ
FLAG
CPA
FLAG3TDO
)
1.2
3
FLAG
CPA
TDI
GENERAL DESCRIPTION
The AD14060/AD14060L Quad-SHARC is the first in a family of high performance DSP multiprocessor modules. The core of the multiprocessor is the ADSP-21060 DSP microcomputer. The AD14060/AD14060L modules have the highest perfor­mance —density and lowest cost—performance ratios of any in their class. They are ideal for applications requiring higher levels of performance and/or functionality per unit area.
The AD14060/AD14060L takes advantage of the built-in multi­processing features of the ADSP-21060 to achieve 480 peak MFLOPS with a single chip type, in a single package. The on­chip SRAM of the DSPs provides 16 Mbits of on-module shared SRAM. The complete shared bus (48 data, 32 address) is also brought off-module for interfacing with expansion memory or other peripherals.
SHARC is a registered trademark of Analog Devices, Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
The ADSP-21060 link ports are interconnected to provide direct communication among the four SHARCs as well as high speed off-module access. Internally, each SHARC has a direct link port connection. Externally, each SHARC has a total of 120 Mbytes/s link port bandwidth.
Multiprocessor performance is enhanced with embedded power and ground planes, matched impedance interconnect, and opti­mized signal routing lengths and separation. The fully tested and ready-to-insert multiprocessor also significantly reduces board space.
AD14060/AD14060L
DETAILED DESCRIPTION Architectural Features
ADSP-21060 Core
The AD14060/AD14060L is based on the powerful ADSP-21060 (SHARC) DSP chip. The ADSP-21060 SHARC combines a high performance floating-point DSP core with integrated, on­chip system features including a 4 Mbit SRAM memory, host processor interface, DMA controller, serial ports, and both link port and parallel bus connectivity for glueless DSP multiprocess­ing, (see Figure 1). It is fabricated in a high speed, low power CMOS process, and has a 25 ns instruction cycle time. The arith­metic/ logic unit (ALU), multiplier and shifter all perform single­cycle instructions, and the three units are arranged in parallel, maximizing computational throughput.
The SHARC features an enhanced Harvard architecture in which the data memory (DM) bus transfers data, and the pro­gram memory (PM) bus transfers both instructions and data. There is also an on-chip instruction cache which selectively caches only those instructions whose fetches conflict with the PM bus data accesses. This combines with the separate program and data memory buses to enable three-bus operation for fetch­ing an instruction and two operands, all in a single cycle. The SHARC also contains a general purpose data register file, which is a 10-port, 32-register (16 primary, 16 secondary) file. Each SHARC’s core also implements two data address generators (DAGs), implementing circular data buffers in hardware. The DAGs contain sufficient registers to allow the creation of up to 32 circular buffers. The 48-bit instruction word accommodates a variety of parallel operations, for concise programming. For ex­ample, the ADSP-21060 can conditionally execute a multiply, an add, a subtract, and a branch, all in a single instruction.
The SHARCs contain 4 Mbits of on-chip SRAM each, orga­nized as two blocks of 2 Mbits, which can be configured for different combinations of code and data storage. The memory can be configured as a maximum of 128K words of 32-bit data, 256K words of 16-bit data, 80K words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to 4 megabits. A 16-bit floating-point storage format is supported which effectively doubles the amount of data that may be stored on chip. Conversion between the 32-bit floating point and 16­bit floating point formats is done in a single instruction. Each memory block is dual-ported for single-cycle, independent accesses by the core processor and I/O processor or DMA con­troller. The dual-ported memory and separate on-chip buses allow two data transfers from the core and one from I/O, all in a single cycle.
Shared Memory Multiprocessing
The AD14060/AD14060L takes advantage of the powerful multiprocessing features built into the SHARC. The SHARCs are connected to maximize the performance of this cluster-of-four architecture, and still allow for off-module expansion. The AD14060/AD14060L in itself is a complete shared memory multiprocessing system, as shown in Figure 3. The unified ad­dress space of the SHARCs allows direct interprocessor ac­cesses of each SHARCs’ internal memory. In other words, each SHARC can directly access the internal memory and IOP registers of each of the other SHARCs by simply reading or writing to the appropriate address in multiprocessor memory space (see Figure
2)—this is called a direct read or direct write.
DAG1
8 x 4 x 32
BUS
CONNECT
(PX)
CORE PROCESSOR
TIMER
DAG2
8 x 4 x 24
DM ADDRESS BUS
PM DATA BUS
DM DATA BUS
DATA
REGISTER
FILE
16 x 40-BIT
BARREL SHIFTER
INSTRUCTION
CACHE
32 x 48-BIT
PROGRAM
SEQUENCER
24PM ADDRESS BUS
32
48
40/32
ALUMULTIPLIER
DUAL-PORTED SRAM
TWO INDEPENDENT
DUAL-PORTED BLOCKS
PROCESSOR PORT I/O PORT
ADDR DATA ADDR
ADDR DATA
DATA
IOP
REGISTERS
MEMORY MAPPED)
(
CONTROL,
STATUS, AND
DATA BUFFERS
DATA
IOD 48
I/O PROCESSOR
Figure 1. ADSP-21060 Processor Block Diagram (Core of the AD14060)
BLOCK 0
BLOCK 1
ADDR
IOA 17
DMA
CONTROLLER
SERIAL PORTS
(2)
LINK PORTS
(6)
JTAG
TEST AND
EMULATION
EXTERNAL
PORT
ADDR BUS
MUX
MULTIPROCESSOR
INTERFACE
DATA BUS
MUX
HOST PORT
4
6
6
36
7
32
48
–2–
REV. A
AD14060/AD14060L
INTERNAL
MEMORY
SPACE
(INDIVIDUAL
SHARCs)
MULTIPROCESSOR
MEMORY SPACE
IOP REGISTERS
NORMAL WORD ADDRESSING
SHORT WORD ADDRESSING
INTERNAL MEMORY SPACE
OF SHARC_A
ID=001
INTERNAL MEMORY SPACE
OF SHARC_B
INTERNAL
TO AD14060
EXTERNAL
TO AD14060
NORMAL WORD ADDRESSING: 32-BIT DATA WORDS 48-BIT INSTRUCTION WORDS
SHORT WORD ADDRESSING: 16-BIT DATA WORDS
INTERNAL MEMORY SPACE
INTERNAL MEMORY SPACE
INTERNAL MEMORY SPACE
INTERNAL MEMORY SPACE
ID=010
OF SHARC_C
ID=011
OF SHARC_D
ID=100
OF ADSP-2106x
WITH ID=101
OF ADSP-2106x
WITH ID=110
BROADCAST WRITE
TO ALL
ADSP-2106xs
0x0000 0000
0x0002 0000
0x0004 0000
0x0008 0000
0x0010 0000
0x0018 0000
0x0020 0000
0x0028 0000
0x0030 0000
0x0038 0000
0x003F FFFF
EXTERNAL
MEMORY
SPACE
BANK 0
DRAM
(OPTIONAL)
BANK 1
BANK 2
BANK 3
NONBANKED
0x0040 0000
MS
0
MS
1
MS
2
MS
3
BANK SIZE IS SELECTED BY MSIZE BIT FIELD OF SYSCON REGISTER.
0xFFFF FFFF
Figure 2. AD14060/AD14060L Memory Map
SYSTEM EXPANSION
1X CLOCK
CLKIN
RESET
RPBA
CPA
BOOTSELECT A BOOTSELECT BCD
DMAR1,2 DMAG1,2
SPORT0 FLAG1
JTAG
SHARC_A
LINKS 1, 3, & 4;
IRQ
FLAGS 2 & 0; TIMEXP, SPORT1
SHARC_D
LINKS 1, 3, & 4;
IRQ
FLAGS 2 & 0; TIMEXP, SPORT1
;
2-0
AD14060/AD14060L
(QUAD PROCESSOR
;
2-0
SHARC_B
LINKS 1, 3, & 4;
IRQ
FLAGS 2 & 0; TIMEXP, SPORT1
CLUSTER)
SHARC_C
LINKS 1, 3, & 4;
IRQ
FLAGS 2 & 0; TIMEXP, SPORT1
ADDR
31-0
;
2-0
;
2-0
DATA
ACK
MS
PAGE
SBTS
ADRCLK
HBR
HBG
REDY
BR
47-0
RD
WR
3-0
SW
CS
1-6
Figure 3. Complete Shared Memory Multiprocessing System
REV. A
–3–
AD14060/AD14060L
Bus arbitration is accomplished with the on-SHARC arbitration logic. Each SHARC has a unique ID, and drives the Bus-Request (BR) line corresponding to its ID, while monitoring all others. BR1–BR4 are used within the AD14060/AD14060L, while BR5 and BR6 can be used for expansion. All bus requests (BR1–BR6) are included in the module I/O.
Two different priority schemes, fixed and rotating, are available to resolve competing bus requests. The RPBA pin selects which scheme is used: when RPBA is high, rotating priority bus arbitra­tion is selected, and when RPBA is low, fixed priority is selected.
Table I. Rotating Priority Arbitration Example
Hardware Processor IDs
Cycle ID1 ID2 ID3 ID4 ID5 ID6
1M12 BR345Initial Priority Assignments 2 4 5 BR M-BR 1 2 3 3 4 5 BR M 1 2 3 4 5 BR M 1 2 3 4 BR 51 BR2345MFinal Priority Assignments
NOTES 1–5 = Assigned Priority. M = Bus Mastership (in that cycle). BR = Requesting Bus Mastership with BRx.
Bus mastership is passed from one SHARC to another during a bus transition cycle. A bus transition cycle only occurs when the current bus master deasserts its BR line and one of the slave SHARCs asserts its BR line. The bus master can therefore re­tain bus mastership by keeping its BR line asserted. When the bus master deasserts its BR line, and no other BR line is as­serted, then the master will not lose any bus cycles. When more than one SHARC asserts its BR line, the SHARC with the highest priority request becomes bus master on the following cycle. Each SHARC observes all of the BR lines, and therefore tracks when a bus transition cycle has occurred, and which processor has become the new bus master. Master processor changeover incurs only one cycle of overhead. An example bus transition sequence is shown in Table I.
Bus locking is possible, allowing indivisible read-modify-write sequences for semaphores. In either the fixed or rotating priority scheme, it is also possible to limit the number of cycles the master can control the bus. The AD14060/AD14060L also provides the option of using the Core Priority Access (CPA) mode of the SHARC. Using the CPA signal allows external bus accesses by the core processor of a slave SHARC to take priority over ongoing DMA transfers. Also, each SHARC can broadcast write to all other SHARCs simultaneously, allowing the imple­mentation of reflective semaphores.
The bus master can communicate with slave SHARCs by writ­ing messages to their internal IOP registers. The MSRG0– MSRG7 registers are general-purpose registers that can be used for convenient message passing, semaphores and resource shar­ing between the SHARCs. For message passing, the master communicates with a slave by writing and/or reading any of the eight message registers on the slave. For vector interrupts, the master can issue a vector interrupt to a slave by writing the address of an interrupt service routine to the slave’s VIRPT register. This causes an immediate high priority interrupt on the slave which, when serviced, will cause it to branch to the speci­fied service routine.
Off-Module Memory and Peripherals Interface
The AD14060/AD14060L’s external port provides the interface to
–4–
off-module memory and peripherals (see Figure 5). This port consists of the complete external port bus of the SHARC, bused together in common among the four SHARCs.
The 4-gigaword off-module address space is included in the ADSP-14060’s unified address space. Addressing of external memory devices is facilitated by each SHARC internally de­coding the high order address lines to generate memory bank select signals. Separate control lines are also generated for sim­plified addressing of page-mode DRAM. The AD14060/ AD14060L also supports programmable memory wait states and external memory acknowledge controls to allow interfacing to DRAM and peripherals with variable access, hold and disable time requirements.
Link Port I/O
Each individual SHARC features six 4-bit link ports that facili­tate SHARC-to-SHARC communication and external I/O inter­facing. Each link port can be configured for either 1× or 2× operation, allowing each to transfer either 4 or 8 bits per cycle. The link ports can operate independently and simultaneously, with a maximum bandwidth of 40 MBytes/s each, or a total of 240 MBytes/s per SHARC.
The AD14060/AD14060L optimizes the link port connections internally, and brings a total of twelve of the link ports off-mod­ule for user-defined system connections. Internally, each SHARC has a connection to the other three SHARCs with a dedicated link port interface. Thus, each SHARC can directly interface with its nearest and next-nearest neighbor. The remaining three link ports from each SHARC are brought out independently from each SHARC. A maximum of 480 MBytes/s link port bandwidth is then available off of the AD14060/AD14060L. The link port connections are detailed in Figure 4.
1
3
SHARC_A SHARC_B
4
0
0
1
3
SHARC_D SHARC_C
4
55
22
22
55
1
3
4
0
0
1
3
4
Figure 4. Link Port Connections
Link port 4, the boot link port, is brought off independently from each SHARC. Individual booting is then allowed, or chained link port booting is possible as described under “Link Port Booting.”
Link port data is packed into 32-bit or 48-bit words, and can be directly read by the SHARC core processor or DMA­transferred to on-SHARC memory.
Each link port has its own double-buffered input and output registers. Clock/acknowledge handshaking controls link port transfers. Transfers are programmable as either transmit or receive.
REV. A
1x
CLOCK
RESET
101
CLKIN
RESET
RPBA
CONTROL
SERIALS LINKS DISCRETES
ADSP-2106x #5
CLKIN
RESET
RPBA
3
ID
2–0
AD14060/
AD14060L
ADDR DATA
ADRCLK
(OPTIONAL)
ADDR DATA
31–0 47–0
ACK
MS
BMS
PAGE
SBTS
HBR
HBG
REDY
CPA
BR
BR
31–0 47–0
RD
WR
3–0
SW
CS
2–6
AD14060/AD14060L
ADDR
GLOBAL
DATA
MEMORY
OE WE
ACK
CS
CS
ADDR DATA
5
1
ADDR DATA
AND
PERIPHERALS
(OPTIONAL)
BOOT
EPROM
(OPTIONAL)
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
CONTROL
CPA
BR
BR
31–0 47–0
CPA
1–5
BR
5
5
5
6
110
ADSP-2106x #6
CLKIN
RESET
RPBA
3
ID
2–0
CONTROL
BR
1, 2, 3, 4, 6
(OPTIONAL)
ADDR DATA
Figure 5. Optional System Interconnections
REV. A
–5–
AD14060/AD14060L
Serial Ports
The SHARC serial ports provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices. Each SHARC has two serial ports. The AD14060/AD14060L provides direct access to Serial Port 1 of each SHARC. Serial Port 0 is bused together in common to each SHARC, and brought off-module.
The serial ports can operate at the full clock rate of the module, providing each with a maximum data rate of 40 Mbit/s. Inde­pendent transmit and receive functions provide more flexible communications. Serial port data can be automatically trans­ferred to and from on-SHARC memory via DMA, and each of the serial ports offers time division multiplexed (TDM) multi­channel mode.
The serial ports can operate with little-endian or big-endian transmission formats, with word lengths selectable from 3 bits to 32 bits. They offer selectable synchronization and transmit modes as well as optional µ-law or A-law companding. Serial port clocks and frame syncs can be internally or externally generated.
Program Booting
The AD14060/AD14060L supports automatic downloading of programs following power-up or a software reset. The SHARC offers four options for program booting: 1) from an 8-bit EPROM; 2) from a host processor; 3) through the link ports; and 4) no-boot. In no-boot mode, the SHARC starts executing instructions from address 0x0040 0004 in external memory. The boot mode is selected by the state of the following signals: BMS, EBOOT, and LBOOT.
On the AD14060/AD14060L, SHARC_A’s boot mode is sepa­rately controlled, while SHARCs B, C, and D are controlled as a group. With this flexibility, the AD14060/AD14060L can be configured to boot in any of the following methods.
Multiprocessor Host Booting
To boot multiple ADSP-21060 processors from a host, each ADSP-21060 must have its EBOOT, LBOOT and BMS pins configured for host booting: EBOOT = 0, LBOOT = 0, and BMS = 1. After system power-up, each ADSP-21060 will be in the idle state and the BRx bus request lines will be deasserted. The host must assert the HBR input and boot each ADSP-21060 by asserting its CS pin and downloading instructions.
Multiprocessor EPROM Booting
There are two methods of booting the multiprocessor system from an EPROM.
SHARC_A Is Booted, Which Then Boots the Others. The EBOOT pin on the SHARC_A must be set high for EPROM booting. All other ADSP-21060s should be configured for host booting (EBOOT = 0, LBOOT = 0, and BMS = 1), which leaves them in the idle state at start-up and allows SHARC_A to become bus master and boot itself. Only the BMS pin of SHARC_A is connected to the chip select of the EPROM. When SHARC_A has finished booting, it can boot the re­maining ADSP-21060s by writing to their external port DMA buffer 0 (EPB0) via multiprocessor memory space.
All ADSP-21060s Boot in Turn From a Single EPROM.
The BMS signals from each ADSP-21060 may be wire-ORed together to drive the chip select pin of the EPROM. Each ADSP-21060 can boot in turn, according to its priority. When the last one has finished booting, it must inform the others (which may be in the idle state) that program execution can begin.
Multiprocessor Link Port Booting
Booting can also be accomplished from a single source through the link ports. Link Buffer 4 must always be used for booting. To simultaneously boot all of the ADSP-21060s, a parallel common connection is available through Link Port 4 on each of the processors. Or, using the daisy chain connection that exists between the processors’ link ports, each ADSP-21060 can boot the next one in turn. In this case, the Link Assignment Register (LAR) must be programmed to configure the internal link ports with Link Buffer 4.
Multiprocessor Booting From External Memory
If external memory contains a program after reset, then SHARC_A should be set up for no boot mode; it will begin ex­ecuting from address 0x0040 0004 in external memory. When booting has completed, the other ADSP-21060s may be booted by SHARC_A if they are set up for host booting, or they can begin executing out of external memory if they are set up for no boot mode. Multiprocessor bus arbitration will allow this booting to occur in an orderly manner.
Host Processor Interface
The AD14060/AD14060L’s host interface allows for easy con­nection to standard microprocessor buses, both 16-bit and 32­bit, with little additional hardware required. Asynchronous transfers at speeds up to the full clock rate of the module are supported. The host interface is accessed through the AD14060/ AD14060L external port and is memory-mapped into the uni­fied address space. Four channels of DMA are available for the host interface; code and data transfers are accomplished with low software overhead.
The host processor requests the AD14060/AD14060L’s external bus with the host bus request (HBR), host bus grant (HBG), and ready (REDY) signals. The host can directly read and write the internal memory of the SHARCs, and can access the DMA channel setup and mailbox registers. Vector interrupt support is provided for efficient execution of host commands.
Direct Memory Access (DMA) Controller
The SHARCs on-chip DMA control logic allows zero-overhead data transfers without processor intervention. The DMA con­troller operates independently and invisibly to each SHARCs processor core, allowing DMA operations to occur while the core is simultaneously executing its program instructions.
DMA transfers can occur between SHARC internal memory and either external memory, external peripherals, or a host processor. DMA transfers can also occur between the SHARC’s internal memory and its serial ports or link ports. DMA trans­fers between external memory and external peripheral devices are another option. External bus packing to 16-, 32- or 48-bit words is performed during DMA transfers.
Ten channels of DMA are available on the SHARCs—two via the link ports, four via the serial ports, and four via the processor’s external port (for either host processor, other SHARCs, memory, or I/O transfers). Four additional link port DMA channels are shared with serial port 1 and the external port. Programs can be downloaded to the SHARCs using DMA transfers. Asynchronous off-module peripherals can control two DMA channels using DMA Request/Grant lines (DMAR1-2, DMAG1-2). Other DMA features include interrupt generation upon completion of DMA transfers and DMA chaining for automatic linked DMA transfers.
–6–
REV. A
AD14060/AD14060L
Development Tools
The ADSP-14060 is supported with a complete set of software and hardware development tools, including an EZ-LAB
®
In-
Circuit Emulator, and development software. Analog Devices’ ADSP-21000 Family Development Software
includes an easy to use Assembler based on an algebraic syntax, an Assembly Library/Librarian, a Linker, an Instruction-Level Simulator, an ANSI C optimizing Compiler, the CBug™ C Source-Level Debugger, and a C Runtime Library including DSP and mathematical functions. The Optimizing Compiler includes Numerical C extensions based on the work of the ANSI Numerical C Extensions Group. Numerical C provides exten­sions to the C language for array selection, vector math op­erations, complex data types, circular pointers and variably dimensioned arrays. The ADSP-21000 Family Development Software is available for both the PC and Sun platforms.
The SHARC EZ-KIT combines the ADSP-21000 Family De­velopment Software for the PC and the EZ-LAB Development Board in one package.
The ADSP-2106x EZ-ICE
®
Emulator uses the IEEE 1149.1 JTAG test access port of the ADSP-2106x processor to monitor and control the target board processor during emulation. The EZ-ICE provides full-speed emulation, allowing inspection and modification of memory, registers and processor stacks.
Nonintrusive in-circuit emulation is assured by the use of the processor’s JTAG interface—the emulator does not affect target system loading or timing.
Further details and ordering information are available in the
ADSP-21000 Family Hardware & Software Development Tools
data sheet (ADDS-2100xx-TOOLS). This data sheet can be requested from any Analog Devices sales office or distributor, or from the Literature Center.
In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools supporting the SHARC processor family. Hard­ware tools include SHARC PC plug-in cards, multiprocessor SHARC VME boards, and daughter card modules with multiple SHARCs and additional memory. These modules are based on the SHARCPAC module specification. Third party software tools include an Ada compiler, DSP libraries, operating systems and block diagram design tools.
Quad-SHARC Development Board
The BlackTip-MCM, AD14060 development board and soft­ware, is available from Bittware Research Systems, Inc. This board has one AD14060 BITSI interface, PROM and SRAM expansion options on an ISA card. It is supported by Bittware’s SHARC software development package. Bittware can be con­tacted at 1-800-848-0436.
Other Package Details
The AD14060/AD14060L contains 16 on-module 0.018 micro­farad bypass capacitors. It is recommended that in the target system at least four additional capacitors, of 0.018 microfarad value, be placed around the module—one near each of the four corners.
The top surface, lid, of the AD14060/AD14060L is electrically connected to GND on the industrial and military grade parts.
Additional Information
This data sheet provides a general overview of the AD14060/ AD14060L architecture and functionality. For detailed infor­mation on the ADSP-2106x SHARC and the ADSP-21000 Family core architecture and instruction set, refer to the ADSP­2106x SHARC User’s Manual.
EZ-ICE and EZ-LAB are registered trademarks of Analog Devices, Inc. CBug is a trademark of Analog Devices, Inc.
REV. A
–7–
AD14060/AD14060L
PIN FUNCTION DESCRIPTIONS
AD14060/AD14060L pin definitions are listed below. Inputs identified as synchronous (S) must meet timing requirements with respect to CLKIN (or with respect to TCK for TMS, TDI). Inputs identified as asynchronous (A) can be asserted asynchronously to CLKIN (or to TCK for TRST).
Unused inputs should be tied or pulled to V for ADDR
, DATA
31-0
, FLAG
47-0
, SW, and inputs that have
2-0
or GND, except
DD
TCLKx, RCLKx, LxDAT TDI)—these pins can be left floating. These pins have a logic­level hold circuit that prevents the input from floating internally.
I = Input P = Power Supply (A/D) = Active Drive O = Output S = Synchronous (O/D) = Open Drain G = Ground A = Asynchronous T = Three-State (when SBTS is asserted, or when the AD14060/ AD14060L is a bus slave)
, LxCLK, LxACK, TMS and
3-0
internal pull-up or pull-down resistors (CPA, ACK, DTx, DRx,
Pin Type Function
ADDR
31-0
I/O/T External Bus Address. (Common to all SHARCs) The AD14060/AD14060L outputs addresses for
external memory and peripherals on these pins. In a multiprocessor system, the bus master outputs addresses for read/writes on the internal memory or IOP registers of slave ADSP-2106xs. The AD14060/ AD14060L inputs addresses when a host processor or multiprocessing bus master is reading or writing the internal memory or IOP registers of internal ADSP-21060s.
DATA
47-0
I/O/T External Bus Data. (Common to all SHARCs) The AD14060/AD14060L inputs and outputs data and
instructions on these pins. 32-bit single-precision floating-point data and 32-bit fixed-point data is trans­ferred over bits 47-16 of the bus. 40-bit extended-precision floating-point data is transferred over bits 47­8 of the bus. 16-bit short word data is transferred over bits 31-16 of the bus. In PROM boot mode, 8-bit data is transferred over bits 23-16. Pull-up resistors on unused DATA pins are not necessary.
MS
3-0
O/T Memory Select Lines. (Common to all SHARCs) These lines are asserted (low) as chip selects for the
corresponding banks of external memory. Memory bank size must be defined in the individual ADSP­21060’s system control registers (SYSCON). The MS change at the same time as the other address lines. When no external memory access is occurring the MS
lines are decoded memory address lines that
3-0
3-0
lines are inactive; they are active, however, when a conditional memory access instruction is executed, whether or not the condition is true. MS (Bank 0). In a multiprocessing system, the MS
can be used with the PAGE signal to implement a bank of DRAM memory
0
lines are output by the bus master.
3-0
RD I/O/T Memory Read Strobe. (Common to all SHARCs) This pin is asserted (low) when the AD14060/
AD14060L reads from external devices or when the internal memory of internal ADSP-2106xs is being accessed. External devices (including other ADSP-2106xs) must assert RD to read from the AD14060/ AD14060L’s internal memory. In a multiprocessing system, RD is output by the bus master and is input by all other ADSP-2106xs.
WR I/O/T Memory Write Strobe. (Common to all SHARCs) This pin is asserted (low) when the AD14060/
AD14060L writes to external devices or when the internal memory of internal ADSP-2106xs is being ac­cessed. External devices (including other ADSP-2106xs) must assert WR to write to the AD14060/ AD14060L’s internal memory. In a multiprocessing system WR is output by the bus master and is input by all other ADSP-2106xs.
PAGE O/T DRAM Page Boundary. (Common to all SHARCs) The AD14060/AD14060L asserts this pin to signal
that an external DRAM page boundary has been crossed. DRAM page size must be defined in the indi­vidual ADSP-21060’s memory control register (WAIT). DRAM can only be implemented in external memory Bank 0; the PAGE signal can only be activated for Bank 0 accesses. In a multiprocessing system, PAGE is output by the bus master.
ADRCLK O/T Clock Output Reference. (Common to all SHARCs) In a multiprocessing system, ADRCLK is output
by the bus master.
SW I/O/T Synchronous Write Select. (Common to all SHARCs) This signal is used to interface the AD14060/
AD14060L to synchronous memory devices (including other ADSP-2106xs). The AD14060/AD14060L asserts SW (low) to provide an early indication of an impending write cycle, which can be aborted if WR is not later asserted (e.g., in a conditional write instruction). In a multiprocessing system, SW is output by the bus master and is input by all other ADSP-2106xs to determine if the multiprocessor memory access is a read or write. SW is asserted at the same time as the address output. A host processor using synchronous writes must assert this pin when writing to the AD14060/AD14060L.
ACK I/O/S Memory Acknowledge. (Common to all SHARCs) External devices can deassert ACK (low) to add
wait states to an external memory access. ACK is used by I/O devices, memory controllers, or other pe­ripherals to hold off completion of an external memory access. The AD14060/AD14060L deasserts ACK, as an output, to add wait states to a synchronous access of its internal memory. In a multiprocess­ing system, a slave ADSP-2106x deasserts the bus master’s ACK input to add wait state(s) to an access of its internal memory. The bus master has a keeper latch on its ACK pin that maintains the input at the level it was last driven to.
–8–
REV. A
AD14060/AD14060L
Pin Type Function
SBTS I/S Suspend Bus Three-State. (Common to all SHARCs) External devices can assert SBTS (low) to
place the external bus address, data, selects, and strobes in a high impedance state for the following cycle. If the AD14060/AD14060L attempts to access external memory while SBTS is asserted, the processor will halt and the memory access will not be completed until SBTS is deasserted. SBTS should only be used to recover from host processor/AD14060/AD14060L deadlock, or used with a DRAM controller.
HBR I/A Host Bus Request. (Common to all SHARCs) Must be asserted by a host processor to request control
of the AD14060/AD14060L’s external bus. When HBR is asserted in a multiprocessing system, the ADSP-2106x that is bus master will relinquish the bus and assert HBG. To relinquish the bus, the ADSP-2106x places the address, data, select, and strobe lines in a high impedance state. HBR has priority over all ADSP-2106x bus requests (BR
HBG I/O Host Bus Grant. (Common to all SHARCs) Acknowledges an HBR bus request, indicating that the
host processor may take control of the external bus. HBG is asserted (held low) by the AD14060/AD14060L until HBR is released. In a multiprocessing system, HBG is output by the ADSP-2106x bus master and is monitored by all others.
CSA I/A Chip Select. Asserted by host processor to select SHARC_A. CSB I/A Chip Select. Asserted by host processor to select SHARC_B. CSC I/A Chip Select. Asserted by host processor to select SHARC_C. CSD I/A Chip Select. Asserted by host processor to select SHARC_D.
REDY (O/D) O Host Bus Acknowledge. (Common to all SHARCs) The AD14060/AD14060L deasserts REDY (low)
to add wait states to an asynchronous access of its internal memory or IOP registers by a host. Open drain output (O/D) by default; can be programmed in ADREDY bit of SYSCON register of individual ADSP­21060s to be active drive (A/D). REDY will only be output if the CS and HBR inputs are asserted.
BR
6-1
I/O/S Multiprocessing Bus Requests. (Common to all SHARCs) Used by multiprocessing ADSP-2106xs to
arbitrate for bus mastership. An ADSP-2106x only drives its own BRx line (corresponding to the value of its ID2-0 inputs) and monitors all others. In a multiprocessor system with less than six ADSP-2106xs, the unused BRx pins should be pulled high; BR
RPBA I/S Rotating Priority Bus Arbitration Select. (Common to all SHARCs) When RPBA is high, rotating
priority for multiprocessor bus arbitration is selected. When RPBA is low, fixed priority is selected. This signal is a system configuration selection that must be set to the same value on every ADSP-2106x. If the value of RPBA is changed during system operation, it must be changed in the same CLKIN cycle on every ADSP-2106x.
CPAy (O/D) I/O Core Priority Access. (y = SHARC_A, B, C, D) Asserting its CPA pin allows the core processor of an
ADSP-2106x bus slave to interrupt background DMA transfers and gain access to the external bus. CPA is an open drain output that is connected to all ADSP-2106x in the system if this function is required. The CPA pin of each internal ADSP-21060 is brought out individually. The CPA pin has an internal 5 k pull-up resistor. If core access priority is not required in a system, the CPA pin should be left unconnected.
DT0 O/T Data Transmit (Common Serial Ports 0 to all SHARCs, TDM). DT pin has a 50 kΩ internal pull-up
resistor.
DR0 I Data Receive (Common Serial Ports 0 to all SHARCs, TDM). DR pin has a 50 k internal pull-up
resistor.
TCLK0 I/O Transmit Clock (Common Serial Ports 0 to all SHARCs, TDM). TCLK pin has a 50 kΩ internal
pull-up resistor.
RCLK0 I/O Receive Clock (Common Serial Ports 0 to all SHARCs, TDM). RCLK pin has a 50 kΩ internal pull-up
resistor. TFS0 I/O Transmit Frame Sync (Common Serial Ports 0 to all SHARCs, TDM). RFS0 I/O Receive Frame Sync (Common Serial Ports 0 to all SHARCs, TDM). DTy1 O/T Data Transmit (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) DT pin
has a 50 k internal pull-up resistor. DRy1 I Data Receive (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) DR pin
has a 50 k internal pull-up resistor.
) in a multiprocessing system.
6-1
must not be pulled high or low because they are outputs.
4-1
REV. A
–9–
AD14060/AD14060L
Pin Type Function
TCLKy1 I/O Transmit Clock (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) TCLK
pin has a 50 k internal pull-up resistor.
RCLKy1 I/O Receive Clock (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) RCLK
pin has a 50 k internal pull-up resistor. TFSy1 I/O Transmit Frame Sync (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) RFSy1 I/O Receive Frame Sync (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) FLAGy0 I/O/A Flag Pins. (FLAG0 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) Each is config-
ured via control bits as either an input or output. As an input, it can be tested as a condition. As an out-
put, it can be used to signal external peripherals. FLAG1 I/O/A Flag Pins. (FLAG1 common to all SHARCs) Configured via control bits internal to individual ADSP-
21060s as either an input or output. As an input, it can be tested as a condition. As an output, it can be
used to signal external peripherals. FLAGy2 I/O/A Flag Pins. (FLAG2 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) Each is config-
ured via control bits as either an input or output. As an input, it can be tested as a condition. As an out-
put, it can be used to signal external peripherals. IRQy2-0 I/A Interrupt Request Lines. (Individual IRQ2-0 from y = SHARC_A, SHARC_B, SHARC_C, SHARC_D)
May be either edge-triggered or level-sensitive.
DMAR1 I/A DMA Request 1 (DMA Channel 7). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D. DMAR2 I/A DMA Request 2 (DMA Channel 8). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D. DMAG1 O/T DMA Grant 1 (DMA Channel 7). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D. DMAG2 O/T DMA Grant 2 (DMA Channel 8). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D.
LyxCLK I/O Link Port Clock (y = SHARC_A, B, C, D; x = Link Ports 1, 3, 4)
internal pull-down resistor which is enabled or disabled by the LPDRD bit of the LCOM register, of the
ADSP-20160. LyxDAT3-0 I/O Link Port Data (y = SHARC_A, B, C, D; x = Link Ports 1, 3, 4)
50 k internal pull-down resistor which is enabled or disabled by the LPDRD bit of the LCOM register,
of the ADSP-21060. LyxACK I/O Link Port Acknowledge (y = SHARC_A, B, C, D; x = Link Ports 1, 3, 4)
50 k internal pull-down resistor which is enabled or disabled by the LPDRD bit of the LCOM register,
of the ADSP-21060. EBOOTA I EPROM Boot Select. (SHARC_A) When EBOOTA is high, SHARC_A is configured for booting from
an 8-bit EPROM. When EBOOTA is low, the LBOOTA and BMSA inputs determine booting mode
for SHARC_A. See the following table. This signal is a system configuration selection which should
be hardwired. LBOOTA I Link Boot. When LBOOTA is high, SHARC_A is configured for link port booting. When LBOOTA is
low, SHARC_A is configured for host processor booting or no booting. See the following table. This
signal is a system configuration selection which should be hardwired. BMSA I/O/T
2
Boot Memory Select. Output: Used as chip select for boot EPROM devices (when EBOOTA = 1,
LBOOTA = 0). In a multiprocessor system, BMS is output by the bus master. Input: When low, indicates
that no booting will occur and that SHARC_A will begin executing instructions from external memory.
See the following table. This input is a system configuration selection which should be hardwired. EBOOTBCD I EPROM Boot Select. (Common to SHARC_B, SHARC_C, SHARC_D) When EBOOTBCD is high,
SHARC_B, C, D are configured for booting from an 8-bit EPROM. When EBOOTBCD is low, the
LBOOTBCD and BMSBCD inputs determine booting mode for SHARC_B, C and D. See the following
table. This signal is a system configuration selection which should be hardwired. LBOOTBCD I LINK Boot. (Common to SHARC_B, SHARC_C, SHARC_D) When LBOOTBCD is high, SHARC_B, C,
D are configured for link port booting. When LBOOTBCD is low, SHARC_B, C, D are configured for
host processor booting or no booting. See the following table. This signal is a system configuration selec-
tion which should be hardwired.
1
. Each LyxCLK pin has a 50 k
1
. Each LyxDAT pin has a
1
. Each LyxACK pin has a
–10–
REV. A
AD14060/AD14060L
Pin Type Function
2
BMSBCD I/O/T
TIMEXPy O Timer Expired. (Individual TIMEXP from y = SHARC_A, SHARC_B, SHARC_C, SHARC_D) Asserted
CLKIN I Clock In. (Common to all SHARCs) External clock input to the AD14060/AD14060L. The instruction
RESET I/A Module Reset. (Common to all SHARCs) Resets the AD14060/AD14060L to a known state. This input
TCK I Test Clock (JTAG). (Common to all SHARCs) Provides an asynchronous clock for JTAG boundary
TMS I/S Test Mode Select (JTAG). (Common to all SHARCs) Used to control the test state machine. TMS has
TDI I/S Test Data Input (JTAG). Provides serial data for the boundary scan logic chain starting at SHARC_A.
TDO O Test Data Output (JTAG). Serial scan output of the boundary scan chain path, from SHARC_D.
TRST I/A Test Reset (JTAG). (Common to all SHARCs) Resets the test state machine. TRST must be asserted
EMU (O/D) O Emulation Status. (Common to all SHARCs) Must be connected to the ADSP-2106x EZ-ICE target
V
DD
P Power Supply. Nominally +5.0 V dc for 5 V devices or +3.3 V dc for 3.3 V devices (26 pins).
GND G Power Supply Return. (28 pins).
NOTES FLAG3 is connected internally, common to SHARC_A, B, C, and D. ID pins are hardwired internally as depicted in the block diagram.
1
LINK PORTS 0, 2 and 5 are connected internally as described earlier in Link Port I/O.
2
Three-statable only in EPROM boot mode (when BMS is an output).
Boot Memory Select. Output: Used as chip select for boot EPROM devices (when EBOOTBCD = 1, LBOOTBCD = 0). In a multiprocessor system, BMS is output by the bus master. Input: When low, indicates that no booting will occur and that SHARC_B, C, D will begin executing instructions from external memory. See table below. This input is a system configuration selection which should be hardwired.
EBOOT LBOOT BMS Booting Mode 1 0 Output EPROM (Connect BMS to EPROM chip select)
0 0 1 (Input) Host Processor 0 1 1 (Input) Link Port 0 0 0 (Input) No Booting. Processor executes from external memory. 0 1 0 (Input) Reserved 1 1 x (Input) Reserved
for four cycles when the timer is enabled and TCOUNT decrements to zero.
cycle rate is equal to CLKIN. CLKIN may not be halted, changed, or operated below the minimum specified frequency.
must be asserted (low) at power-up.
scan.
a 20 k internal pull-up resistor.
TDI has a 20 k internal pull-up resistor.
(pulsed low) after power-up or held low for proper operation of the AD14060/AD14060L. TRST has a 20 k internal pull-up resistor.
board connector only.
REV. A
–11–
AD14060/AD14060L

TARGET BOARD CONNECTOR FOR EZ-ICE PROBE

The ADSP-2106x EZ-ICE Emulator uses the IEEE 1149.1 JTAG test access port of the ADSP-2106x to monitor and control the target board processor during emulation. The EZ-ICE probe requires that the AD14060/AD14060L’s CLKIN (optional), TMS, TCK, TRST, TDI, TDO, EMU and GND signals be made accessible on the target system via a 14-pin connector (a pin strip header) such as that shown in Figure 6. The EZ-ICE probe plugs directly onto this connector for chip-on-board emu­lation. You must add this connector to your target board design if you intend to use the ADSP-2106x EZ-ICE. The length of the traces between the connector and the AD14060/ AD14060L’s JTAG pins should be as short as possible.
GND
KEY (NO PIN)
BTMS
BTCK
BTRST
BTDI
GND
1 2
3 4
5 6
7 8
9 10
9
11 12
13 14
TOP VIEW
EMU
CLKIN (OPTIONAL)
TMS
TCK
TRST
TDI
TDO
Figure 6. Target Board Connector for ADSP-2106x EZ-ICE Emulator (Jumpers in Place)
The 14-pin, 2-row pin strip header is keyed at the Pin 3 location; Pin 3 must be removed from the header. The pins must be
0.025 inch square and at least 0.20 inch in length. Pin spacing should be 0.1 × 0.1 inches. Pin strip headers are available from vendors such as 3M, McKenzie and Samtec.
The BTMS, BTCK, BTRST and BTDI signals are provided so that the test access port can also be used for board-level testing. When the connector is not being used for emulation, place jumpers between the Bxxx pins and the xxx pins as shown in Figure 6. If you are not going to use the test access port for board testing, tie BTRST to GND and tie or pull up BTCK to V
. The TRST pin must be asserted after power-up (through
DD
BTRST on the connector) or held low for proper operation of the AD14060/AD14060L. None of the Bxxx pins (Pins 5, 7, 9,
11) are connected on the EZ-ICE probe. The JTAG signals are terminated on the EZ-ICE probe as follows:
Signal Termination
TMS Driven through 22 Resistor (16 µA–3.2 µA Driver) TCK Driven at 10 MHz through 22 Resistor (16 µA–
3.2 µA Driver)
TRST Driven by Open-Drain Driver* (Pulled Up by On-Chip
20 k resistor) TDI Driven by 16 µA–3.2 µA Driver TDO One TTL Load, No Termination CLKIN One TTL Load, No Termination (Optional Signal) EMU 4.7 k Pull-Up Resistor, One TTL Load (Open-Drain
Output from ADSP-2106x)
*TRST is driven low until the EZ-ICE probe is turned on by the EZ-ICE
software (after the invocation command).
Figure 7 shows JTAG scan path connections for the multi­processor system.
Connecting CLKIN to Pin 4 of the EZ-ICE header is optional. The emulator only uses CLKIN when directed to perform
OTHER
JTAG
CONTROLLER
EZ-ICE
JTAG
CONNECTOR
TCK TMS
EMU
TRST
TDO
CLKIN
TDI
SHARC_A
TDI TDO
TCK
TMS
OPTIONAL
EMU
TRST
SHARC_B
TDI TDO
TCK
TMS
EMU
TRST
SHARC_C
TDI TDO
TCK
TMS
EMU
TRST
SHARC_D
TDI TDO
TCK
TMS
EMU
TRST
Figure 7. JTAG Scan Path Connections for the AD14060/AD14060L
–12–
JTAG DEVICE
(OPTIONAL)
TDI TDO
TCK
TMS
TRST
ADSP-2106x
#n
TDI TDO
TCK
TMS
EMU
REV. A
TRST
AD14060/AD14060L
operations such as starting, stopping and single-stepping mul­tiple ADSP-2106xs in a synchronous manner. If you do not need these operations to occur synchronously on the multiple processors, simply tie Pin 4 of the EZ-ICE header to ground.
If synchronous multiprocessor operations are needed and CLKIN is connected, clock skew between the AD14060/AD14060L and the CLKIN pin on the EZ-ICE header must be minimal. If the skew is too large, synchronous operations may be off by one cycle between processors. For synchronous multiprocessor operation TCK, TMS, CLKIN and EMU should be treated as critical signals in terms of skew, and should be laid out as short
TDI TDO TDI TDO
5kV
*
TDI
EMU
TCK
TMS
TRST
TDO
CLKIN
TDI TDO
5kV
*
*
OPEN DRAIN DRIVER OR EQUIVALENT, i.e.,
TDI TDO
as possible on your board. If TCK, TMS and CLKIN are driv­ing a large number of ADSP-2106xs (more than eight) in your system, then treat them as a “clock tree” using multiple drivers to minimize skew. (See Figure 8 JTAG Clock Tree and Clock Distribution in the “High Frequency Design Considerations” section of the ADSP-2106x User’s Manual).
If synchronous multiprocessor operations are not needed (i.e., CLKIN is not connected), just use appropriate parallel termina­tion on TCK and TMS. TDI, TDO, EMU and TRST are not critical signals in terms of skew.
TDI TDO
TDI TDO
SYSTEM
EMU
CLKIN
Figure 8. JTAG Clocktree for Multiple ADSP-2106x Systems
REV. A
–13–
AD14060/AD14060L–SPECIFICA TIONS

RECOMMENDED OPERATING CONDITIONS

Parameter Min Max Min Max Units
B Grade K Grade
V T
DD
CASE
Supply Voltage (5 V) 4.75 5.25 4.75 5.25 V Supply Voltage (3.3 V) 3.15 3.6 3.15 3.6 V Case Operating Temperature –40 +100 0 +85 °C
ELECTRICAL CHARACTERISTICS (3.3 V, 5 V SUPPLY)
Parameter Temp Level Test Condition Min Typ Max Min Typ Max Units
V
IH1
V
IH2
V
IL
V
OH
V
OL
I
IH
I
IL
I
ILP
I
ILPX4
I
OZH
I
OZL
I
OZHP
I
OZLC
I
OZLA
I
OZLAR
I
OZLS
I
OZLSX4
I
DDIN
I
DDIDLE
C
IN
High Level Input Voltage High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage High Level Input Current Low Level Input Current Low Level Input Current Low Level Input Current Three-State Leakage Current Three-State Leakage Current Three-State Leakage Current Three-State Leakage Current Three-State Leakage Current
Three-State Leakage Current Three-State Leakage Current Three-State Leakage Current Supply Current (Internal) Supply Current (Idle) Input Capacitance
1 2
1, 2
3, 4
3, 4
5, 6, 7 5 6 7
8, 9, 10, 14 8, 11 11 12 13
10 9 14
15
16
17, 18
EXPLANATION OF TEST LEVELS Test Level
I 100% Production Tested19. II 100% Production Tested at +25°C, and Sample Tested at Specified Temperatures. III Sample Tested Only. IV Parameter is guaranteed by design and analysis, and characterization testing on discrete SHARCs. V Parameter is typical value only. VI All devices are 100% production tested at +25°C; sample tested at temperature extremes.
NOTES
1
Applies to input and bidirectional pins: DATA
BR
, RPBA, CPAy, TFS0, TFSy1, RFS0, RFSy1, LyxDAT
6-1
TDI, TCK, HBR, DR0, DRy1, TCLK0, TCLKy1, RCLK0, RCLKy1.
2
Applies to input pins: CLKIN, RESET, TRST.
3
Applies to output and bidirectional pins: DATA REDY, DMAG1, DMAG2, BR BMSA, BMSBCD, TDO, EMU.
4
See Output Drive Currents for typical drive current capabilities.
5
Applies to input pins: SBTS, IRQy
6
Applies to input pins with internal pull-ups: DR0, DRy1, TDI.
7
Applies to bussed input pins with internal pull-ups: TRST, TMS.
8
Applies to three-statable pins: DATA BMSA, BMSBCD, TDO, EMU. (Note that ACK is pulled up internally with 2 k during reset in a multiprocessor system, when ID 2106x is not requesting bus mastership. HBG AND EMU are not tested for leakage current.)
9
Applies to three-statable pins with internal pull-ups: DTy1, TCLKy1, RCLKy1.
10
Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 k during reset in a multiprocessor system, when ID ADSP-2106x is not requesting bus mastership.)
11
Applies to three-statable pins with internal pull-downs: LyxDAT
12
Applies to CPAy pin.
13
Applies to ACK pin when keeper latch enabled.
14
Applies to bused three-statable pins with internal pull-ups: DT0, TCLK0, RCLK0.
15
Applies to VDD pins. Conditions of operation: each processor executing radix-2 FFT butterfly with instruction in cache, one data operand fetched from each internal memory block, and one DMA transfer occurring from/to internal memory at tCK = 25 ns.
16
Applies to VDD pins. Idle denotes AD14060/AD14060L state during execution of IDLE instruction.
17
Applies to all signal pins.
18
Guaranteed but not tested.
19
Link and Serial Ports: All are 100% tested at die level prior to assembly. All are 100% ac tested at module level; Link-4 and Serial-0 are also dc tested at the module
, CPAy, DTO, DTy1, TCLK0, TCLKy1, RCLK0, RCLKy1, TFS0, TFSy1, RFS0, RFSy1 LyxDAT
6-1
, HBR, CSy, DMAR1, DMAR2, RPBA, EBOOTA, LBOOTA, EBOOTBCD, LBOOTBCD, CLKIN, RESET, TCK.
2-0
, ADDR
47-0
level. See Timing Specifications.
Specifications subject to change without notice.
Case Test 5 V 3.3 V
Full I @ VDD = max 2.0 VDD + 0.5 2.0 VDD + 0.5 V Full I @ VDD = max 2.2 VDD + 0.5 2.2 VDD + 0.5 V Full I @ VDD = min 0.8 0.8 V Full I @ VDD = min, IOH = –2.0 mA44.1 2.4 V Full I @ VDD = min, IOL = 4.0 mA
4
0.4 0.4 V Full I @ VDD = max, VIN = VDD max 10 10 µA Full I @ VDD = max, VIN = 0 V 10 10 µA Full I @ VDD = max, VIN = 0 V 150 150 µA Full I @ VDD = max, VIN = 0 V 600 600 µA Full I @ VDD = max, VIN = VDD max 10 10 µA Full I @ VDD = max, VIN = 0 V 10 10 µA Full I @ VDD = max, VIN = VDD max 350 350 µA Full I @ VDD = max, VIN = 0 V 1.5 1.5 mA Full I @ VDD = max, VIN = 1.5 V (5 V),
2 V (3.3 V) 350 350 µA Full I @ VDD = max, VIN = 0 V 4.2 4.2 mA Full I @ VDD = max, VIN = 0 V 150 150 µA Full I @ VDD = max, VIN = 0 V 600 600 µA Full IV tCK = 25 ns, VDD = max 1.4 3.4 1.0 2.2 A Full I VDD = max 800 760 mA +25°CV
, ADDR
47-0
, ADDR
47-0
, MS
31-0
, RD, WR, SW, ACK, SBTS, IRQy
31-0
, LyxCLK, LyxACK, EBOOTA, LBOOTA, EBOOTBCD, LBOOTBCD, BMSA, BMSBCD, TMS,
3-0
, MS
31-0
, RD, WR, PAGE, ADRCLK, SW, ACK, FLAGy0, FLAG1, FLAGy2, REDY, HBG, DMAG1, DMAG2,
3-0
RD, WR, PAGE, ADRCLK, SW, ACK, FLAGy0, FLAG1, FLAGy2, TIMEXPy, HBG,
3-0
, LyxCLK, LyxACK.
3-0
, FLAGy0, FLAG1, FLAGy2, HBG, CSy, DMAR1, DMAR2,
2-0
15 15 pF
, LyxCLK, LyxACK,
3-0
= 001 and another ADSP-
2-0
= 001 and another
2-0
–14–
REV. A
AD14060/AD14060L
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage (5 V) . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Supply Voltage (3.3 V) . . . . . . . . . . . . . . . . –0.3 V to +4.6 V
Input Voltage . . . . . . . . . . . . . . . . . . . . –0.5 V to V
Output Voltage Swing . . . . . . . . . . . . . –0.5 V to V
Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF
Junction Temperature Under Bias . . . . . . . . . . . . . . . . 130°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (5 seconds) . . . . . . . . . . . . . . . . . +280°C
*Stresses greater than those listed above may cause permanent damage to the
device. These are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD SENSITIVITY

The AD14060/AD14060L modules are ESD (electrostatic discharge) sensitive devices. Electro­static charges readily accumulate on the human body and equipment and can discharge without detection. Permanent damage may occur to devices subjected to high energy electrostatic discharges.
The ADSP-21060 processors include proprietary ESD protection circuitry to dissipate high energy discharges. Per method 3015 of MIL-STD-883, the ADSP-21060 processors have been classified as a Class 2 device.
Proper ESD precautions are recommended to avoid performance degradation or loss of function­ality. Unused devices must be stored in conductive foam or shunts, and the foam should be discharged to the destination socket before devices are removed.
+ 0.5 V
DD
+ 0.5 V
DD

TIMING SPECIFICATIONS

GENERAL NOTES
This data sheet represents production released specifications for the AD14060 (5 V), and for the AD14060L (3.3 V). The ADSP-21060 die components are 100% tested, and the assembled AD14060/AD14060L units are again extensively tested at­speed, and across-temperature. Parametric limits were estab­lished from the ADSP-21060 characterization followed by further design/analysis of the AD14060/AD14060L package characteristics. The specifications shown are based on a CLKIN frequency of 40 MHz (t specifications at other CLKIN frequencies (within the min-max range of the t
specification; see “Clock Input” below). DT is the
CK
difference between the actual CLKIN period and a CLKIN period of 25 ns:
Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for
= 25 ns). The DT derating allows
CK
DT = t
– 25 ns
CK
an individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, you cannot meaningfully add parameters to derive longer times.
Switching Characteristics specify how the processor changes its signals. You have no control over this timing—circuitry external to the processor must be designed for compatibility with these signal characteristics. Switching characteristics tell you what the processor will do in a given circumstance. You can also use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied.
Timing Requirements apply to signals that are controlled by cir­cuitry external to the processor, such as the data input for a read operation. Timing requirements guarantee that the processor operates correctly with other devices.
(O/D) = Open Drain (A/D) = Active Drain
REV. A
–15–
AD14060/AD14060L
40 MHz–5 V 40 MHz–3.3 V
Parameter Min Max Min Max Units Clock Input
Timing Requirements:
t
CK
t
CKL
t
CKH
t
CKRF
CLKIN Period 25 100 25 100 ns CLKIN Width Low 7 8.75 ns CLKIN Width High 5 5 ns CLKIN Rise/Fall (0.4 V–2.0 V) 3 3 ns
t
CK
CLKIN
t
CKH
t
CKL
Figure 9. Clock Input
5 V 3.3 V
Parameter Min Max Min Max Units Reset
Timing Requirements:
t
WRST
t
SRST
NOTES
1
Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2000 CLKIN cycles while RESET is
low, assuming stable VDD and CLKIN (not including start-up time of external clock oscillator).
2
Only required if multiple ADSP-2106xs must come out of reset synchronous to CLKIN with program counters (PC) equal (i.e., for a SIMD system). Not required
for multiple ADSP-2106xs communicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself after reset.
RESET Pulsewidth Low RESET Setup Before CLKIN High214 + DT/2 t
CLKIN

RESET

1
4t
CK
t
WRST
CK
4t
CK
14 + DT/2 t
t
SRST
CK
ns ns
Figure 10. Reset
5 V 3.3 V
Parameter Min Max Min Max Units Interrupts
Timing Requirements:
t
SIR
t
HIR
t
IPW
NOTES
1
Only required for IRQx recognition in the following cycle.
2
Applies only if t
IRQ2-0 Setup Before CLKIN High118 + 3DT/4 18 + 3DT/4 ns IRQ2-0 Hold Before CLKIN High IRQ2-0 Pulsewidth
and t
SIR
requirements are not met.
HIR
2
1
2 + t
CK
11.5 + 3DT/4 11.5 + 3DT/4 ns 2 + t
CK
ns
CLKIN
IRQ2-0
t
SIR
t
HIR
t
IPW
Figure 11. Interrupts
–16–
REV. A
AD14060/AD14060L
5 V 3.3 V
Parameter Min Max Min Max Units Timer
Switching Characteristic:
t
DTEX
Parameter Min Max Min Max Units Flags
Timing Requirements:
t
SFI
t
HFI
t
DWRFI
t
HFIWR
CLKIN High to TIMEXP 16 16 ns
CLKIN
t
DTEX
TIMEXP
t
DTEX
Figure 12. Timer
5 V 3.3 V
FLAG2-0 FLAG2-0 FLAG2-0 FLAG2-0
Setup Before CLKIN High
IN
Hold After CLKIN High
IN
Delay After RD/WR Low
IN
Hold After RD/WR Deasserted10.5 0.5 ns
IN
1
1
1
8 + 5DT/16 8 + 5DT/16 ns
0.5 – 5DT/16 0.5 – 5DT/16 ns
4.5 + 7DT/16 4.5 + 7DT/16 ns
Switching Characteristics:
t
DFO
t
HFO
t
DFOE
t
DFOD
NOTE
1
Flag inputs meeting these setup and hold times will affect conditional instructions in the following instruction cycle.
FLAG2-0 FLAG2-0 CLKIN High to FLAG2-0 CLKIN High to FLAG2-0
CLKIN
FLAG2–0
OUT
CLKIN
FLAG2–0
IN
RD, WR
Delay After CLKIN High 17 17 ns
OUT
Hold After CLKIN High 4 4 ns
OUT
t
DFOE
t
DWRFI
FLAG INPUT
Enable 3 3 ns
OUT
Disable 15 15 ns
OUT
t
t
DFO
FLAG OUTPUT
t
t
HFIWR
HFI
t
SFI
DFO
t
HFO
Figure 13. Flags
t
DFOD
REV. A
–17–
AD14060/AD14060L

Memory Read—Bus Master

Use these specifications for asynchronous interfacing to memo­ries (and memory-mapped peripherals) without reference to CLKIN. These specifications apply when the AD14060/
These switching characteristics also apply for bus master syn­chronous read/write timing (see Synchronous Read/Write – Bus Master below). If these timing requirements are met, the syn­chronous read/write timing can be ignored (and vice versa).
AD14060L is the bus master accessing external memory space.
5 V 3.3 V
Parameter Min Max Min Max Units
Timing Requirements:
t
DAD
t
DRLD
t
HDA
t
HDRH
t
DAAK
t
DSAK
Address, Delay to Data Valid RD Low to Data Valid Data Hold from Address Data Hold from RD High ACK Delay from Address ACK Delay from RD Low
1, 4
1
2
2 3, 4
3
11ns
2.5 2.5 ns
17.5 + DT + W 17.5 + DT + W ns
11.5 + 5DT/8 + W 11.5 + 5DT/8 + W ns
13.5 + 7DT/8 + W 13.5 + 7DT/8 + W ns
7.5 + DT/2 + W 7.5 + DT/2 + W ns
Switching Characteristics:
t
DRHA
t
DARL
t
RW
t
RWR
t
SADADC
W = (number of wait states specified in WAIT register) × t HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0). H = tCK (if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).
NOTES
1
Data Delay/Setup: User must meet t
2
Data Hold: User must meet t given capacitive and dc loads.
3
ACK Delay/Setup: User must meet t
4
For MSx, SW, BMS, the falling edge is referenced.
Address Hold After RD High –0.5 + H –0.5 + H ns Address to RD Low
4
1.5 + 3DT/8 1.5 + 3DT/8 ns
RD Pulsewidth 12.5 + 5DT/8 + W 12.5 + 5DT/8 + W ns RD High to WR, RD, DMAGx Low 8 + 3DT/8 + HI 8 + 3DT/8 + HI ns
Address Setup Before ADRCLK High4–0.5 + DT/4 –0.5 + DT/4 ns
CK.
or t
HDA
DAD
or t
DRLD
or synchronous spec t
HDRH
or t
DSAK
or synchronous spec t
HDATI
or synchronous specification t
DAAK
.
SSDATI
. See System Hold Time Calculation under Test Conditions for the calculation of hold times
.
SACKC
ADDRESS
MSx, SW
BMS
RD
DATA
ACK
WR, DMAG
ADRCLK
(OUT)
t
SADADC
t
DARL
t
t
RW
t
t
t
DAAK
DRLD
DAD
DSAK
Figure 14. Memory Read—Bus Master
t
t
t
HDRH
DRHA
HDA
t
RWR
–18–
REV. A
AD14060/AD14060L

Memory Write—Bus Master

Use these specifications for asynchronous interfacing to memo­ries (and memory-mapped peripherals) without reference to CLKIN. These specifications apply when the AD14060/
These switching characteristics also apply for bus master syn­chronous read/write timing (see Synchronous Read/Write–Bus Master). If these timing requirements are met, the synchronous read/write timing can be ignored (and vice versa).
AD14060L is the bus master accessing external memory space.
5 V 3.3 V
Parameter Min Max Min Max Units
Timing Requirements:
t
DAAK
t
DSAK
ACK Delay from Address, Selects ACK Delay from WR Low
1, 2
1
13.5 + 7DT/8 + W 13.5 + 7DT/8 + W ns
7.5 + DT/2 + W 7.5 + DT/2 + W ns
Switching Characteristics:
t
DAWH
t
DAWL
t
WW
t
DDWH
t
DWHA
t
DATRWH
t
WWR
t
DDWR
t
WDE
t
SADADC
W = (number of wait states specified in WAIT register) × tCK. H = tCK (if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0). I = tCK (if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0). NOTES
1
ACK Delay/Setup: User must meet t
2
For MSx, SW, BMS, the falling edge is referenced.
3
See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
Address, Selects to WR Deasserted216.5 + 15DT/16 + W 16.5 + 15DT/16 + W ns Address, Selects to WR Low
2
2.5 + 3DT/8 2.5 + 3DT/8 ns WR Pulsewidth 12 + 9DT/16 + W 12 + 9DT/16 + W ns Data Setup before WR High 6.5 + DT/2 + W 6.5 + DT/2 + W ns Address Hold after WR Deasserted –1 + DT/16 + H –1 + DT/16 + H ns Data Disable after WR Deasserted30.5 + DT/16 + H 6.5 + DT/16 + H 0.5 + DT/16 + H 6.5 + DT/16 + H ns WR High to WR, RD, DMAGx Low 7.5 + 7DT/16 + H 7.5 + 7DT/16 + H ns Data Disable before WR or RD Low 4.5 + 3DT/8 + I 4.5 + 3DT/8 + I ns WR Low to Data Enabled –1.5 + DT/16 –1.5 + DT/16 ns Address, Selects to ADRCLK High2–0.5 + DT/4 –0.5 + DT/4 ns
or t
DAAK
or synchronous specification t
DSAK
SACKC
.
ADDRESS
MSx , SW
BMS
WR
DATA
ACK
RD , DMAG
ADRCLK
(OUT)
t
SADADC
t
DAWL
t
DAWH
t
WW
t
WDE
t
DSAK
t
DAAK
Figure 15. Memory Write—Bus Master
t
DDWH
t
DATRWH
t
DWHA
t
WWR
t
DDWR
REV. A
–19–
AD14060/AD14060L
Synchronous Read/Write—Bus Master
Use these specifications for interfacing to external memory systems that require CLKIN—relative timing or for accessing a slave ADSP-2106x (in multiprocessor memory space). These synchronous switching characteristics are also valid during asyn-
When accessing a slave ADSP-2106x, these switching character­istics must meet the slave’s timing requirements for synchronous read/writes (see Synchronous Read/Write—Bus Slave). The slave ADSP-2106x must also meet these (bus master) timing
requirements for data and acknowledge setup and hold times. chronous memory reads and writes (see Memory Read—Bus Master and Memory Write—Bus Master).
5 V 3.3 V
Parameter Min Max Min Max Units
Timing Requirements:
t
SSDATI
t
HSDATI
t
DAAK
t
SACKC
t
HACKC
Switching Characteristics:
t
DADRO
t
HADRO
t
DPGC
t
DRDO
t
DWRO
t
DRWL
t
SDDATO
t
DATTR
t
DADCCK
t
ADRCK
t
ADRCKH
t
ADRCKL
W = (number of Wait states specified in WAIT register) × tCK. NOTES
1
For MSx, SW, BMS, the falling edge is referenced.
2
ACK Delay/Setup: User must meet t
3
See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
Data Setup Before CLKIN 3 + DT/8 3 + DT/8 ns Data Hold After CLKIN 4 – DT/8 4 – DT/8 ns ACK Delay After Address, MSx, SW, BMS ACK Setup Before CLKIN
2
1, 2
13.5 + 7 DT/8 + W 13.5 + 7 DT/8 + W ns
6.5 + DT/4 6.5 + DT/4 ns
ACK Hold After CLKIN –0.5 – DT/4 –0.5 – DT/4 ns
Address, MSx, BMS, SW Delay After CLKIN
1
8 – DT/8 8 – DT/8 ns Address, MSx, BMS, SW Hold After CLKIN –1 – DT/8 –1 – DT/8 ns PAGE Delay After CLKIN 9 + DT/8 17 + DT/8 9 + DT/8 17 + DT/8 ns
RD High Delay After CLKIN –2 – DT/8 5 – DT/8 –2 – DT/8 5 – DT/8 ns WR High Delay After CLKIN –3 – 3DT/16 5 – 3DT/16 –3 – 3DT/16 5 – 3DT/16 ns RD/WR Low Delay After CLKIN 8 + DT/4 13.5 + DT/4 8 + DT/4 13.5 + DT/4 ns
Data Delay After CLKIN 20 + 5DT/16 20 + 5DT/16 ns Data Disable After CLKIN
3
0 – DT/8 8 – DT/8 0 – DT/8 8 – DT/8 ns ADRCLK Delay After CLKIN 4 + DT/8 11 + DT/8 4 + DT/8 11 + DT/8 ns ADRCLK Period t
CK
t
CK
ns ADRCLK Width High (tCK/2 – 2) (tCK/2 – 2) ns ADRCLK Width Low (tCK/2 – 2) (tCK/2 – 2) ns
or t
DAAK
or synchronous specification t
DSAK
SACKC
.
–20–
REV. A
CLKIN
ADRCLK
ADDRESS
SW
PAGE
ACK
(IN)
READ CYCLE
RD
DATA
(IN)
t
DADRO
t
DADCCK
t
t
DPGC
DRWL
t
DAAK
t
ADRCKH
t
ADRCK
t
SACKC
t
SSDATI
AD14060/AD14060L
t
ADRCKL
t
HADRO
t
HACKC
t
DRDO
t
HSDATI
WRITE CYCLE
WR
DATA (OUT)
t
DRWL
t
SDDATO
Figure 16. Synchronous Read/Write—Bus Master
t
DWRO
t
DATTR
REV. A
–21–
AD14060/AD14060L

Synchronous Read/Write—Bus Slave

The bus master must meet these (bus slave) timing requirements. Use these specifications for bus master accesses of a slave’s IOP registers or internal memory (in multiprocessor memory space).
5 V 3.3 V
Parameter Min Max Min Max Units
Timing Requirements:
t
SADRI
t
HADRI
t
SRWLI
t
HRWLI
t
RWHPI
t
SDATWH
t
HDATWH
Address, SW Setup Before CLKIN 15.5 + DT/2 15.5 + DT/2 ns Address, SW Hold Before CLKIN 4.5 + DT/2 4.5 + DT/2 ns
RD/WR Low Setup Before CLKIN19.5 + 5DT/16 9.5 + 5DT/16 ns RD/WR Low Hold After CLKIN –3.5 – 5DT/16 8 + 7DT/16 –3.5 – 5DT/16 8 + 7DT/16 ns RD/WR Pulse High 3 3 ns
Data Setup Before WR High 5.5 5.5 ns Data Hold After WR High 1.5 1.5 ns
Switching Characteristics:
t
SDDATO
t
DATTR
t
DACKAD
t
ACKTR
NOTES
1
t
(min) = 9.5 + 5DT/16 when Multiprocessor Memory Space Wait State (MMSWS bit in WAIT register) is disabled; when MMSWS is enabled,
SRWLI
t
(min) = 4 + DT/8.
SRWLI
2
See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
3
t
is true only if the address and SW inputs have setup times (before CLKIN) greater than 10.5 + DT/8 and less than 18.5 + 3DT/4. If the address and SW inputs have
DACKAD
setup times greater than 19 + 3DT/4, then ACK is valid 15 + DT/4 (max) after CLKIN. A slave that sees an address with an M field match will respond with ACK regardless of the state of MMSWS or strobes. A slave will three-state ACK every cycle with t
Data Delay After CLKIN 20 + 5DT/16 20 + 5DT/16 ns Data Disable After CLKIN ACK Delay After Address, SW ACK Disable After CLKIN
2
3
3
0 – DT/8 8 – DT/8 0 – DT/8 8 – DT/8 ns
10 10 ns
–1 – DT/8 7 – DT/8 –1 – DT/8 7 – DT/8 ns
.
ACKTR
CLKIN
ADDRESS
SW
ACK
READ ACCESS
RD
DATA
(OUT)
WRITE ACCESS
WR
DATA
(IN)
t
t
SDDATO
t
DACKAD
SADRI
t
SRWLI
t
SRWLI
t
HADRI
t
SDATWH
Figure 17. Synchronous Read/Write—Bus Slave
t
HRWLI
t
HRWLI
t
HDATWH
t
t
DATTR
ACKTR
t
RWHPI
t
RWHPI
–22–
REV. A
AD14060/AD14060L
Multiprocessor Bus Request and Host Bus Request
Use these specifications for passing of bus mastership between multiprocessing ADSP-2106x’s (BRx) or a host processor (HBR, HBG).
5 V 3.3 V
Parameter Min Max Min Max Units
Timing Requirements:
t
HBGRCSV
t
SHBRI
t
HHBRI
t
SHBGI
t
HHBGI
t
SBRI
t
HBRI
t
SRPBAI
t
HRPBAI
HBG Low to RD/WR/CS Valid HBR Setup Before CLKIN HBR Hold Before CLKIN HBG Setup Before CLKIN 13 + DT/2 13 + DT/2 ns HBG Hold Before CLKIN High 5.5 + DT/2 5.5 + DT/2 ns BRx, CPA Setup Before CLKIN BRx, CPA Hold Before CLKIN High 5.5 + DT/2 5.5 + DT/2 ns
RPBA Setup Before CLKIN 20 + 3DT/4 20 + 3DT/4 ns RPBA Hold Before CLKIN 11.5 + 3DT/4 11.5 + 3DT/4 ns
Switching Characteristics:
t
DHBGO
t
HHBGO
t
DBRO
t
HBRO
t
DCPAO
t
TRCPA
t
DRDYCS
t
TRDYHG
t
ARDYTR
HBG Delay After CLKIN 8 – DT/8 8 – DT/8 ns HBG Hold After CLKIN –2 – DT/8 –2 – DT/8 ns BRx Delay After CLKIN 8 – DT/8 8 – DT/8 ns BRx Hold After CLKIN –2 – DT/8 –2 – DT/8 ns CPA Low Delay After CLKIN 9 – DT/8 9 – DT/8 ns CPA Disable After CLKIN –2 – DT/8 5.5 – DT/8 –2 – DT/8 5.5 – DT/8 ns
REDY (O/D) or (A/D) Low from CS and HBR Low REDY (O/D) Disable or REDY (A/D) High from HBG REDY (A/D) Disable from CS or HBR High
1
2
2
3
4
4
20 + 3DT/4 20 + 3DT/4 ns
13 + DT/2 13 + DT/2 ns
4
44 + 27DT/16 44 + 27DT/16 ns
19.5 + 5DT/4 19.5 + 5DT/4 ns
13.5 + 3DT/4 13.5 + 3DT/4 ns
9.5 10.25 ns 11 11 ns
NOTES
1
For first asynchronous access after HBR and CS asserted, ADDR low. This is easily accomplished by driving an upper address signal high when HBG is asserted.
2
Only required for recognition in the current cycle.
3
CPA assertion must meet the setup to CLKIN; deassertion does not need to meet the setup to CLKIN.
4
(O/D) = open drain, (A/D) = active drive.
must be a non-MMS value 1/2 tCK before RD or WR goes low or by t
31–0
HBGRCSV
after HBG goes
REV. A
–23–
AD14060/AD14060L
CLKIN
t
SHBRI
HBR
HBG
(OUT)
BRx
(OUT)
CPA (OUT)
(O/D)
HBG (IN)
BRx (IN)
CPA (IN) (O/D)
HBR
CS
REDY (O/D)
t
DRDYCS
t
HHBRI
t
HHBGO
t
HBRO
t
DHBGO
t
DBRO
t
DCPAO
t
TRDYHG
t
t
SHBGI
SBRI
t
HHBGI
t
HBRI
t
TRCPA
t
ARDYTR
REDY (A/D)
HBG (OUT)
RD
WR
CS
RPBA
t
HBGRCSV
t
SRPBAI
O/D = OPEN DRAIN, A/D = ACTIVE DRIVE HBG WILL BE DELAYED BY n CLOCK CYCLES WHEN WAIT STATES OR BUS LOCK ARE IN EFFECT.
t
HRPBAI
Figure 18. Multiprocessor Bus Request and Host Bus Request
–24–
REV. A
AD14060/AD14060L
Asynchronous Read/Write—Host to AD14060/AD14060L
Use these specifications for asynchronous host processor accesses of an AD14060/AD14060L, after the host has asserted CS and
AD14060L, the host can drive the RD and WR pins to access the AD14060/AD14060L’s internal memory or IOP registers.
HBR and HBG are assumed low for this timing.
HBR (low). After HBG is returned by the AD14060/
5 V 3.3 V
Parameter Min Max Min Max Units
Read Cycle
Timing Requirements:
t
SADRDL
t
HADRDH
t
WRWH
t
DRDHRDY
t
DRDHRDY
Address Setup/CS Low Before RD Low Address Hold/CS Hold Low After RD 0.5 0.5 ns
RD/WR High Width 6 6 ns RD High Delay After REDY (O/D) Disable 0.5 0.5 ns RD High Delay After REDY (A/D) Disable 0.5 0.5 ns
1
0.5 0.5 ns
Switching Characteristics:
t
SDATRDY
t
DRDYRDL
t
RDYPRD
t
HDARWH
Data Valid Before REDY Disable from Low 1.5 1.5 ns REDY (O/D) or (A/D) Low Delay After RD Low 11 11.5 ns REDY (O/D) or (A/D) Low Pulsewidth for Read 45 + DT 45 + DT ns Data Disable After RD High 1.5 9 1.5 9.5 ns
Write Cycle
Timing Requirements:
t
SCSWRL
t
HCSWRH
t
SADWRH
t
HADWRH
t
WWRL
t
WRWH
t
DWRHRDY
t
SDATWH
t
HDATWH
CS Low Setup Before WR Low 0.5 0.5 ns CS Low Hold After WR High 0.5 0.5 ns
Address Setup Before WR High 5.5 5.5 ns Address Hold After WR High 2.5 2.5 ns
WR Low Width 7 7 ns RD/WR High Width 6 6 ns WR High Delay After REDY (O/D) or (A/D) Disable 0.5 0.5 ns
Data Setup Before WR High 5.5 5.5 ns Data Hold After WR High 1.5 1.5 ns
Switching Characteristics:
t
DRDYWRL
t
RDYPWR
t
SRDYCK
NOTE
1
Not required if RD and address are valid t or WR goes low or by t driven during asynchronous host accesses, see Table 8.2 of the ADSP-2106x SHARC User’s Manual.
REDY (O/D) or (A/D) Low Delay After WR/CS Low 11 11.5 ns REDY (O/D) or (A/D) Low Pulsewidth for Write 15 15 ns REDY (O/D) or (A/D) Disable to CLKIN 1 + 7DT/16 9 + 7DT/16 0 + 7DT/16 8 + 7DT/16 ns
after HBG goes low. For first access after HBR asserted, ADDR
after HBG goes low. This is easily accomplished by driving an upper address signal high when HBG is asserted. For address bits to be
HBGRCSV
HBGRCSV
CLKIN
REDY (O/D)
REDY (A/D)
O/D = OPEN DRAIN, A/D = ACTIVE DRIVE
Figure 19a. Synchronous REDY Timing
t
SRDYCK
must be a non-MMS value 1/2 t
31–0
before RD
CLK
REV. A
–25–
AD14060/AD14060L
READ CYCLE
ADDRESS/CS
RD
DATA (OUT)
REDY (O/D)
REDY (A/D)
WRITE CYCLE
t
SADRDL
t
DRDYRDL
t
SDATRDY
t
RDYPRD
t
DRDHRDY
t
HDARWH
t
HADRDH
t
WRWH
ADDRESS
WR
DATA (IN)
REDY (O/D)
REDY (A/D)
CS
O/D = OPEN DRAIN, A/D = ACTIVE DRIVE
Figure 19b. Asynchronous Read/Write—Host to ADSP-2106x
t
SCSWRL
t
DRDYWRL
t
WWRL
t
RDYPWR
t
SADWRH
t
SDATWH
t
HCSWRH
t
DWRHRDY
t
HADWRH
t
HDATWH
t
WRWH
–26–
REV. A
AD14060/AD14060L
Three-State Timing—Bus Master, Bus Slave, HBR, SBTS
These specifications show how the memory interface is disabled (stops driving) or enabled (resumes driving) relative to CLKIN and the SBTS pin. This timing is applicable to bus master tran­sition cycles (BTC) and host transition cycles (HTC) as well as the SBTS pin.
5 V 3.3 V
Parameter Min Max Min Max Units
Timing Requirements:
t
STSCK
t
HTSCK
Switching Characteristics:
t
MIENA
t
MIENS
t
MIENHG
t
MITRA
t
MITRS
t
MITRHG
t
DATEN
t
DATTR
t
ACKEN
t
ACKTR
t
ADCEN
t
ADCTR
t
MTRHBG
t
MENHBG
SBTS Setup Before CLKIN 12 + DT/2 12 + DT/2 ns SBTS Hold Before CLKIN 5.5 + DT/2 5.5 + DT/2 ns
Address/Select Enable After CLKIN –1.5 – DT/8 –1.25 – DT/8 ns Strobes Enable After CLKIN
1
–1.5 – DT/8 –1.5 – DT/8 ns HBG Enable After CLKIN –1.5 – DT/8 –1.5 – DT/8 ns Address/Select Disable After CLKIN 1 – DT/4 1 – DT/4 ns Strobes Disable After CLKIN HBG Disable After CLKIN 3 – DT/4 3 – DT/4 ns Data Enable After CLKIN Data Disable After CLKIN ACK Enable After CLKIN ACK Disable After CLKIN
1
2
2
2
2
9 + 5DT/16 9 + 5DT/16 ns
0 – DT/8 8 – DT/8 0 – DT/8 8 – DT/8 ns
7.5 + DT/4 7.5 + DT/4 ns
–1 – DT/8 7 – DT/8 –1 – DT/8 7 – DT/8 ns
2.5 – DT/4 2.5 – DT/4 ns
ADRCLK Enable After CLKIN –2 – DT/8 –2 – DT/8 ns ADRCLK Disable After CLKIN 9 – DT/4 9 – DT/4 ns Memory Interface Disable Before HBG Low3–1 + DT/8 –1 + DT/8 ns Memory Interface Enable After HBG High
3
18.5 + DT 18.5 + DT ns
NOTES
1
Strobes = RD, WR, SW, PAGE, DMAG.
2
In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write.
3
Memory Interface = Address, RD, WR, MSx, SW, HBG, PAGE, DMAGx, BMS (in EPROM boot mode).
CLKIN
t
SBTS
MEMORY
INTERFACE
DATA
ACK
ADRCLK
HBG
MEMORY
INTERFACE
STSCK
t
MIENA, tMIENS, tMIENHG
t
DATEN
t
ACKEN
t
ADCEN
t
MENHBG
MEMORY INTERFACE = ADDRESS, RD, WR, MSx, SW, HBG, PAGE, DMAGx. BMS (IN EPROM BOOT MODE)
t
HTSCK
t
MITRA, tMITRS, tMITRHG
t
DATTR
t
ACKTR
t
ADCTR
Figure 20. Three-State Timing
t
MTRHBG
REV. A
–27–
AD14060/AD14060L
DMA Handshake
These specifications describe the three DMA handshake modes. In all three modes DMAR is used to initiate transfers. For hand­shake mode, DMAG controls the latching or enabling of data externally. For external handshake mode, the data transfer is controlled by the ADDR
, RD, WR, SW, PAGE, MS
31-0
3-0
,
transfer is controlled by ADDR (not DMAG). For Paced Master mode, the “Memory Read–Bus Master”, “Memory Write–Bus Master”, and “Synchronous Read/Write–Bus Master” timing specifications for ADDR RD, WR, MS
, SW, PAGE, DATA
3-0
, RD, WR, MS
31-0
, and ACK also apply.
47-0
, and ACK
3-0
31-0
,
ACK, and DMAG signals. For Paced Master mode, the data
5 V 3.3 V
Parameter Min Max Min Max Units
Timing Requirements:
t
SDRLC
t
SDRHC
t
WDR
t
SDATDGL
t
HDATIDG
t
DATDRH
t
DMARLL
t
DMARH
DMARx Low Setup Before CLKIN DMARx High Setup Before CLKIN DMARx Width Low (Nonsynchronous) 6 6 ns
Data Setup After DMAGx Low Data Hold After DMAGx High 2.5 2.5 ns Data Valid After DMAGx High
DMAGx Low Edge to Low Edge 23 + 7DT/8 23 + 7DT/8 ns DMAGx Width High 6 6 ns
1
2
2
55ns
1
55ns
9.5 + 5DT/8 9.5 + 5DT/8 ns
15.5 + 7DT/8 15.5 + 7DT/8 ns
Switching Characteristics:
t
DDGL
t
WDGH
t
WDGL
t
HDGC
t
VDATDGH
t
DATRDGH
t
DGWRL
t
DGWRH
t
DGWRR
t
DGRDL
t
DRDGH
t
DGRDR
t
DGWR
t
DADGH
t
DDGHA
W = (number of wait states specified in WAIT register) × tCK. HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
NOTES
1
Only required for recognition in the current cycle.
2
t
SDATDGL
data can be driven t
3
t
VDATDGH
where n equals the number of extra cycles that the access is prolonged.
4
See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
DMAGx Low Delay After CLKIN 9 + DT/4 16 + DT/4 9 + DT/4 16 + DT/4 ns DMAGx High Width 6 + 3DT/8 6 + 3DT/8 ns DMAGx Low Width 12 + 5DT/8 12 + 5DT/8 ns DMAGx High Delay After CLKIN –2 – DT/8 7 – DT/8 –2 – DT/8 7 – DT/8 ns
Data Valid Before DMAGx High Data Disable After DMAGx High
3
4
7.5 + 9DT/16 7.5 + 9DT/16 ns –0.5 8 –0.5 8 ns
WR Low Before DMAGx Low –0.5 2.5 –0.5 2.5 ns DMAGx Low Before WR High 9.5 + 5DT/8 + W 9.5 + 5DT/8 + W ns WR High Before DMAGx High 0.5 + DT/16 3.5 + DT/16 0.5 + DT/16 3.5 + DT/16 ns RD Low Before DMAGx Low –0.5 2 –0.5 2 ns RD Low Before DMAGx High 10.5 + 9DT/16 + W 10.5 + 9DT/16 + W ns RD High Before DMAGx High –0.5 3.5 –0.5 3.5 ns DMAGx High to WR, RD, DMAGx Low 4.5 + 3DT/8 + HI 4.5 + 3DT/8 + HI ns
Address/Select Valid to DMAGx High 16 + DT 16 + DT ns Address/Select Hold after DMAGx High –1 –1 ns
is the data setup requirement if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of the write, the
is valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then t
after DMARx is brought high.
DATDRH
= 7.5 + 9DT/16 + (n × tCK)
VDATDGH
–28–
REV. A
CLKIN
DMARx
DMAGx
t
SDRLC
t
WDR
t
DDGL
t
DMARLL
t
SDRHC
t
WDGL
AD14060/AD14060L
t
DMARH
t
HDGC
t
WDGH
TRANSFERS BETWEEN ADSP-2106x INTERNAL MEMORY AND EXTERNAL DEVICE
DATA (FROM
ADSP-2106x TO
EXTERNAL DRIVE)
t
DATDRH
t
DATA (FROM
EXTERNAL DRIVE
TO ADSP-2106x)
SDATDGL
TRANSFERS BETWEEN EXTERNAL DEVICE AND EXTERNAL MEMORY* (EXTERNAL HANDSHAKE MODE)
t
(EXTERNAL DEVICE
TO EXTERNAL
EXTERNAL DEVICE)
WR
MEMORY)
RD
(EXTERNAL
MEMORY TO
ADDRESS
MS
, SW
X
*
“MEMORY READ – BUS MASTER,” “MEMORY WRITE – BUS MASTER,” AND “SYNCHRONOUS READ/WRITE – BUS MASTER”
TIMING SPECIFICATIONS FOR ADDR
, RD, WR, SW, MS
31–0
DGWRL
t
DGRDL
AND ACK ALSO APPLY HERE.
3-0
t
DGWRH
t
DADGH
t
DRDGH
Figure 21. DMA Handshake Timing
t
VDATDGH
t
DGWRR
t
DGRDR
t
DATRDGH
t
HDATIDG
t
DDGHA
REV. A
–29–
AD14060/AD14060L
Link Ports: 1 × CLK Speed Operation
5 V 3.3 V
Parameter Min Max Min Max Units Receive
Timing Requirements:
t
SLDCL
t
HLDCL
t
LCLKIW
t
LCLKRWL
t
LCLKRWH
Switching Characteristics:
t
DLAHC
t
DLALC
t
ENDLK
t
TDLK
Transmit
Timing Requirements:
t
SLACH
t
HLACH
Switching Characteristics:
t
DLCLK
t
DLDCH
t
HLDCH
t
LCLKTWL
t
LCLKTWH
t
DLACLK
t
ENDLK
t
TDLK
Data Setup Before LCLK Low 3.5 3 ns Data Hold After LCLK Low 3 3 ns LCLK Period (1 × Operation) t
CK
t
CK
ns LCLK Width Low 6 6 ns LCLK Width High 5 5 ns
LACK High Delay After CLKIN High 18 + DT/2 29.5 + DT/2 18 + DT/2 29.5 + DT/2 ns LACK Low Delay After LCLK High
1
–3 13.5 –3 13.5 ns LACK Enable from CLKIN 5 + DT/2 5 + DT/2 ns LACK Disable from CLKIN 21 + DT/2 21 + DT/2 ns
LACK Setup Before LCLK High 18 20 ns LACK Hold After LCLK High –7 –7 ns
LCLK Delay After CLKIN (1 × Operation) 16.5 17.5 ns Data Delay After LCLK High 3.5 3 ns Data Hold After LCLK High –3 –3 ns LCLK Width Low (tCK/2) – 2 (tCK/2) + 2 (tCK/2) – 1 (tCK/2) + 1.25 ns LCLK Width High (tCK/2) – 2 (tCK/2) + 2 (tCK/2) – 1.25 (tCK/2) + 1 ns LCLK Low Delay After LACK High (tCK/2) + 8.5 (3 × tCK/2) + 17.5 (tCK/2) + 8 (3 × tCK/2) + 18 ns LDAT, LCLK Enable After CLKIN 5 + DT/2 5 + DT/2 ns LDAT, LCLK Disable After CLKIN 21 + DT/2 21 + DT/2 ns
Link Port Service Request Interrupts: 1 × and 2 × Speed Operations
Timing Requirements:
t
SLCK
t
HLCK
NOTES
1
LACK will go low with t
2
Only required for interrupt recognition in the current cycle.
LACK/LCLK Setup Before CLKIN Low210 10 ns LACK/LCLK Hold After CLKIN Low22.5 2.5 ns
relative to rising edge of LCLK after first nibble is received. LACK will not go low if the receiver’s link buffer is not about to fill.
DLALC
–30–
REV. A
AD14060/AD14060L
Link Ports: 2 × CLK Speed Operation
5 V 3.3 V
Parameter Min Max Min Max Units
R
eceive
Timing Requirements:
t
SLDCL
t
HLDCL
t
LCLKIW
t
LCLKRWL
t
LCLKRWH
Switching Characteristics:
t
DLAHC
t
DLALC
Transmit
Timing Requirements:
t
SLACH
t
HLACH
Switching Characteristics:
t
DLCLK
t
DLDCH
t
HLDCH
t
LCLKTWL
t
LCLKTWH
t
DLACLK
Data Setup Before LCLK Low 2.5 2.25 ns Data Hold After LCLK Low 2.25 2.25 ns LCLK Period (2 × Operation) tCK/2 tCK/2 ns LCLK Width Low 4.5 5 ns LCLK Width High 4.25 4 ns
LACK High Delay After CLKIN High 18 + DT/2 29.5 + DT/2 18 + DT/2 30.5 + DT/2 ns LACK Low Delay After LCLK High16 16.5 6 18.5 ns
LACK Setup Before LCLK High 19 19 ns LACK Hold After LCLK High –6.75 –6.5 ns
LCLK Delay After CLKIN 9 9 ns Data Delay After LCLK High 3 2.75 ns Data Hold After LCLK High –2 –2 ns LCLK Width Low (tCK/4) – 1 (tCK/4) + 1 (tCK/4) – 0.75 (tCK/4) + 1.5 ns LCLK Width High (tCK/4) – 1 (tCK/4) + 1 (tCK/4) – 1.5 (tCK/4) + 1 ns LCLK Low Delay After LACK High (tCK/4) + 9 (3 × tCL/4) + 17 (tCK/4) + 9 (3 × tCL/4) + 17 ns
NOTE
1
LACK will go low with t
relative to rising edge of LCLK after first nibble is received. LACK will not go low if the receiver’s link buffer is not about to fill.
DLALC
REV. A
–31–
AD14060/AD14060L
TRANSMIT
CLKIN
t
DLCLK
t
LCLKTWH
LCLK 1x
OR
LCLK 2x
t
DLDCH
t
HLDCH
t
LCLKTWL
LAST NIBBLE
TRANSMITTED
FIRST NIBBLE TRANSMITTED
LCLK INACTIVE
(HIGH)
LDAT(3:0)
LACK (IN)
THE
OUT
t
SLACH
REQUIREMENT APPLIES TO THE RISING EDGE OF LCLK ONLY FOR THE FIRST NIBBLE TRANSMITTED.
t
SLACH
RECEIVE
CLKIN
t
LCLKIW
t
HLDCL
IN
t
LCLKRWL
LCLK 1x
OR
LCLK 2x
LDAT(3:0)
LACK (OUT)
t
LCLKRWH
t
SLDCL
t
DLAHC
LACK GOES LOW ONLY AFFTER THE SECOND NIBBLE IS RECEIVED.
LINK PORT ENABLE/THREE-STATE DELAY FROM INSTRUCTION
CLKIN
LCLK
LDAT(3:0)
LACK
t
ENDLK
LINK PORT ENABLE OR THREE-STATE TAKES EFFECT 2 CYCLES AFTER A WRITE TO A LINK PORT CONTROL REGISTER.
t
TDLK
t
HLACH
t
DLALC
t
DLACLK
LINK PORT INTERRUPT SETUP TIME
CLKIN
t
SLCK
LCLK
LACK
t
HLCK
Figure 22. Link Ports
–32–
REV. A
AD14060/AD14060L
Serial Ports
5 V 3.3 V
Parameter Min Max Min Max Units External Clock
Timing Requirements:
t
SFSE
t
HFSE
t
SDRE
t
HDRE
t
SCLKW
t
SCLK
TFS/RFS Setup Before TCLK/RCLK TFS/RFS Hold After TCLK/RCLK Receive Data Setup Before RCLK Receive Data Hold After RCLK TCLK/RCLK Width 9.5 9 ns TCLK/RCLK Period t
Internal Clock
Timing Requirements:
t
SFSI
t
HFSI
t
SDRI
t
HDRI
TFS Setup Before TCLK1; RFS Setup Before RCLK199ns TFS/RFS Hold After TCLK/RCLK Receive Data Setup Before RCLK Receive Data Hold After RCLK
External or Internal Clock
Switching Characteristics:
t
DFSE
t
HFSE
RFS Delay After RCLK (Internally Generated RFS) RFS Hold After RCLK (Internally Generated RFS)333ns
External Clock
Switching Characteristics:
t
DFSE
t
HFSE
t
DDTE
t
HDTE
TFS Delay After TCLK (Internally Generated TFS) TFS Hold After TCLK (Internally Generated TFS)333ns Transmit Data Delay After TCLK Transmit Data Hold After TCLK
Internal Clock
Switching Characteristics:
t
DFSI
t
HFSI
t
DDTI
t
HDTI
t
SCLKIW
TFS Delay After TCLK (Internally Generated TFS) TFS Hold After TCLK (Internally Generated TFS)3–1.5 –1.5 ns Transmit Data Delay After TCLK Transmit Data Hold After TCLK TCLK/RCLK Width (SCLK/2) – 2 (SCLK/2) + 2 (SCLK/2) – 2.5 (SCLK/2) + 2.5 ns
Enable and Three-State
Switching Characteristics:
t
DDTEN
t
DDTTE
t
DDTIN
t
DDTTI
t
DCLK
t
DPTR
Data Enable from External TCLK Data Disable from External TCLK Data Enable from Internal TCLK Data Disable from Internal TCLK TCLK/RCLK Delay from CLKIN 23 + 3DT/8 23 + 3DT/8 ns SPORT Disable After CLKIN 18 18 ns
External Late Frame Sync
Switching Characteristics:
t
DDTLFSE
Data Delay from Late External TFS or 13 13.8 ns External RFS with MCE = 1, MFD = 0
t
DDTENFS
Data Enable from late FS or MCE = 1, MFD = 043.0 3.5 ns
1
1, 2
1
1
1, 2
1
1
3
3
3
3
3
3
3
3
4
44ns
4.5 4.5 ns 22ns
4.5 4.5 ns
CK
t
CK
ns
11ns 44ns 33ns
3
3
14 14 ns
14 14 ns
17 17 ns
55ns
3
55ns
88ns
00ns
3.5 4 ns
11.5 11.5 ns
00ns
33ns
To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) SCLK width.
NOTES
1
Referenced to sample edge.
2
RFS hold after RCK when MCE = 1, MFD = 0 is 0.5 ns minimum from drive edge. TFS hold after TCK for late external TFS is 0.5 ns minimum from drive edge.
3
Referenced to drive edge.
4
MCE = 1, TFS enable and TFS valid follow t
REV. A
DDTLFSE
and t
DDTENFS
.
–33–
AD14060/AD14060L
EXTERNAL RFS with MCE = 1, MFD = 0
DRIVE SAMPLE
RCLK
t
SFSE/I
RFS
t
DDTENFS
DT
t
DDTLFSE
t
1ST BIT 2ND BIT
LATE EXTERNAL TFS
HDTE/I
DRIVE
t
HFSE/I
t
DDTE/I
(SEE NOTE 2)
TCLK
TFS
DRIVE SAMPLE
DT
t
DDTLFSE
DRIVE
t
HFSE/I
t
(SEE NOTE 2)
DDTE/I
t
SFSE/I
t
DDTENFS
t
HDTE/I
1ST BIT 2ND BIT
Figure 23. External Late Frame Sync
–34–
REV. A
AD14060/AD14060L
DATA RECEIVE– INTERNAL CLOCK
DRIVE
RCLK
RFS
DR
EDGE
t
HFSE
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
t
DFSE
t
SCLKIW
t
SFSI
t
SDRI
DATA TRANSMIT– INTERNAL CLOCK
DRIVE
TCLK
TFS
DT
EDGE
t
t
HFSI
HDTI
t
t
DFSI
DDTI
t
SCLKIW
t
SFSI
SAMPLE
EDGE
SAMPLE
EDGE
t
HFSI
t
HDRI
t
HFSI
DATA RECEIVE– EXTERNAL CLOCK
DRIVE
RCLK
RFS
DR
EDGE
t
HFSE
t
DFSE
t
SCLKW
t
SFSE
t
SDRE
DATA TRANSMIT– EXTERNAL CLOCK
DRIVE
TCLK
TFS
DT
EDGE
t
HFSE
t
HDTE
t
DFSE
t
DDTE
t
SCLKW
t
SFSE
SAMPLE
EDGE
SAMPLE
EDGE
t
t
t
HFSE
HDRE
HFSE
TCLK (EXT)
CLKIN
TCLK, RCLK
TFS, RFS, DT
TCLK (INT) RCLK (INT)
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DRIVE
EDGE
t
DDTEN
DT
DRIVE EDGE
t
DDTIN
DT
SPORT DISABLE DELAY
FROM INSTRUCTION
LOW TO HIGH ONLY
t
DCLK
t
DPTR
SPORT ENABLE AND THREE-STATE LATENCY IS TWO CYCLES
TCLK / RCLK
TCLK / RCLKTCLK (INT)
CLKIN
TFS (EXT)
NOTE: APPLIES ONLY TO GATED SERIAL CLOCK MODE WITH EXTERNAL TFS, AS USED IN THE SERIAL PORT SYSTEM I/O FOR MESH MULTIPROCESSING.
DRIVE EDGE
DRIVE EDGE
t
DDTTI
t
DDTTE
t
STFSCK
t
HTFSCK
REV. A
Figure 24. Serial Ports
–35–
AD14060/AD14060L
JTAG Test Access Port and Emulation
5 V 3.3 V
Parameter Min Max Min Max Units
Timing Requirements:
t
TCK
t
STAP
t
HTAP
t
SSYS
t
HSYS
t
TRSTW
Switching Characteristics:
t
DTDO
t
DSYS
NOTES
1
System Inputs = DATA TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT
2
System Outputs = DATA DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT
TCK Period t
CK
t
CK
ns TDI, TMS Setup Before TCK High 5 5 ns TDI, TMS Hold After TCK High 6 6 ns System Inputs Setup Before TCK Low System Inputs Hold After TCK Low TRST Pulsewidth 4t
TDO Delay from TCK Low 13 13 ns System Outputs Delay After TCK Low
, ADDR
47-0
47-0
OUTPUTS
, ADDR
SYSTEM
SYSTEM
, RD, WR, ACK, SBTS, SW, HBR, HBG, CS, DMAR1, DMAR2, BR
31-0
, MS
, RD, WR, ACK, PAGE, ADRCLK, SW, HBG, REDY, DMAG1, DMAG2, BR
3-0
TCK
TMS
TDI
TDO
INPUTS
31-0
t
DTDO
1
1
2
, LxCLK, LxACK, EBOOT, LBOOT, BMS, CLKIN, RESET.
3-0
t
STAP
t
DSYS
88ns
18.5 19 ns
CK
20 20 ns
6-1
, LxCLK, LxACK, BMS.
3-0
t
TCK
t
HTAP
t
SSYS
4t
, RPBA, IRQ
CK
, FLAG2-0, DR0, DR1, TCLK0,
2-0
t
HSYS
, CPA, FLAG
6-1
, TIMEXP, DT0,
2-0
ns
Figure 25. IEEE 11499.1 JTAG Test Access Port
–36–
REV. A
AD14060/AD14060L

OUTPUT DRIVE CURRENTS

Figure 26 shows typical I-V characteristics for the output drivers of the ADSP-2106x. The curves represent the current drive capability of the output drivers as a function of output voltage.
120 100
80 60 40 20
0 –20 –40 –60 –80
SOURCE CURRENT – mA
–100 –120 –140 –160
0 51 2 3 4
HIGH LEVEL DRIVE
(P DEVICE)
LOW LEVEL DRIVE
(N DEVICE)
SOURCE VOLTAGE – V
Figure 26. ADSP-2106x Typical Drive Currents (VDD = 5 V)

POWER DISSIPATION

Total power dissipation has two components, one due to inter­nal circuitry and one due to the switching of external output drivers. Internal power dissipation is dependent on the instruc­tion execution sequence and the data operands involved. Inter­nal power dissipation is calculated in the following way:
P
INT
= I
DDIN
× V
DD
The external component of total power dissipation is caused by the switching of output pins. Its magnitude depends on:
– the number of output pins that switch during each cycle (O) – the maximum frequency at which they can switch (f) – their load capacitance (C) – their voltage swing (V
DD
)
and is calculated by:
= O × C × V
P
EXT
DD
2
× f
The load capacitance should include the processor’s package capacitance (C
). The switching frequency includes driving the
IN
load high and then back low. Address and data pins can drive high and low at a maximum rate of 1/(2t can switch every cycle at a frequency of 1/t at 1/(2t
), but selects can switch on each cycle.
CK
). The write strobe
CK
. Select pins switch
CK
Example:
Estimate P
with the following assumptions:
EXT
–A system with one bank of external data memory RAM (32-bit) –Four 128K × 8 RAM chips are used, each with a load of 10 pF –External data memory writes occur every other cycle, a rate
of 1/(4t
–The instruction cycle rate is 40 MHz (t
V
DD
), with 50% of the pins switching
CK
= 5.0 V.
= 25 ns) and
CK
The P
equation is calculated for each class of pins that can
EXT
drive:
Pin # of % Type Pins Switching 3 C 3 f 3 V
Address 15 50 × 55 pF × 20 MHz × 25 V = 0.206 W
MS0 10 × 55 pF × 20 MHz × 25 V = 0.00 W WR 1– × 55 pF × 40 MHz × 25 V = 0.055 W
Data 32 50 × 25 pF × 20 MHz × 25 V = 0.200 W ADRCLK 1 × 15 pF 40 MHz × 25 V = 0.015 W
P
P
2
= P
DD
(5 V) = 0.476 W
EXT
(3.3 V) = 0.207 W
EXT
EXT
A typical power consumption can now be calculated for these conditions by adding a typical internal power dissipation:
P
= P
TOTAL
EXT
+ (I
Note that the conditions causing a worst-case P from those causing a worst-case P
× 5.0 V )
DDIN2
. Maximum P
INT
are different
EXT
cannot
INT
occur while 100% of the output pins are switching from all ones to all zeros. Also note that it is not common for an application to have 100% or even 50% of the outputs switching simultaneously.
TEST CONDITIONS Output Disable Time
Output pins are considered to be disabled when they stop driv­ing, go into a high impedance state, and start to decay from their output high or low voltage. The time for the voltage on the bus to decay by V is dependent on the capacitive load, C the load current, I
. This decay time can be approximated by
L
, and
L
the following equation:
V
C
t
DECAY
The output disable time, t and t
as shown in Figure 27. The time t
DECAY
DIS
L
=
I
L
, is the difference between t
MEASURED
MEASURED
is the interval from when the reference signal switches to when the output voltage decays V from the measured output high or output low voltage. t I
, and with V equal to 0.5 V.
L
is calculated with test loads CL and
DECAY
Output Enable Time
Output pins are considered to be enabled when they have made a transition from a high impedance state to when they start driving. The output enable time, t
, is the interval from when
ENA
a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in the Output Enable/Disable diagram (Figure 27). If multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving.
Example System Hold Time Calculation
To determine the data output hold time in a particular system, first calculate t
using the equation given above. Choose
DECAY
V to be the difference between the ADSP-2106x’s output voltage and the input threshold for the device requiring the hold time. A typical V will be 0.4 V. C (per data line), and I
is the total leakage or three-state current
L
is the total bus capacitance
L
REV. A
–37–
AD14060/AD14060L
(per data line). The hold time will be t disable time (i.e., t
REFERENCE
SIGNAL
t
DIS
V
OH (MEASURED)
V
OL (MEASURED)
OUTPUT STOPS
DRIVING
for the write cycle).
HDWD
t
MEASURED
V
OH (MEASURED)
V
OL (MEASURED)
t
DECAY
HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE THIS VOLTAGE TO BE APPROXIMATELY 1.5V
DECAY
V
+ V
OUTPUT STARTS
Figure 27. Output Enable/Disable
I
OL
TO
OUTPUT
PIN
50pF
I
OH
plus the minimum
t
ENA
V
+1.5V
OH (MEASURED)
V
OL (MEASURED)
2.0V
1.0V
DRIVING
16.0
14.0
12.0
10.0
8.0
6.0
(0.5V – 4.5V, 10% – 90%)
RISE AND FALL TIMES – ns
4.0
3.7
2.0
1.1 0
0 20020 40 60 80 100 120 140 160 180
RISE TIME
FALL TIME
LOAD CAPACITANCE – pF
Figure 30. Typical Output Rise Time (10%–90% VDD)
vs. Load Capacitance (V
3.5
3.0
2.5
2.0
1.5
1.0
0.6
0.5
RISE AND FALL TIMES – ns (0.8V–2.0V)
= 5 V)
DD
RISE TIME
FALL TIME
14.7
7.4
2.9
1.6
Figure 28. Equivalent Device Loading for AC Measure­ments (Includes All Fixtures)
INPUT OR
OUTPUT
1.5V
1.5V
Figure 29. Voltage Reference Levels for AC Measure­ments (Except Output Enable/Disable)
Capacitive Loading
Output delays and holds are based on standard capacitive loads: 50 pF on all pins (see Figure 28). The delay and hold specifica­tions given should be derated by a factor of 1.5 ns/50pF for loads other than the nominal value of 50 pF. Figures 30 and 31 show how output rise time varies with capacitance. Figure 32 graphically shows how output delays and holds vary with load capacitance. (Note that this graph or derating does not apply to output disable delays; see the previous section Output Disable Time under Test Conditions.) The graphs of Figures 30, 31 and 32 may not be linear outside the ranges shown.
0020 40 60 80 100 120
LOAD CAPACITANCE – pF
140 160 180 200
Figure 31. Typical Output Rise Time (0.8 V –2.0 V)
vs. Load Capacitance (V
5
4
3
2
1
OUTPUT DELAY OR HOLD – ns
NOMINAL
–0.7
–1
25 20050 75 100 125 150 175
= 5 V)
DD
LOAD CAPACITANCE – pF
Figure 32. Typical Output Delay or Hold vs. Load Capacitance (at Maximum Case Temperature) (V
DD
4.5
= 5 V)
–38–
REV. A
AD14060/AD14060L
0.170
(4.318)
2.110 (53.59)
2.210 ±0.010 (56.134 ±0.254)
0.016 MIN
0 TO 10 MILS
0° TO 8°
DETAIL "A"
18
16
14
12
10
8
6
4
RISE AND FALL TIMES – ns (10% – 90%)
2
0
0
20 40 60 80 100 120
Y = 0.0796X + 1.17
RISE TIME
Y = 0.0467X + 0.55
FALL TIME
140 160 180 200
LOAD CAPACITANCE – pF
Figure 33. Typical Output Rise Time (10%–90% VDD) vs. Load Capacitance (V
9
8
7
6
5
4
3
2
RISE AND FALL TIMES – ns (0.8V – 2.0V)
1
= 3.3 V)
DD
Y = 0.0391X + 0.36
RISE TIME
Y = 0.0305X + 0.24
FALL TIME
AD14060/AD14060L ASSEMBLY RECOMMENDATIONS
SOCKET INFORMATION
Standard sockets and carriers are available for the AD14060/ AD14060L, if needed. Socket part number IC53-3084-262 and carrier part number ICC-308-1 are available from Yamaichi Electronics.
Trim and Form
The AD14060/AD14060L will be shipped as shown on the final page of the data sheet with untrimmed and unformed leads and with the nonconductive tie bar in place. This avoids disturbance of lead spacing and coplanarity prior to assembly. Optimally, the leads should be trimmed, formed and solder-dipped just prior to placement on the board.
Trim/Form can be accomplished with a Universal Trim/Form, Customer-Designed Trim/Form, or with the Analog Devices’ Developed Tooling described below.
A trim/form tool specific to the AD14060/AD14060L has been developed and is available for use by all parties at:
Tintronics Industries 2122-A Metro Circle Huntsville, AL 35801 205-650-0220 Contact Person: Tom Rice
The package outline and dimensions resulting from this tool are shown below. (Alternatively, the package can also be trimmed/ formed for cavity-down placement.)
0020 40 60 80 100 120
LOAD CAPACITANCE – pF
140 160 180 200
Figure 34. Typical Output Rise Time (0.8 V –2.0 V) vs. Load Capacitance (V
5
4
3
2
1
OUTPUT DELAY OR HOLD – ns
NOMINAL
–0.7
–1
25 20050 75 100 125 150 175
= 3.3 V)
DD
Y = 0.0329X - 1.65
LOAD CAPACITANCE – pF
4.5
Figure 35. Typical Output Delay or Hold vs. Load Capaci­tance (at Maximum Case Temperature) (V
= 3.3 V)
DD
REV. A
–39–
AD14060/AD14060L

PCB LAYOUT GUIDELINES

The drawing below assumes that the trim/form tooling described above is used. These recommendations are provided for user convenience and are recommendations only, based on stan­dard practice. PCB pad footprint geometries and placement are illustrated.
2.260 (57.404) 4 PLACES
2.060 (52.324) 4 PLACES
1.9000 (48.26) 4 PLACES
THIS IS A PC BOARD COMPONENT
FOOTPRINT, NOT THE PACKAGE
OUTLINE.
NOTE: These drawings are recommended PCB layout guide­lines only, and they assume that the trim/form tooling described above is used.
0.015 (0.381)
0.025 (0.635)
0.025 (0.635) MIN 0.025 (0.635) MIN
–40–
REV. A
AD14060/AD14060L
Thermal Characteristics
The AD14060/AD14060L is packaged in a 308-lead ceramic quad flatpack (CQFP). The package is optimized for thermal conduction through the core (base of the package) down to the mounting surface. The AD14060/AD14060L is specified for a case temperature (T attachment material should be such that T
). Design of the mounting surface and
CASE
= 0.36°C/W
θ
JC
is not exceeded.
CASE
Thermal Cross-Section
The data below, together with the detailed mechanical drawings at the end of the data sheet, allows for constructing simple ther­mal models for further analysis within targeted systems. The top layer of the package, where the die are mounted, is a metal V
DD
layer. The approximate metal area coverage from the metal planes and routing layers is estimated below.
Thermal Conductivity
Thermal Conductivity
Material W/cm8C
Ceramic 0.18 Kovar 0.14 Tungsten 1.78 Thermoplastic 0.03 Silicon 1.45
Metal Coverage Per Layer
Percent Metal
Layer (1 Mil Thick)
V
DD
88 SIG2 16 SIG3 14 GND 91 SIG4 15 SIG5 13 BASE 95
SILICON DIE
19 MILS
THERMOPLASTIC
THICKNESS 5 MILS
V
DD
SIG2 SIG3
GND SIG4
SIG5
BASE
KOVAR LID
0.015 MILS
KOVAR SEAL RING
HEIGHT = 50 MILS
SURFACE
CERAMIC LAYER 28 MILS
CERAMIC LAYER 6 MILS CERAMIC LAYER 6 MILS
CERAMIC LAYER 10 MILS CERAMIC LAYER 4 MILS CERAMIC LAYER 10 MILS
CERAMIC LAYER 10 MILS CERAMIC LAYER 4 MILS CERAMIC LAYER 10 MILS CERAMIC LAYER 4 MILS
REV. A
–41–
AD14060/AD14060L

MECHANICAL CHARACTERISTICS

Lid Deflection Analysis
External Pressure Reduction
Delta Pressure Deflection
12 psi 10.0 mil 15 psi 11.9 mil
Mechanical Model
The data below, together with the detailed mechanical drawings at the end of the data sheet, allows for construction of simple mechanical models for further analysis within targeted systems.
Mechanical Properties
0.302
0.670 4X
0.616
0.633
0.653 4X
2.050 SQ.
Material Modulus of Elasticity
Ceramic 26 × 10
3
Kovar 14.1 × 103 kg/mm Tungsten 35 × 103 kg/mm Thermoplastic 279 kg/mm Silicon 11 × 103 kg/mm
kg/mm
2
2
2
2
2
308-LEAD CQFP PIN CONFIGURATION
308
1
0.260
AD14060/AD14060L
TOP VIEW
0.250 0.345
1.890 ±0.005
1.810 ±0.005
1.780 ±0.018
0.040 ±0.002
232
231
0.012 REF 4X
77
78
–42–
154
155
REV. A
AD14060/AD14060L
PIN CONFIGURATIONS
Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin No. Name No. Name No. Name No. Name No. Name No. Name No. Name
1 WR 45 GND 89 ADDR13 133 IRQB0 177 LC4DAT2 221 GND 265 GND 2 RD 46 RFSD1 90 ADDR12 134 IRQB1 178 LC4DAT3 222 LA3ACK 266 DATA24 3 GND 47 RCLKD1 91 ADDR11 135 IRQB2 179 GND 223 LA3CLK 267 DATA25 4 CSA 48 DRD1 92 GND 136 GND 180 LC3ACK 224 LA3DAT0 268 DATA26 5 CSB 49 TFSD1 93 ADDR10 137 IRQC0 181 LC3CLK 225 LA3DAT1 269 DATA27 6 CSC 50 TCLKD1 94 ADDR9 138 IRQC1 182 LC3DAT0 226 LA3DAT2 270 V 7 CSD 51 DTD1 95 ADDR8 139 IRQC2 183 LC3DAT1 227 LA3DAT3 271 DATA28 8 GND 52 V
DD
96 V
DD
140 IRQD0 184 LC3DAT2 228 V
DD
9 HBG 53 HBR 97 ADDR7 141 IRQD1 185 LC3DAT3 229 LA1ACK 273 DATA30 10 REDY 54 DMAR1 98 ADDR6 142 IRQD2 186 V 11 ADRCLK 55 DMAR2 99 ADDR5 143 V 12 V
DD
56 SBTS 100 GND 144 EBOOTA 188 LC1CLK 232 LA1DAT1 276 DATA32
DD
187 LC1ACK 231 LA1DAT0 275 GND
DD
230 LA1CLK 274 DATA31
13 RFS0 57 BMSA 101 ADDR4 145 LBOOTA 189 LC1DAT0 233 LA1DAT2 277 DATA33 14 RCLK0 58 BMSBCD 102 ADDR3 146 EBOOTBCD 190 LC1DAT1 234 LA1DAT3 278 DATA34 15 DR0 59 SW 103 ADDR2 147 LBOOTBCD 191 LC1DAT2 235 GND 279 DATA35 16 TFS0 60 GND 104 V
DD
148 GND 192 LC1DAT3 236 DATA0 280 V 17 TCLK0 61 MS0 105 ADDR1 149 RESET 193 GND 237 DATA1 281 DATA36 18 DT0 62 MS1 106 ADDR0 150 RPBA 194 LB4ACK 238 DATA2 282 DATA37 19 GND 63 MS2 107 FLAGA0 151 GND 195 LB4CLK 239 DATA3 283 DATA38 20 CPAA 64 MS3 108 GND 152 LD4ACK 196 LB4DAT0 240 V 21 CPAB 65 V
DD
109 FLAGA2 153 LD4CLK 197 LB4DAT1 241 DATA4 285 GND
DD
22 CPAC 66 ADDR31 110 FLAGB0 154 LD4DAT0 198 LB4DAT2 242 DATA5 286 DATA40 23 CPAD 67 ADDR30 111 FLAGB2 155 LD4DAT1 199 LB4DAT3 243 DATA6 287 DATA41 24 V
DD
68 ADDR29 112 FLAGC0 156 LD4DAT2 200 V
DD
244 DATA7 288 CLKIN 25 RFSA1 69 GND 113 FLAGC2 157 LD4DAT3 201 LB3ACK 245 GND 289 GND 26 RCLKA1 70 ADDR28 114 FLAGD0 158 V
DD
202 LB3CLK 246 DATA8 290 DATA42 27 DRA1 71 ADDR27 115 FLAGD2 159 LD3ACK 203 LB3DAT0 247 DATA9 291 DATA43 28 TFSA1 72 ADDR26 116 V 29 TCLKA1 73 V
DD
DD
117 FLAG1 161 LD3DAT0 205 LB3DAT2 249 DATA11 293 DATA44
30 DTA1 74 ADDR25 118 EMU 162 LD3DAT1 206 LB3DAT3 250 V
160 LD3CLK 204 LB3DAT1 248 DATA10 292 V
DD
31 GND 75 ADDR24 119 TIMEXPA 163 LD3DAT2 207 GND 251 DATA12 295 DATA46 32 RFSB1 76 ADDR23 120 TIMEXPB 164 LD3DAT3 208 LB1ACK 252 DATA13 296 DATA47 33 RCLKB1 77 ADDR22 121 TIMEXPC 165 GND 209 LB1CLK 253 DATA14 297 GND 34 DRB1 78 ADDR21 122 TIMEXPD 166 LD1ACK 210 LB1DAT0 254 DATA15 298 BR1 35 TFSB1 79 ADDR20 123 GND 167 LD1CLK 211 LB1DAT1 255 GND 299 BR2 36 TCLKB1 80 V
DD
124 TDO 168 LD1DAT0 212 LB1DAT2 256 DATA16 300 BR3 37 DTB1 81 ADDR19 125 TRST 169 LD1DAT1 213 LB1DAT3 257 DATA17 301 BR4 38 V
DD
82 ADDR18 126 TDI 170 LD1DAT2 214 V
DD
258 DATA18 302 BR5 39 RFSC1 83 ADDR17 127 TMS 171 LD1DAT3 215 LA4ACK 259 DATA19 303 BR6 40 RCLKC1 84 GND 128 TCK 172 V 41 DRC1 85 ADDR16 129 V
DD
173 LC4ACK 217 LA4DAT0 261 DATA20 305 V
DD
216 LA4CLK 260 V
DD
42 TFSC1 86 ADDR15 130 IRQA0 174 LC4CLK 218 LA4DAT1 262 DATA21 306 DMAG1 43 TCLKC1 87 ADDR14 131 IRQA1 175 LC4DAT0 219 LA4DAT2 263 DATA22 307 DMAG2 44 DTC1 88 V
DD
132 IRQA2 176 LC4DAT1 220 LA4DAT3 264 DATA23 308 ACK
DD
272 DATA29
DD
284 DATA39
DD
294 DATA45
304 PAGE
DD
REV. A
–43–
AD14060/AD14060L

ORDERING GUIDE

Part Number Case Temperature Range SMD Instruction Rate Operating Voltage
AD14060BF-4 –40°C to +100°C N/A 40 MHz 5 V AD14060LBF-4 –40°C to +100°C N/A 40 MHz 3.3 V 5962-9750601HXC –40°C to +100°C QML-H 40 MHz 5 V 5962-9750701HXC* –40°C to +100°C QML-H 40 MHz 3.3 V
*Part numbers marked with an * are shipping as x-grade (preproduction) material at the time of this printing. These parts are packaged in a 308-lead Ceramic Quad
Flatpack Package (CQFP). MIL-SMD parts, in the same package, are in development.

PACKAGE DIMENSIONS

Dimensions shown in inches and (mm).
308-Lead Ceramic Quad Flatpack (CQFP)
(QS-308)
3.050 (77.47) MAX
3.000 60.010 (76.2 60.254)
0.340 60.010
60.254)
(8.636
4x
2.730 60.015 (69.34 60.381)
2.050 60.012 (52.07 60.305)
C3225–7–10/97PRINTED IN U.S.A.
2.300 60.030
(58.42
0.092 60.009
(2.337
60.229)
60.762)
(0.889)
0.035 MAX
232
308
0.040 (1.016) x 45
0.015 (0.381) x 45
155231
154
TOP VIEW
78
1
°
1.890 60.005
(48.006
60.127)
77
0.005 +0.0015 –0.001 (0.127 +0.0381 –0.025)
3 PLACES
0.008 60.002 (0.203
0.025 (0.635) TYP
0.160 (4.064) MAX
°
60.051)
–44–
REV. A
Loading...