Analog Devices AD14060L, AD14060 Datasheet
Quad-SHARC
®
a
PERFORMANCE FEATURES
...
ADSP-21060 Core Processor (
480 MFLOPS Peak, 320 MFLOPS Sustained
25 ns Instruction Rate, Single-Cycle
Instruction Execution–Each of Four Processors
16 Mbit Shared SRAM (Internal to SHARCs)
4 Gigawords Addressable Off-Module Memory
Twelve 40 Mbyte/s Link Ports (Three per SHARC)
Four 40 Mbit/s Independent Serial Ports (One from
Each SHARC)
One 40 Mbit/s Common Serial Port
5 V and 3.3 V Operation
32-Bit Single Precision and 40-Bit Extended
Precision IEEE Floating Point Data Formats, or
32-Bit Fixed Point Data Format
IEEE JTAG Standard 1149.1 Test Access Port and
On-Chip Emulation
PACKAGING FEATURES
308-Lead Ceramic Quad Flatpack (CQFP)
2.05" (52 mm) Body Size
Cavity Up or Down, Configurable
Low Profile, 0.160" Height
Hermetic
25 Mil (0.65 mm) Lead Pitch
29 Grams (typical)
= 0.368C/W
u
JC
34)
CPA
SPORT 1
TDI
EBOOT,
AD14060/
AD14060L
EBOOT,
CPA
SPORT 1
TDO
DSP Multiprocessor Family
AD14060/AD14060L
FUNCTIONAL BLOCK DIAGRAM
2,0
CS
TIMEXP
SHARC_A
(ID
LBOOT, BMS
EMU
CLKIN
EMU
CLKIN
LBOOT, BMS
SHARC_D
(ID
CS
TIMEXP
2-0
LINK 1
2-0
LINK 0
IRQ
LINK 1
LINK 3
LINK 4
FLAG
LINK 2
= 1)
2-0
RESET
RESET
= 4)
LINK 3
LINK 5
TDO
1
3
SPORT 0
TCK, TMS, TRST
FLAG
FLAG
SHARC BUS (
SBTS, HBR, HBG, REDY, BR
SPORT 0
LINK 4
ADDR
1
3
FLAG
FLAG
LINK 0
TCK, TMS, TRST
LINK 2
LINK 5
2,0
2-0
TDI
IRQ
FLAG
31-0
,
DATA
CS
LINK 0
LINK 2
LINK 5
TDI
47-0,
LINK 0
LINK 2
LINK 5
TDO
EBOOT,
MS
EBOOT,
LINK 1
TIMEXP
SHARC_B
(ID
2-0
LBOOT, BMS
EMU
CLKIN
RESET
,
RD, WR, PAGE, ADRCLK, SW, ACK,
3-0
, RPBA, DMAR
6-1
EMU
CLKIN
RESET
LBOOT, BMS
SHARC_C
(ID
2-0
CS
TIMEXP
LINK 1
LINK 3
= 2)
= 3)
LINK 3
2,0
2-0
IRQ
LINK 4
FLAG
SPORT 1
1
SPORT 0
TCK, TMS, TRST
FLAG
, DMAG
1.2
1
FLAG
SPORT 0
TCK, TMS, TRST
SPORT 1
2,0
2-0
LINK 4
IRQ
FLAG
CPA
FLAG3TDO
)
1.2
3
FLAG
CPA
TDI
GENERAL DESCRIPTION
The AD14060/AD14060L Quad-SHARC is the first in a family
of high performance DSP multiprocessor modules. The core of
the multiprocessor is the ADSP-21060 DSP microcomputer.
The AD14060/AD14060L modules have the highest performance —density and lowest cost—performance ratios of any in
their class. They are ideal for applications requiring higher levels
of performance and/or functionality per unit area.
The AD14060/AD14060L takes advantage of the built-in multiprocessing features of the ADSP-21060 to achieve 480 peak
MFLOPS with a single chip type, in a single package. The onchip SRAM of the DSPs provides 16 Mbits of on-module
shared SRAM. The complete shared bus (48 data, 32 address)
is also brought off-module for interfacing with expansion
memory or other peripherals.
SHARC is a registered trademark of Analog Devices, Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
The ADSP-21060 link ports are interconnected to provide
direct communication among the four SHARCs as well as high
speed off-module access. Internally, each SHARC has a direct
link port connection. Externally, each SHARC has a total of
120 Mbytes/s link port bandwidth.
Multiprocessor performance is enhanced with embedded power
and ground planes, matched impedance interconnect, and optimized signal routing lengths and separation. The fully tested
and ready-to-insert multiprocessor also significantly reduces
board space.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1997
AD14060/AD14060L
DETAILED DESCRIPTION
Architectural Features
ADSP-21060 Core
The AD14060/AD14060L is based on the powerful ADSP-21060
(SHARC) DSP chip. The ADSP-21060 SHARC combines a
high performance floating-point DSP core with integrated, onchip system features including a 4 Mbit SRAM memory, host
processor interface, DMA controller, serial ports, and both link
port and parallel bus connectivity for glueless DSP multiprocessing, (see Figure 1). It is fabricated in a high speed, low power
CMOS process, and has a 25 ns instruction cycle time. The arithmetic/ logic unit (ALU), multiplier and shifter all perform singlecycle instructions, and the three units are arranged in parallel,
maximizing computational throughput.
The SHARC features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data, and the program memory (PM) bus transfers both instructions and data.
There is also an on-chip instruction cache which selectively
caches only those instructions whose fetches conflict with the
PM bus data accesses. This combines with the separate program
and data memory buses to enable three-bus operation for fetching an instruction and two operands, all in a single cycle. The
SHARC also contains a general purpose data register file, which
is a 10-port, 32-register (16 primary, 16 secondary) file. Each
SHARC’s core also implements two data address generators
(DAGs), implementing circular data buffers in hardware. The
DAGs contain sufficient registers to allow the creation of up to
32 circular buffers. The 48-bit instruction word accommodates a
variety of parallel operations, for concise programming. For example, the ADSP-21060 can conditionally execute a multiply, an
add, a subtract, and a branch, all in a single instruction.
The SHARCs contain 4 Mbits of on-chip SRAM each, organized as two blocks of 2 Mbits, which can be configured for
different combinations of code and data storage. The memory
can be configured as a maximum of 128K words of 32-bit data,
256K words of 16-bit data, 80K words of 48-bit instructions (or
40-bit data), or combinations of different word sizes up to
4 megabits. A 16-bit floating-point storage format is supported
which effectively doubles the amount of data that may be stored
on chip. Conversion between the 32-bit floating point and 16bit floating point formats is done in a single instruction. Each
memory block is dual-ported for single-cycle, independent
accesses by the core processor and I/O processor or DMA controller. The dual-ported memory and separate on-chip buses
allow two data transfers from the core and one from I/O, all in a
single cycle.
Shared Memory Multiprocessing
The AD14060/AD14060L takes advantage of the powerful
multiprocessing features built into the SHARC. The SHARCs are
connected to maximize the performance of this cluster-of-four
architecture, and still allow for off-module expansion. The
AD14060/AD14060L in itself is a complete shared memory
multiprocessing system, as shown in Figure 3. The unified address space of the SHARCs allows direct interprocessor accesses of each SHARCs’ internal memory. In other words, each
SHARC can directly access the internal memory and IOP registers
of each of the other SHARCs by simply reading or writing to the
appropriate address in multiprocessor memory space (see Figure
2)—this is called a direct read or direct write.
DAG1
8 x 4 x 32
BUS
CONNECT
(PX)
CORE PROCESSOR
TIMER
DAG2
8 x 4 x 24
DM ADDRESS BUS
PM DATA BUS
DM DATA BUS
DATA
REGISTER
FILE
16 x 40-BIT
BARREL
SHIFTER
INSTRUCTION
CACHE
32 x 48-BIT
PROGRAM
SEQUENCER
24PM ADDRESS BUS
32
48
40/32
ALUMULTIPLIER
DUAL-PORTED SRAM
TWO INDEPENDENT
DUAL-PORTED BLOCKS
PROCESSOR PORT I/O PORT
ADDR DATA ADDR
ADDR DATA
DATA
IOP
REGISTERS
MEMORY MAPPED)
(
CONTROL,
STATUS, AND
DATA BUFFERS
DATA
IOD
48
I/O PROCESSOR
Figure 1. ADSP-21060 Processor Block Diagram (Core of the AD14060)
BLOCK 0
BLOCK 1
ADDR
IOA
17
DMA
CONTROLLER
SERIAL PORTS
(2)
LINK PORTS
(6)
JTAG
TEST AND
EMULATION
EXTERNAL
PORT
ADDR BUS
MUX
MULTIPROCESSOR
INTERFACE
DATA BUS
MUX
HOST PORT
4
6
6
36
7
32
48
–2–
REV. A
AD14060/AD14060L
INTERNAL
MEMORY
SPACE
(INDIVIDUAL
SHARCs)
MULTIPROCESSOR
MEMORY SPACE
IOP REGISTERS
NORMAL WORD ADDRESSING
SHORT WORD ADDRESSING
INTERNAL MEMORY SPACE
OF SHARC_A
ID=001
INTERNAL MEMORY SPACE
OF SHARC_B
INTERNAL
TO AD14060
EXTERNAL
TO AD14060
NORMAL WORD ADDRESSING: 32-BIT DATA WORDS
48-BIT INSTRUCTION WORDS
SHORT WORD ADDRESSING: 16-BIT DATA WORDS
INTERNAL MEMORY SPACE
INTERNAL MEMORY SPACE
INTERNAL MEMORY SPACE
INTERNAL MEMORY SPACE
ID=010
OF SHARC_C
ID=011
OF SHARC_D
ID=100
OF ADSP-2106x
WITH ID=101
OF ADSP-2106x
WITH ID=110
BROADCAST WRITE
TO ALL
ADSP-2106xs
0x0000 0000
0x0002 0000
0x0004 0000
0x0008 0000
0x0010 0000
0x0018 0000
0x0020 0000
0x0028 0000
0x0030 0000
0x0038 0000
0x003F FFFF
EXTERNAL
MEMORY
SPACE
BANK 0
DRAM
(OPTIONAL)
BANK 1
BANK 2
BANK 3
NONBANKED
0x0040 0000
MS
0
MS
1
MS
2
MS
3
BANK SIZE IS
SELECTED BY
MSIZE BIT FIELD OF
SYSCON
REGISTER.
0xFFFF FFFF
Figure 2. AD14060/AD14060L Memory Map
SYSTEM EXPANSION
1X CLOCK
CLKIN
RESET
RPBA
CPA
BOOTSELECT A
BOOTSELECT BCD
DMAR1,2
DMAG1,2
SPORT0
FLAG1
JTAG
SHARC_A
LINKS 1, 3, & 4;
IRQ
FLAGS 2 & 0;
TIMEXP,
SPORT1
SHARC_D
LINKS 1, 3, & 4;
IRQ
FLAGS 2 & 0;
TIMEXP,
SPORT1
;
2-0
AD14060/AD14060L
(QUAD PROCESSOR
;
2-0
SHARC_B
LINKS 1, 3, & 4;
IRQ
FLAGS 2 & 0;
TIMEXP,
SPORT1
CLUSTER)
SHARC_C
LINKS 1, 3, & 4;
IRQ
FLAGS 2 & 0;
TIMEXP,
SPORT1
ADDR
31-0
;
2-0
;
2-0
DATA
ACK
MS
PAGE
SBTS
ADRCLK
HBR
HBG
REDY
BR
47-0
RD
WR
3-0
SW
CS
1-6
Figure 3. Complete Shared Memory Multiprocessing System
REV. A
–3–
AD14060/AD14060L
Bus arbitration is accomplished with the on-SHARC arbitration
logic. Each SHARC has a unique ID, and drives the Bus-Request
(BR) line corresponding to its ID, while monitoring all others.
BR1–BR4 are used within the AD14060/AD14060L, while BR5
and BR6 can be used for expansion. All bus requests (BR1–BR6)
are included in the module I/O.
Two different priority schemes, fixed and rotating, are available
to resolve competing bus requests. The RPBA pin selects which
scheme is used: when RPBA is high, rotating priority bus arbitration is selected, and when RPBA is low, fixed priority is selected.
Table I. Rotating Priority Arbitration Example
Hardware Processor IDs
Cycle ID1 ID2 ID3 ID4 ID5 ID6
1M12 BR345Initial Priority Assignments
2 4 5 BR M-BR 1 2 3
3 4 5 BR M 1 2 3
4 5 BR M 1 2 3 4 BR
51 BR2345MFinal Priority Assignments
NOTES
1–5 = Assigned Priority.
M = Bus Mastership (in that cycle).
BR = Requesting Bus Mastership with BRx.
Bus mastership is passed from one SHARC to another during a
bus transition cycle. A bus transition cycle only occurs when the
current bus master deasserts its BR line and one of the slave
SHARCs asserts its BR line. The bus master can therefore retain bus mastership by keeping its BR line asserted. When the
bus master deasserts its BR line, and no other BR line is asserted, then the master will not lose any bus cycles. When more
than one SHARC asserts its BR line, the SHARC with the
highest priority request becomes bus master on the following
cycle. Each SHARC observes all of the BR lines, and therefore
tracks when a bus transition cycle has occurred, and which
processor has become the new bus master. Master processor
changeover incurs only one cycle of overhead. An example bus
transition sequence is shown in Table I.
Bus locking is possible, allowing indivisible read-modify-write
sequences for semaphores. In either the fixed or rotating priority
scheme, it is also possible to limit the number of cycles the
master can control the bus. The AD14060/AD14060L also
provides the option of using the Core Priority Access (CPA)
mode of the SHARC. Using the CPA signal allows external bus
accesses by the core processor of a slave SHARC to take priority
over ongoing DMA transfers. Also, each SHARC can broadcast
write to all other SHARCs simultaneously, allowing the implementation of reflective semaphores.
The bus master can communicate with slave SHARCs by writing messages to their internal IOP registers. The MSRG0–
MSRG7 registers are general-purpose registers that can be used
for convenient message passing, semaphores and resource sharing between the SHARCs. For message passing, the master
communicates with a slave by writing and/or reading any of the
eight message registers on the slave. For vector interrupts, the
master can issue a vector interrupt to a slave by writing the
address of an interrupt service routine to the slave’s VIRPT
register. This causes an immediate high priority interrupt on the
slave which, when serviced, will cause it to branch to the specified service routine.
Off-Module Memory and Peripherals Interface
The AD14060/AD14060L’s external port provides the interface to
–4–
off-module memory and peripherals (see Figure 5). This port
consists of the complete external port bus of the SHARC, bused
together in common among the four SHARCs.
The 4-gigaword off-module address space is included in the
ADSP-14060’s unified address space. Addressing of external
memory devices is facilitated by each SHARC internally decoding the high order address lines to generate memory bank
select signals. Separate control lines are also generated for simplified addressing of page-mode DRAM. The AD14060/
AD14060L also supports programmable memory wait states and
external memory acknowledge controls to allow interfacing to
DRAM and peripherals with variable access, hold and disable
time requirements.
Link Port I/O
Each individual SHARC features six 4-bit link ports that facilitate SHARC-to-SHARC communication and external I/O interfacing. Each link port can be configured for either 1× or 2×
operation, allowing each to transfer either 4 or 8 bits per cycle.
The link ports can operate independently and simultaneously,
with a maximum bandwidth of 40 MBytes/s each, or a total of
240 MBytes/s per SHARC.
The AD14060/AD14060L optimizes the link port connections
internally, and brings a total of twelve of the link ports off-module for user-defined system connections. Internally, each SHARC
has a connection to the other three SHARCs with a dedicated
link port interface. Thus, each SHARC can directly interface
with its nearest and next-nearest neighbor. The remaining three
link ports from each SHARC are brought out independently
from each SHARC. A maximum of 480 MBytes/s link port
bandwidth is then available off of the AD14060/AD14060L.
The link port connections are detailed in Figure 4.
1
3
SHARC_A SHARC_B
4
0
0
1
3
SHARC_D SHARC_C
4
55
22
22
55
1
3
4
0
0
1
3
4
Figure 4. Link Port Connections
Link port 4, the boot link port, is brought off independently
from each SHARC. Individual booting is then allowed, or
chained link port booting is possible as described under “Link
Port Booting.”
Link port data is packed into 32-bit or 48-bit words, and can
be directly read by the SHARC core processor or DMAtransferred to on-SHARC memory.
Each link port has its own double-buffered input and output
registers. Clock/acknowledge handshaking controls link port
transfers. Transfers are programmable as either transmit or
receive.
REV. A
1x
CLOCK
RESET
101
CLKIN
RESET
RPBA
CONTROL
SERIALS
LINKS
DISCRETES
ADSP-2106x #5
CLKIN
RESET
RPBA
3
ID
2–0
AD14060/
AD14060L
ADDR
DATA
ADRCLK
(OPTIONAL)
ADDR
DATA
31–0
47–0
ACK
MS
BMS
PAGE
SBTS
HBR
HBG
REDY
CPA
BR
BR
31–0
47–0
RD
WR
3–0
SW
CS
2–6
AD14060/AD14060L
ADDR
GLOBAL
DATA
MEMORY
OE
WE
ACK
CS
CS
ADDR
DATA
5
1
ADDR
DATA
AND
PERIPHERALS
(OPTIONAL)
BOOT
EPROM
(OPTIONAL)
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
CONTROL
CPA
BR
BR
31–0
47–0
CPA
1–5
BR
5
5
5
6
110
ADSP-2106x #6
CLKIN
RESET
RPBA
3
ID
2–0
CONTROL
BR
1, 2, 3, 4, 6
(OPTIONAL)
ADDR
DATA
Figure 5. Optional System Interconnections
REV. A
–5–
AD14060/AD14060L
Serial Ports
The SHARC serial ports provide an inexpensive interface to a
wide variety of digital and mixed-signal peripheral devices. Each
SHARC has two serial ports. The AD14060/AD14060L provides
direct access to Serial Port 1 of each SHARC. Serial Port 0
is bused together in common to each SHARC, and brought
off-module.
The serial ports can operate at the full clock rate of the module,
providing each with a maximum data rate of 40 Mbit/s. Independent transmit and receive functions provide more flexible
communications. Serial port data can be automatically transferred to and from on-SHARC memory via DMA, and each of
the serial ports offers time division multiplexed (TDM) multichannel mode.
The serial ports can operate with little-endian or big-endian
transmission formats, with word lengths selectable from 3 bits to
32 bits. They offer selectable synchronization and transmit modes
as well as optional µ-law or A-law companding. Serial port clocks
and frame syncs can be internally or externally generated.
Program Booting
The AD14060/AD14060L supports automatic downloading of
programs following power-up or a software reset. The SHARC
offers four options for program booting: 1) from an 8-bit
EPROM; 2) from a host processor; 3) through the link ports;
and 4) no-boot. In no-boot mode, the SHARC starts executing
instructions from address 0x0040 0004 in external memory.
The boot mode is selected by the state of the following signals:
BMS, EBOOT, and LBOOT.
On the AD14060/AD14060L, SHARC_A’s boot mode is separately controlled, while SHARCs B, C, and D are controlled as
a group. With this flexibility, the AD14060/AD14060L can be
configured to boot in any of the following methods.
Multiprocessor Host Booting
To boot multiple ADSP-21060 processors from a host, each
ADSP-21060 must have its EBOOT, LBOOT and BMS pins
configured for host booting: EBOOT = 0, LBOOT = 0, and
BMS = 1. After system power-up, each ADSP-21060 will be in
the idle state and the BRx bus request lines will be deasserted.
The host must assert the HBR input and boot each ADSP-21060
by asserting its CS pin and downloading instructions.
Multiprocessor EPROM Booting
There are two methods of booting the multiprocessor system
from an EPROM.
SHARC_A Is Booted, Which Then Boots the Others. The
EBOOT pin on the SHARC_A must be set high for EPROM
booting. All other ADSP-21060s should be configured for host
booting (EBOOT = 0, LBOOT = 0, and BMS = 1), which
leaves them in the idle state at start-up and allows SHARC_A
to become bus master and boot itself. Only the BMS pin of
SHARC_A is connected to the chip select of the EPROM.
When SHARC_A has finished booting, it can boot the remaining ADSP-21060s by writing to their external port DMA
buffer 0 (EPB0) via multiprocessor memory space.
All ADSP-21060s Boot in Turn From a Single EPROM.
The BMS signals from each ADSP-21060 may be wire-ORed
together to drive the chip select pin of the EPROM. Each
ADSP-21060 can boot in turn, according to its priority. When
the last one has finished booting, it must inform the others
(which may be in the idle state) that program execution can begin.
Multiprocessor Link Port Booting
Booting can also be accomplished from a single source through
the link ports. Link Buffer 4 must always be used for booting.
To simultaneously boot all of the ADSP-21060s, a parallel
common connection is available through Link Port 4 on each of
the processors. Or, using the daisy chain connection that exists
between the processors’ link ports, each ADSP-21060 can boot
the next one in turn. In this case, the Link Assignment Register
(LAR) must be programmed to configure the internal link ports
with Link Buffer 4.
Multiprocessor Booting From External Memory
If external memory contains a program after reset, then
SHARC_A should be set up for no boot mode; it will begin executing from address 0x0040 0004 in external memory. When
booting has completed, the other ADSP-21060s may be booted
by SHARC_A if they are set up for host booting, or they can
begin executing out of external memory if they are set up for no
boot mode. Multiprocessor bus arbitration will allow this booting
to occur in an orderly manner.
Host Processor Interface
The AD14060/AD14060L’s host interface allows for easy connection to standard microprocessor buses, both 16-bit and 32bit, with little additional hardware required. Asynchronous
transfers at speeds up to the full clock rate of the module are
supported. The host interface is accessed through the AD14060/
AD14060L external port and is memory-mapped into the unified address space. Four channels of DMA are available for the
host interface; code and data transfers are accomplished with
low software overhead.
The host processor requests the AD14060/AD14060L’s external
bus with the host bus request (HBR), host bus grant (HBG),
and ready (REDY) signals. The host can directly read and write
the internal memory of the SHARCs, and can access the DMA
channel setup and mailbox registers. Vector interrupt support is
provided for efficient execution of host commands.
Direct Memory Access (DMA) Controller
The SHARCs on-chip DMA control logic allows zero-overhead
data transfers without processor intervention. The DMA controller operates independently and invisibly to each SHARCs
processor core, allowing DMA operations to occur while the core
is simultaneously executing its program instructions.
DMA transfers can occur between SHARC internal memory
and either external memory, external peripherals, or a host
processor. DMA transfers can also occur between the SHARC’s
internal memory and its serial ports or link ports. DMA transfers between external memory and external peripheral devices are
another option. External bus packing to 16-, 32- or 48-bit words
is performed during DMA transfers.
Ten channels of DMA are available on the SHARCs—two via
the link ports, four via the serial ports, and four via the processor’s
external port (for either host processor, other SHARCs, memory,
or I/O transfers). Four additional link port DMA channels are
shared with serial port 1 and the external port. Programs can be
downloaded to the SHARCs using DMA transfers. Asynchronous
off-module peripherals can control two DMA channels using
DMA Request/Grant lines (DMAR1-2, DMAG1-2). Other
DMA features include interrupt generation upon completion of
DMA transfers and DMA chaining for automatic linked DMA
transfers.
–6–
REV. A
AD14060/AD14060L
Development Tools
The ADSP-14060 is supported with a complete set of software
and hardware development tools, including an EZ-LAB
®
In-
Circuit Emulator, and development software.
Analog Devices’ ADSP-21000 Family Development Software
includes an easy to use Assembler based on an algebraic syntax,
an Assembly Library/Librarian, a Linker, an Instruction-Level
Simulator, an ANSI C optimizing Compiler, the CBug™ C
Source-Level Debugger, and a C Runtime Library including
DSP and mathematical functions. The Optimizing Compiler
includes Numerical C extensions based on the work of the ANSI
Numerical C Extensions Group. Numerical C provides extensions to the C language for array selection, vector math operations, complex data types, circular pointers and variably
dimensioned arrays. The ADSP-21000 Family Development
Software is available for both the PC and Sun platforms.
The SHARC EZ-KIT combines the ADSP-21000 Family Development Software for the PC and the EZ-LAB Development
Board in one package.
The ADSP-2106x EZ-ICE
®
Emulator uses the IEEE 1149.1
JTAG test access port of the ADSP-2106x processor to monitor
and control the target board processor during emulation. The
EZ-ICE provides full-speed emulation, allowing inspection and
modification of memory, registers and processor stacks.
Nonintrusive in-circuit emulation is assured by the use of the
processor’s JTAG interface—the emulator does not affect target
system loading or timing.
Further details and ordering information are available in the
ADSP-21000 Family Hardware & Software Development Tools
data sheet (ADDS-2100xx-TOOLS). This data sheet can be
requested from any Analog Devices sales office or distributor,
or from the Literature Center.
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the SHARC processor family. Hardware tools include SHARC PC plug-in cards, multiprocessor
SHARC VME boards, and daughter card modules with multiple
SHARCs and additional memory. These modules are based on
the SHARCPAC module specification. Third party software
tools include an Ada compiler, DSP libraries, operating systems
and block diagram design tools.
Quad-SHARC Development Board
The BlackTip-MCM, AD14060 development board and software, is available from Bittware Research Systems, Inc. This
board has one AD14060 BITSI interface, PROM and SRAM
expansion options on an ISA card. It is supported by Bittware’s
SHARC software development package. Bittware can be contacted at 1-800-848-0436.
Other Package Details
The AD14060/AD14060L contains 16 on-module 0.018 microfarad bypass capacitors. It is recommended that in the target
system at least four additional capacitors, of 0.018 microfarad
value, be placed around the module—one near each of the four
corners.
The top surface, lid, of the AD14060/AD14060L is electrically
connected to GND on the industrial and military grade parts.
Additional Information
This data sheet provides a general overview of the AD14060/
AD14060L architecture and functionality. For detailed information on the ADSP-2106x SHARC and the ADSP-21000
Family core architecture and instruction set, refer to the ADSP2106x SHARC User’s Manual.
EZ-ICE and EZ-LAB are registered trademarks of Analog Devices, Inc.
CBug is a trademark of Analog Devices, Inc.
REV. A
–7–
AD14060/AD14060L
PIN FUNCTION DESCRIPTIONS
AD14060/AD14060L pin definitions are listed below. Inputs
identified as synchronous (S) must meet timing requirements
with respect to CLKIN (or with respect to TCK for TMS,
TDI). Inputs identified as asynchronous (A) can be asserted
asynchronously to CLKIN (or to TCK for TRST).
Unused inputs should be tied or pulled to V
for ADDR
, DATA
31-0
, FLAG
47-0
, SW, and inputs that have
2-0
or GND, except
DD
TCLKx, RCLKx, LxDAT
TDI)—these pins can be left floating. These pins have a logiclevel hold circuit that prevents the input from floating internally.
I = Input P = Power Supply (A/D) = Active Drive
O = Output S = Synchronous (O/D) = Open Drain
G = Ground A = Asynchronous
T = Three-State (when SBTS is asserted, or when the AD14060/
AD14060L is a bus slave)
, LxCLK, LxACK, TMS and
3-0
internal pull-up or pull-down resistors (CPA, ACK, DTx, DRx,
Pin Type Function
ADDR
31-0
I/O/T External Bus Address. (Common to all SHARCs) The AD14060/AD14060L outputs addresses for
external memory and peripherals on these pins. In a multiprocessor system, the bus master outputs
addresses for read/writes on the internal memory or IOP registers of slave ADSP-2106xs. The AD14060/
AD14060L inputs addresses when a host processor or multiprocessing bus master is reading or writing
the internal memory or IOP registers of internal ADSP-21060s.
DATA
47-0
I/O/T External Bus Data. (Common to all SHARCs) The AD14060/AD14060L inputs and outputs data and
instructions on these pins. 32-bit single-precision floating-point data and 32-bit fixed-point data is transferred over bits 47-16 of the bus. 40-bit extended-precision floating-point data is transferred over bits 478 of the bus. 16-bit short word data is transferred over bits 31-16 of the bus. In PROM boot mode, 8-bit
data is transferred over bits 23-16. Pull-up resistors on unused DATA pins are not necessary.
MS
3-0
O/T Memory Select Lines. (Common to all SHARCs) These lines are asserted (low) as chip selects for the
corresponding banks of external memory. Memory bank size must be defined in the individual ADSP21060’s system control registers (SYSCON). The MS
change at the same time as the other address lines. When no external memory access is occurring the MS
lines are decoded memory address lines that
3-0
3-0
lines are inactive; they are active, however, when a conditional memory access instruction is executed, whether
or not the condition is true. MS
(Bank 0). In a multiprocessing system, the MS
can be used with the PAGE signal to implement a bank of DRAM memory
0
lines are output by the bus master.
3-0
RD I/O/T Memory Read Strobe. (Common to all SHARCs) This pin is asserted (low) when the AD14060/
AD14060L reads from external devices or when the internal memory of internal ADSP-2106xs is being
accessed. External devices (including other ADSP-2106xs) must assert RD to read from the AD14060/
AD14060L’s internal memory. In a multiprocessing system, RD is output by the bus master and is input
by all other ADSP-2106xs.
WR I/O/T Memory Write Strobe. (Common to all SHARCs) This pin is asserted (low) when the AD14060/
AD14060L writes to external devices or when the internal memory of internal ADSP-2106xs is being accessed. External devices (including other ADSP-2106xs) must assert WR to write to the AD14060/
AD14060L’s internal memory. In a multiprocessing system WR is output by the bus master and is input by
all other ADSP-2106xs.
PAGE O/T DRAM Page Boundary. (Common to all SHARCs) The AD14060/AD14060L asserts this pin to signal
that an external DRAM page boundary has been crossed. DRAM page size must be defined in the individual ADSP-21060’s memory control register (WAIT). DRAM can only be implemented in external
memory Bank 0; the PAGE signal can only be activated for Bank 0 accesses. In a multiprocessing system,
PAGE is output by the bus master.
ADRCLK O/T Clock Output Reference. (Common to all SHARCs) In a multiprocessing system, ADRCLK is output
by the bus master.
SW I/O/T Synchronous Write Select. (Common to all SHARCs) This signal is used to interface the AD14060/
AD14060L to synchronous memory devices (including other ADSP-2106xs). The AD14060/AD14060L
asserts SW (low) to provide an early indication of an impending write cycle, which can be aborted if WR
is not later asserted (e.g., in a conditional write instruction). In a multiprocessing system, SW is output
by the bus master and is input by all other ADSP-2106xs to determine if the multiprocessor memory
access is a read or write. SW is asserted at the same time as the address output. A host processor using
synchronous writes must assert this pin when writing to the AD14060/AD14060L.
ACK I/O/S Memory Acknowledge. (Common to all SHARCs) External devices can deassert ACK (low) to add
wait states to an external memory access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off completion of an external memory access. The AD14060/AD14060L deasserts
ACK, as an output, to add wait states to a synchronous access of its internal memory. In a multiprocessing system, a slave ADSP-2106x deasserts the bus master’s ACK input to add wait state(s) to an access
of its internal memory. The bus master has a keeper latch on its ACK pin that maintains the input at the
level it was last driven to.
–8–
REV. A
AD14060/AD14060L
Pin Type Function
SBTS I/S Suspend Bus Three-State. (Common to all SHARCs) External devices can assert SBTS (low) to
place the external bus address, data, selects, and strobes in a high impedance state for the following cycle.
If the AD14060/AD14060L attempts to access external memory while SBTS is asserted, the processor
will halt and the memory access will not be completed until SBTS is deasserted. SBTS should only be
used to recover from host processor/AD14060/AD14060L deadlock, or used with a DRAM controller.
HBR I/A Host Bus Request. (Common to all SHARCs) Must be asserted by a host processor to request control
of the AD14060/AD14060L’s external bus. When HBR is asserted in a multiprocessing system, the
ADSP-2106x that is bus master will relinquish the bus and assert HBG. To relinquish the bus, the
ADSP-2106x places the address, data, select, and strobe lines in a high impedance state. HBR has priority
over all ADSP-2106x bus requests (BR
HBG I/O Host Bus Grant. (Common to all SHARCs) Acknowledges an HBR bus request, indicating that the
host processor may take control of the external bus. HBG is asserted (held low) by the AD14060/AD14060L
until HBR is released. In a multiprocessing system, HBG is output by the ADSP-2106x bus master and is
monitored by all others.
CSA I/A Chip Select. Asserted by host processor to select SHARC_A.
CSB I/A Chip Select. Asserted by host processor to select SHARC_B.
CSC I/A Chip Select. Asserted by host processor to select SHARC_C.
CSD I/A Chip Select. Asserted by host processor to select SHARC_D.
REDY (O/D) O Host Bus Acknowledge. (Common to all SHARCs) The AD14060/AD14060L deasserts REDY (low)
to add wait states to an asynchronous access of its internal memory or IOP registers by a host. Open drain
output (O/D) by default; can be programmed in ADREDY bit of SYSCON register of individual ADSP21060s to be active drive (A/D). REDY will only be output if the CS and HBR inputs are asserted.
BR
6-1
I/O/S Multiprocessing Bus Requests. (Common to all SHARCs) Used by multiprocessing ADSP-2106xs to
arbitrate for bus mastership. An ADSP-2106x only drives its own BRx line (corresponding to the value of
its ID2-0 inputs) and monitors all others. In a multiprocessor system with less than six ADSP-2106xs, the
unused BRx pins should be pulled high; BR
RPBA I/S Rotating Priority Bus Arbitration Select. (Common to all SHARCs) When RPBA is high, rotating
priority for multiprocessor bus arbitration is selected. When RPBA is low, fixed priority is selected. This
signal is a system configuration selection that must be set to the same value on every ADSP-2106x. If the
value of RPBA is changed during system operation, it must be changed in the same CLKIN cycle on
every ADSP-2106x.
CPAy (O/D) I/O Core Priority Access. (y = SHARC_A, B, C, D) Asserting its CPA pin allows the core processor of an
ADSP-2106x bus slave to interrupt background DMA transfers and gain access to the external bus.
CPA is an open drain output that is connected to all ADSP-2106x in the system if this function is
required. The CPA pin of each internal ADSP-21060 is brought out individually. The CPA pin has
an internal 5 kΩ pull-up resistor. If core access priority is not required in a system, the CPA pin
should be left unconnected.
DT0 O/T Data Transmit (Common Serial Ports 0 to all SHARCs, TDM). DT pin has a 50 kΩ internal pull-up
resistor.
DR0 I Data Receive (Common Serial Ports 0 to all SHARCs, TDM). DR pin has a 50 kΩ internal pull-up
resistor.
TCLK0 I/O Transmit Clock (Common Serial Ports 0 to all SHARCs, TDM). TCLK pin has a 50 kΩ internal
pull-up resistor.
RCLK0 I/O Receive Clock (Common Serial Ports 0 to all SHARCs, TDM). RCLK pin has a 50 kΩ internal pull-up
resistor.
TFS0 I/O Transmit Frame Sync (Common Serial Ports 0 to all SHARCs, TDM).
RFS0 I/O Receive Frame Sync (Common Serial Ports 0 to all SHARCs, TDM).
DTy1 O/T Data Transmit (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) DT pin
has a 50 kΩ internal pull-up resistor.
DRy1 I Data Receive (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) DR pin
has a 50 kΩ internal pull-up resistor.
) in a multiprocessing system.
6-1
must not be pulled high or low because they are outputs.
4-1
REV. A
–9–
AD14060/AD14060L
Pin Type Function
TCLKy1 I/O Transmit Clock (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) TCLK
pin has a 50 kΩ internal pull-up resistor.
RCLKy1 I/O Receive Clock (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) RCLK
pin has a 50 kΩ internal pull-up resistor.
TFSy1 I/O Transmit Frame Sync (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D)
RFSy1 I/O Receive Frame Sync (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D)
FLAGy0 I/O/A Flag Pins. (FLAG0 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) Each is config-
ured via control bits as either an input or output. As an input, it can be tested as a condition. As an out-
put, it can be used to signal external peripherals.
FLAG1 I/O/A Flag Pins. (FLAG1 common to all SHARCs) Configured via control bits internal to individual ADSP-
21060s as either an input or output. As an input, it can be tested as a condition. As an output, it can be
used to signal external peripherals.
FLAGy2 I/O/A Flag Pins. (FLAG2 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) Each is config-
ured via control bits as either an input or output. As an input, it can be tested as a condition. As an out-
put, it can be used to signal external peripherals.
IRQy2-0 I/A Interrupt Request Lines. (Individual IRQ2-0 from y = SHARC_A, SHARC_B, SHARC_C, SHARC_D)
May be either edge-triggered or level-sensitive.
DMAR1 I/A DMA Request 1 (DMA Channel 7). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D.
DMAR2 I/A DMA Request 2 (DMA Channel 8). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D.
DMAG1 O/T DMA Grant 1 (DMA Channel 7). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D.
DMAG2 O/T DMA Grant 2 (DMA Channel 8). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D.
LyxCLK I/O Link Port Clock (y = SHARC_A, B, C, D; x = Link Ports 1, 3, 4)
internal pull-down resistor which is enabled or disabled by the LPDRD bit of the LCOM register, of the
ADSP-20160.
LyxDAT3-0 I/O Link Port Data (y = SHARC_A, B, C, D; x = Link Ports 1, 3, 4)
50 kΩ internal pull-down resistor which is enabled or disabled by the LPDRD bit of the LCOM register,
of the ADSP-21060.
LyxACK I/O Link Port Acknowledge (y = SHARC_A, B, C, D; x = Link Ports 1, 3, 4)
50 kΩ internal pull-down resistor which is enabled or disabled by the LPDRD bit of the LCOM register,
of the ADSP-21060.
EBOOTA I EPROM Boot Select. (SHARC_A) When EBOOTA is high, SHARC_A is configured for booting from
an 8-bit EPROM. When EBOOTA is low, the LBOOTA and BMSA inputs determine booting mode
for SHARC_A. See the following table. This signal is a system configuration selection which should
be hardwired.
LBOOTA I Link Boot. When LBOOTA is high, SHARC_A is configured for link port booting. When LBOOTA is
low, SHARC_A is configured for host processor booting or no booting. See the following table. This
signal is a system configuration selection which should be hardwired.
BMSA I/O/T
2
Boot Memory Select. Output: Used as chip select for boot EPROM devices (when EBOOTA = 1,
LBOOTA = 0). In a multiprocessor system, BMS is output by the bus master. Input: When low, indicates
that no booting will occur and that SHARC_A will begin executing instructions from external memory.
See the following table. This input is a system configuration selection which should be hardwired.
EBOOTBCD I EPROM Boot Select. (Common to SHARC_B, SHARC_C, SHARC_D) When EBOOTBCD is high,
SHARC_B, C, D are configured for booting from an 8-bit EPROM. When EBOOTBCD is low, the
LBOOTBCD and BMSBCD inputs determine booting mode for SHARC_B, C and D. See the following
table. This signal is a system configuration selection which should be hardwired.
LBOOTBCD I LINK Boot. (Common to SHARC_B, SHARC_C, SHARC_D) When LBOOTBCD is high, SHARC_B, C,
D are configured for link port booting. When LBOOTBCD is low, SHARC_B, C, D are configured for
host processor booting or no booting. See the following table. This signal is a system configuration selec-
tion which should be hardwired.
1
. Each LyxCLK pin has a 50 kΩ
1
. Each LyxDAT pin has a
1
. Each LyxACK pin has a
–10–
REV. A
AD14060/AD14060L
Pin Type Function
2
BMSBCD I/O/T
TIMEXPy O Timer Expired. (Individual TIMEXP from y = SHARC_A, SHARC_B, SHARC_C, SHARC_D) Asserted
CLKIN I Clock In. (Common to all SHARCs) External clock input to the AD14060/AD14060L. The instruction
RESET I/A Module Reset. (Common to all SHARCs) Resets the AD14060/AD14060L to a known state. This input
TCK I Test Clock (JTAG). (Common to all SHARCs) Provides an asynchronous clock for JTAG boundary
TMS I/S Test Mode Select (JTAG). (Common to all SHARCs) Used to control the test state machine. TMS has
TDI I/S Test Data Input (JTAG). Provides serial data for the boundary scan logic chain starting at SHARC_A.
TDO O Test Data Output (JTAG). Serial scan output of the boundary scan chain path, from SHARC_D.
TRST I/A Test Reset (JTAG). (Common to all SHARCs) Resets the test state machine. TRST must be asserted
EMU (O/D) O Emulation Status. (Common to all SHARCs) Must be connected to the ADSP-2106x EZ-ICE target
V
DD
P Power Supply. Nominally +5.0 V dc for 5 V devices or +3.3 V dc for 3.3 V devices (26 pins).
GND G Power Supply Return. (28 pins).
NOTES
FLAG3 is connected internally, common to SHARC_A, B, C, and D.
ID pins are hardwired internally as depicted in the block diagram.
1
LINK PORTS 0, 2 and 5 are connected internally as described earlier in Link Port I/O.
2
Three-statable only in EPROM boot mode (when BMS is an output).
Boot Memory Select. Output: Used as chip select for boot EPROM devices (when EBOOTBCD = 1,
LBOOTBCD = 0). In a multiprocessor system, BMS is output by the bus master. Input: When low,
indicates that no booting will occur and that SHARC_B, C, D will begin executing instructions from
external memory. See table below. This input is a system configuration selection which should be
hardwired.
EBOOT LBOOT BMS Booting Mode
1 0 Output EPROM (Connect BMS to EPROM chip select)
0 0 1 (Input) Host Processor
0 1 1 (Input) Link Port
0 0 0 (Input) No Booting. Processor executes from external memory.
0 1 0 (Input) Reserved
1 1 x (Input) Reserved
for four cycles when the timer is enabled and TCOUNT decrements to zero.
cycle rate is equal to CLKIN. CLKIN may not be halted, changed, or operated below the minimum specified
frequency.
must be asserted (low) at power-up.
scan.
a 20 kΩ internal pull-up resistor.
TDI has a 20 kΩ internal pull-up resistor.
(pulsed low) after power-up or held low for proper operation of the AD14060/AD14060L. TRST has a
20 kΩ internal pull-up resistor.
board connector only.
REV. A
–11–
AD14060/AD14060L
TARGET BOARD CONNECTOR FOR EZ-ICE PROBE
The ADSP-2106x EZ-ICE Emulator uses the IEEE 1149.1 JTAG
test access port of the ADSP-2106x to monitor and control the
target board processor during emulation. The EZ-ICE probe
requires that the AD14060/AD14060L’s CLKIN (optional),
TMS, TCK, TRST, TDI, TDO, EMU and GND signals be
made accessible on the target system via a 14-pin connector (a
pin strip header) such as that shown in Figure 6. The EZ-ICE
probe plugs directly onto this connector for chip-on-board emulation. You must add this connector to your target board design
if you intend to use the ADSP-2106x EZ-ICE. The length of
the traces between the connector and the AD14060/
AD14060L’s JTAG pins should be as short as possible.
GND
KEY (NO PIN)
BTMS
BTCK
BTRST
BTDI
GND
1 2
3 4
5 6
7 8
9 10
9
11 12
13 14
TOP VIEW
EMU
CLKIN (OPTIONAL)
TMS
TCK
TRST
TDI
TDO
Figure 6. Target Board Connector for ADSP-2106x EZ-ICE
Emulator (Jumpers in Place)
The 14-pin, 2-row pin strip header is keyed at the Pin 3 location;
Pin 3 must be removed from the header. The pins must be
0.025 inch square and at least 0.20 inch in length. Pin spacing
should be 0.1 × 0.1 inches. Pin strip headers are available from
vendors such as 3M, McKenzie and Samtec.
The BTMS, BTCK, BTRST and BTDI signals are provided so
that the test access port can also be used for board-level testing.
When the connector is not being used for emulation, place
jumpers between the Bxxx pins and the xxx pins as shown in
Figure 6. If you are not going to use the test access port for
board testing, tie BTRST to GND and tie or pull up BTCK to
V
. The TRST pin must be asserted after power-up (through
DD
BTRST on the connector) or held low for proper operation of
the AD14060/AD14060L. None of the Bxxx pins (Pins 5, 7, 9,
11) are connected on the EZ-ICE probe.
The JTAG signals are terminated on the EZ-ICE probe as follows:
Signal Termination
TMS Driven through 22 Ω Resistor (16 µA–3.2 µA Driver)
TCK Driven at 10 MHz through 22 Ω Resistor (16 µA–
3.2 µA Driver)
TRST Driven by Open-Drain Driver* (Pulled Up by On-Chip
20 kΩ resistor)
TDI Driven by 16 µA–3.2 µA Driver
TDO One TTL Load, No Termination
CLKIN One TTL Load, No Termination (Optional Signal)
EMU 4.7 kΩ Pull-Up Resistor, One TTL Load (Open-Drain
Output from ADSP-2106x)
*TRST is driven low until the EZ-ICE probe is turned on by the EZ-ICE
software (after the invocation command).
Figure 7 shows JTAG scan path connections for the multiprocessor system.
Connecting CLKIN to Pin 4 of the EZ-ICE header is optional.
The emulator only uses CLKIN when directed to perform
OTHER
JTAG
CONTROLLER
EZ-ICE
JTAG
CONNECTOR
TCK
TMS
EMU
TRST
TDO
CLKIN
TDI
SHARC_A
TDI TDO
TCK
TMS
OPTIONAL
EMU
TRST
SHARC_B
TDI TDO
TCK
TMS
EMU
TRST
SHARC_C
TDI TDO
TCK
TMS
EMU
TRST
SHARC_D
TDI TDO
TCK
TMS
EMU
TRST
Figure 7. JTAG Scan Path Connections for the AD14060/AD14060L
–12–
JTAG DEVICE
(OPTIONAL)
TDI TDO
TCK
TMS
TRST
ADSP-2106x
#n
TDI TDO
TCK
TMS
EMU
REV. A
TRST
AD14060/AD14060L
operations such as starting, stopping and single-stepping multiple ADSP-2106xs in a synchronous manner. If you do not
need these operations to occur synchronously on the multiple
processors, simply tie Pin 4 of the EZ-ICE header to ground.
If synchronous multiprocessor operations are needed and CLKIN
is connected, clock skew between the AD14060/AD14060L and
the CLKIN pin on the EZ-ICE header must be minimal. If the
skew is too large, synchronous operations may be off by one
cycle between processors. For synchronous multiprocessor
operation TCK, TMS, CLKIN and EMU should be treated as
critical signals in terms of skew, and should be laid out as short
TDI TDO TDI TDO
5kV
*
TDI
EMU
TCK
TMS
TRST
TDO
CLKIN
TDI TDO
5kV
*
*
OPEN DRAIN DRIVER OR EQUIVALENT, i.e.,
TDI TDO
as possible on your board. If TCK, TMS and CLKIN are driving a large number of ADSP-2106xs (more than eight) in your
system, then treat them as a “clock tree” using multiple drivers
to minimize skew. (See Figure 8 JTAG Clock Tree and Clock
Distribution in the “High Frequency Design Considerations”
section of the ADSP-2106x User’s Manual).
If synchronous multiprocessor operations are not needed (i.e.,
CLKIN is not connected), just use appropriate parallel termination on TCK and TMS. TDI, TDO, EMU and TRST are not
critical signals in terms of skew.
TDI TDO
TDI TDO
SYSTEM
EMU
CLKIN
Figure 8. JTAG Clocktree for Multiple ADSP-2106x Systems
REV. A
–13–
AD14060/AD14060L–SPECIFICA TIONS
RECOMMENDED OPERATING CONDITIONS
Parameter Min Max Min Max Units
B Grade K Grade
V
T
DD
CASE
Supply Voltage (5 V) 4.75 5.25 4.75 5.25 V
Supply Voltage (3.3 V) 3.15 3.6 3.15 3.6 V
Case Operating Temperature –40 +100 0 +85 °C
ELECTRICAL CHARACTERISTICS (3.3 V, 5 V SUPPLY)
Parameter Temp Level Test Condition Min Typ Max Min Typ Max Units
V
IH1
V
IH2
V
IL
V
OH
V
OL
I
IH
I
IL
I
ILP
I
ILPX4
I
OZH
I
OZL
I
OZHP
I
OZLC
I
OZLA
I
OZLAR
I
OZLS
I
OZLSX4
I
DDIN
I
DDIDLE
C
IN
High Level Input Voltage
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
High Level Input Current
Low Level Input Current
Low Level Input Current
Low Level Input Current
Three-State Leakage Current
Three-State Leakage Current
Three-State Leakage Current
Three-State Leakage Current
Three-State Leakage Current
Three-State Leakage Current
Three-State Leakage Current
Three-State Leakage Current
Supply Current (Internal)
Supply Current (Idle)
Input Capacitance
1
2
1, 2
3, 4
3, 4
5, 6, 7
5
6
7
8, 9, 10, 14
8, 11
11
12
13
10
9
14
15
16
17, 18
EXPLANATION OF TEST LEVELS
Test Level
I 100% Production Tested19.
II 100% Production Tested at +25°C, and Sample Tested at Specified Temperatures.
III Sample Tested Only.
IV Parameter is guaranteed by design and analysis, and characterization testing on discrete SHARCs.
V Parameter is typical value only.
VI All devices are 100% production tested at +25°C; sample tested at temperature extremes.
NOTES
1
Applies to input and bidirectional pins: DATA
BR
, RPBA, CPAy, TFS0, TFSy1, RFS0, RFSy1, LyxDAT
6-1
TDI, TCK, HBR, DR0, DRy1, TCLK0, TCLKy1, RCLK0, RCLKy1.
2
Applies to input pins: CLKIN, RESET, TRST.
3
Applies to output and bidirectional pins: DATA
REDY, DMAG1, DMAG2, BR
BMSA, BMSBCD, TDO, EMU.
4
See Output Drive Currents for typical drive current capabilities.
5
Applies to input pins: SBTS, IRQy
6
Applies to input pins with internal pull-ups: DR0, DRy1, TDI.
7
Applies to bussed input pins with internal pull-ups: TRST, TMS.
8
Applies to three-statable pins: DATA
BMSA, BMSBCD, TDO, EMU. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID
2106x is not requesting bus mastership. HBG AND EMU are not tested for leakage current.)
9
Applies to three-statable pins with internal pull-ups: DTy1, TCLKy1, RCLKy1.
10
Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID
ADSP-2106x is not requesting bus mastership.)
11
Applies to three-statable pins with internal pull-downs: LyxDAT
12
Applies to CPAy pin.
13
Applies to ACK pin when keeper latch enabled.
14
Applies to bused three-statable pins with internal pull-ups: DT0, TCLK0, RCLK0.
15
Applies to VDD pins. Conditions of operation: each processor executing radix-2 FFT butterfly with instruction in cache, one data operand fetched from each internal
memory block, and one DMA transfer occurring from/to internal memory at tCK = 25 ns.
16
Applies to VDD pins. Idle denotes AD14060/AD14060L state during execution of IDLE instruction.
17
Applies to all signal pins.
18
Guaranteed but not tested.
19
Link and Serial Ports: All are 100% tested at die level prior to assembly. All are 100% ac tested at module level; Link-4 and Serial-0 are also dc tested at the module
, CPAy, DTO, DTy1, TCLK0, TCLKy1, RCLK0, RCLKy1, TFS0, TFSy1, RFS0, RFSy1 LyxDAT
6-1
, HBR, CSy, DMAR1, DMAR2, RPBA, EBOOTA, LBOOTA, EBOOTBCD, LBOOTBCD, CLKIN, RESET, TCK.
2-0
, ADDR
47-0
level. See Timing Specifications.
Specifications subject to change without notice.
Case Test 5 V 3.3 V
Full I @ VDD = max 2.0 VDD + 0.5 2.0 VDD + 0.5 V
Full I @ VDD = max 2.2 VDD + 0.5 2.2 VDD + 0.5 V
Full I @ VDD = min 0.8 0.8 V
Full I @ VDD = min, IOH = –2.0 mA44.1 2.4 V
Full I @ VDD = min, IOL = 4.0 mA
4
0.4 0.4 V
Full I @ VDD = max, VIN = VDD max 10 10 µA
Full I @ VDD = max, VIN = 0 V 10 10 µA
Full I @ VDD = max, VIN = 0 V 150 150 µA
Full I @ VDD = max, VIN = 0 V 600 600 µA
Full I @ VDD = max, VIN = VDD max 10 10 µA
Full I @ VDD = max, VIN = 0 V 10 10 µA
Full I @ VDD = max, VIN = VDD max 350 350 µA
Full I @ VDD = max, VIN = 0 V 1.5 1.5 mA
Full I @ VDD = max, VIN = 1.5 V (5 V),
2 V (3.3 V) 350 350 µA
Full I @ VDD = max, VIN = 0 V 4.2 4.2 mA
Full I @ VDD = max, VIN = 0 V 150 150 µA
Full I @ VDD = max, VIN = 0 V 600 600 µA
Full IV tCK = 25 ns, VDD = max 1.4 3.4 1.0 2.2 A
Full I VDD = max 800 760 mA
+25°CV
, ADDR
47-0
, ADDR
47-0
, MS
31-0
, RD, WR, SW, ACK, SBTS, IRQy
31-0
, LyxCLK, LyxACK, EBOOTA, LBOOTA, EBOOTBCD, LBOOTBCD, BMSA, BMSBCD, TMS,
3-0
, MS
31-0
, RD, WR, PAGE, ADRCLK, SW, ACK, FLAGy0, FLAG1, FLAGy2, REDY, HBG, DMAG1, DMAG2,
3-0
RD, WR, PAGE, ADRCLK, SW, ACK, FLAGy0, FLAG1, FLAGy2, TIMEXPy, HBG,
3-0
, LyxCLK, LyxACK.
3-0
, FLAGy0, FLAG1, FLAGy2, HBG, CSy, DMAR1, DMAR2,
2-0
15 15 pF
, LyxCLK, LyxACK,
3-0
= 001 and another ADSP-
2-0
= 001 and another
2-0
–14–
REV. A
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