Altera I/O Buffer IP Core User Manual

2014.12.15

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I/O Buffer (ALTIOBUF) IP Core User Guide

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The ALTIOBUF megafunction IP core implements either an I/O input buffer (ALTIOBUF_in), I/O
output buffer (ALTIOBUF_out), or I/O bidirectional buffer (ALTIOBUF_bidir). You can configure the IP
core through the IP Catalog and parameter editor in the Quartus® II software.

This user guide assumes that you are familiar with IP cores and how to configure them.

Related Information

Introduction to Altera IP Cores

Provides general information about Altera IP cores

ALTIOBUF Features

The ALTIOBUF IP core provides the following features:

• Capable of bus-hold circuitry

• Can enable differential mode

• Can specify open-drain output

• Can specify output enable port (oe)

• Can enable dynamic termination control ports for I/O bidirectional buffers

• Can enable series and parallel termination control ports for I/O output buffers and I/O bidirectional
buffers

• Can enable dynamic delay chains for I/O buffers

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I/O Buffer and Dynamic Delay Integration

Altera recommends that you use the ALTIOBUF IP core to utilize the I/O buffers for any purpose that
includes LVDS interfaces (using the ALTLVDS IP core), DDR interfaces (using the ALTDDIO_IN,
ALTDDIO_OUT, ALTDDIO_BIDIR, ALTDQ, ALTDQS, and ALTDQ_DQS IP cores) and dynamic on­chip termination (OCT) control (using the ALTOCT IP core).

ALTIOBUF Common Application

The I/O buffers have standard capabilities such as bus-hold circuitry, differential mode, open-drain
output, and output enable port.

One of the key applications for this IP core is to have more direct termination control of the buffers. By
enabling series and parallel termination control ports for the I/O output buffers and I/O bidirectional

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of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.

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ALTIOBUF Common Application

buffers, you can connect these ports to the ALTOCT IP core to enable dynamic calibration for on-chip
termination.

The additional dynamic termination control ports allow control when series termination or parallel
termination are enabled for bidirectional buffers. Parallel termination needs to only be enabled when the
bidirectional I/O is receiving input. Otherwise, it needs to be disabled so that the output performance and
power dissipation is optimal.

Another key application for this IP core is for dynamic delay chain in the I/O buffer. Dynamic I/O delay
allows implementing automatic deskew, especially for memory interfaces, such as DDR3, which is
handled by the memory interface intellectual property (IP). You need to dynamically deskew and not
calculate manually because much of the skew can come from the I/O buffers of either the FPGA or the
other device the FPGA is interfacing with (for example, memory). Even if the trace lengths are matched,
there can still be electrical skew in the system. Also, this skew changes and can change from device to
device. Having the ability to deskew from the fabric allows you to remove uncertainties that would have to
be considered in the timing budget. This allows you to gain more timing margin, which allows higher
frequencies.

Figure 1: Example Illustrating Deskew

This figure shows an example of deskew.

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For example, if the input (or output) bus signals are DQ[0] and DQ[1], board trace skew, transmitter
device skew, or even FPGA package skew could cause signals that were initially aligned to become
misaligned. The third waveform shows the window available to the receiver for capturing the data. If

DQ[0] was delayed a bit to match DQ[1], a wider window would become available to the receiver.

Note:

To find the left and right edges of the data valid window, you need to do coarser adjustments (one
possible method is to use the new phase adjustment functionality of the PLL (ALTPLL IP core). The range

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The deskew delay chains are not meant to find the middle of a data valid window, but just to
deskew the incoming (or outgoing) data to widen the overall window for a bus of inputs (or
outputs). To do this, you only need to align just one edge (for example, the left edge) of the data
valid window of all the pins.

I/O Buffer (ALTIOBUF) IP Core User Guide

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acds

quartus - Contains the Quartus II software
ip - Contains the Altera IP Library and third-party IP cores

altera - Contains the Altera IP Library source code

<IP core name> - Contains the IP core source files

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of the deskew delay chains is only designed to compensate for a reasonable amount of board and package/
layout skew.

Related Information

ALTOCT IP Core User Guide

Provides information about connecting the ALTIOBUF ports to ALTOCT IP core.

Installing and Licensing IP Cores

The Altera IP Library provides many useful IP core functions for production use without purchasing an
additional license. You can evaluate any Altera® IP core in simulation and compilation in the Quartus® II
software using the OpenCore® evaluation feature. Some Altera IP cores, such as MegaCore® functions,
require that you purchase a separate license for production use. You can use the OpenCore Plus feature to
evaluate IP that requires purchase of an additional license until you are satisfied with the functionality and
performance. After you purchase a license, visit the Self Service Licensing Center to obtain a license
number for any Altera product.

Figure 2: IP Core Installation Path

Installing and Licensing IP Cores

3

Note: The default IP installation directory on Windows is <drive>:\altera\<version number>; on Linux it is

<home directory>/altera/ <version number>.

Related Information

• Altera Licensing Site

• Altera Software Installation and Licensing Manual

IP Catalog and Parameter Editor

The Quartus II IP Catalog (Tools > IP Catalog) and parameter editor help you easily customize and
integrate IP cores into your project. You can use the IP Catalog and parameter editor to select, customize,
and generate files representing your custom IP variation.

Note:

The IP Catalog lists IP cores available for your design. Double-click any IP core to launch the parameter
editor and generate files representing your IP variation. The parameter editor prompts you to specify an
IP variation name, optional ports, and output file generation options. The parameter editor generates a
top-level Qsys system file (.qsys) or Quartus II IP file (.qip) representing the IP core in your project. You
can also parameterize an IP variation without an open project.

The IP Catalog (Tools > IP Catalog) and parameter editor replace the MegaWizard™ Plug-In
Manager for IP selection and parameterization, beginning in Quartus II software version 14.0. Use
the IP Catalog and parameter editor to locate and paramaterize Altera IP cores.

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Search and filter IP for your target device

Double-click to customize, right-click for information

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Using the Parameter Editor

Use the following features to help you quickly locate and select an IP core:

• Filter IP Catalog to Show IP for active device family or Show IP for all device families.

• Search to locate any full or partial IP core name in IP Catalog. Click Search for Partner IP, to access

partner IP information on the Altera website.

• Right-click an IP core name in IP Catalog to display details about supported devices, open the IP core's
installation folder, andor view links to documentation.

Figure 3: Quartus II IP Catalog

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Note: The IP Catalog is also available in Qsys (View > IP Catalog). The Qsys IP Catalog includes

exclusive system interconnect, video and image processing, and other system-level IP that are not
available in the Quartus II IP Catalog. For more information about using the Qsys IP Catalog, refer
to Creating a System with Qsys in the Quartus II Handbook.

Using the Parameter Editor

The parameter editor helps you to configure IP core ports, parameters, and output file generation options.

• Use preset settings in the parameter editor (where provided) to instantly apply preset parameter values
for specific applications.

• View port and parameter descriptions, and links to documentation.

• Generate testbench systems or example designs (where provided).

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I/O Buffer (ALTIOBUF) IP Core User Guide

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View IP port
and parameter
details

Apply preset parameters for
specific applications

Specify your IP variation name
and target device

Legacy parameter
editors

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Figure 4: IP Parameter Editors

Customizing and Generating IP Cores

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Customizing and Generating IP Cores

You can customize IP cores to support a wide variety of applications. The Quartus II IP Catalog displays
IP cores available for the current target device. The parameter editor guides you to set parameter values
for optional ports, features, and output files.

To customize and generate a custom IP core variation, follow these steps:

1. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize.
The parameter editor appears.

2. Specify a top-level name for your custom IP variation. This name identifies the IP core variation files
in your project. If prompted, also specify the target Altera device family and output file HDL
preference. Click OK.

3. Specify the desired parameters, output, and options for your IP core variation:

• Optionally select preset parameter values. Presets specify all initial parameter values for specific

applications (where provided).

• Specify parameters defining the IP core functionality, port configuration, and device-specific

features.

• Specify options for generation of a timing netlist, simulation model, testbench, or example design

(where applicable).

• Specify options for processing the IP core files in other EDA tools.

4. Click Finish or Generate to generate synthesis and other optional files matching your IP variation
specifications. The parameter editor generates the top-level .qip or .qsys IP variation file and HDL files

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Upgrading IP Cores

for synthesis and simulation. Some IP cores also simultaneously generate a testbench or example
design for hardware testing.

5. To generate a simulation testbench, click Generate > Generate Testbench System. Generate >
Generate Testbench System is not available for some IP cores.

6. To generate a top-level HDL design example for hardware verification, click Generate > HDL
Example. Generate > HDL Example is not available for some IP cores.

When you generate the IP variation with a Quartus II project open, the parameter editor automatically
adds the IP variation to the project. Alternatively, click Project > Add/Remove Files in Project to
manually add a top-level .qip or .qsys IP variation file to a Quartus II project. To fully integrate the IP
into the design, make appropriate pin assignments to connect ports. You can define a virtual pin to
avoid making specific pin assignments to top-level signals.

Note: By default, all unused pins are tied to ground. Altera recommends setting all unused pins to tri-

state because doing otherwise might cause interference. To set all unused pins to tri-state, in the
Quartus II software, click Assignments > Device > Device and Pin Options > Unused Pins
and select an item from the Reserve all unused pins list.

Upgrading IP Cores

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IP core variants generated with a previous version of the Quartus II software may require upgrading
before use in the current version of the Quartus II software. Click Project > Upgrade IP Components to
identify and upgrade IP core variants.

The Upgrade IP Components dialog box provides instructions when IP upgrade is required, optional, or
unsupported for specific IP cores in your design. You must upgrade IP cores that require it before you can
compile the IP variation in the current version of the Quartus II software. Many Altera IP cores support
automatic upgrade.

The upgrade process renames and preserves the existing variation file (.v, .sv, or .vhd) as <my_variant>_

BAK.v, .sv, .vhd in the project directory.

Table 1: IP Core Upgrade Status

IP Core Status Corrective Action

Required Upgrade IP
Components

Optional Upgrade IP
Components

You must upgrade the IP variation before compiling in the current version of
the Quartus II software.

Upgrade is optional for this IP variation in the current version of the Quartus
II software. You can upgrade this IP variation to take advantage of the latest
development of this IP core. Alternatively you can retain previous IP core
characteristics by declining to upgrade.

Upgrade Unsupported Upgrade of the IP variation is not supported in the current version of the

Quartus II software due to IP core end of life or incompatibility with the
current version of the Quartus II software. You are prompted to replace the
obsolete IP core with a current equivalent IP core from the IP Catalog.

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I/O Buffer (ALTIOBUF) IP Core User Guide

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Displays upgrade
status for all IP cores
in the Project

Upgrades all IP core that support “Auto Upgrade”
Upgrades individual IP cores unsupported by “Auto Upgrade”

Checked IP cores
support “Auto Upgrade”

Successful
“Auto Upgrade”

Upgrade
unavailable

Double-click to
individually migrate

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Upgrading IP Cores

Before you begin

• Archive the Quartus II project containing outdated IP cores in the original version of the Quartus II
software: Click Project > Archive Project to save the project in your previous version of the Quartus II
software. This archive preserves your original design source and project files.

• Restore the archived project in the latest version of the Quartus II software: Click Project > Restore
Archived Project. Click OK if prompted to change to a supported device or overwrite the project
database. File paths in the archive must be relative to the project directory. File paths in the archive
must reference the IP variation .v or .vhd file or .qsys file (not the .qip file).

1. In the latest version of the Quartus II software, open the Quartus II project containing an outdated IP
core variation. The Upgrade IP Components dialog automatically displays the status of IP cores in
your project, along with instructions for upgrading each core. Click Project > Upgrade IP

Components to access this dialog box manually.

2. To simultaneously upgrade all IP cores that support automatic upgrade, click Perform Automatic
Upgrade. The Status and Version columns update when upgrade is complete. Example designs

provided with any Altera IP core regenerate automatically whenever you upgrade the IP core.

Figure 5: Upgrading IP Cores

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I/O Buffer (ALTIOBUF) IP Core User Guide

Example 1: Upgrading IP Cores at the Command Line

You can upgrade IP cores that support auto upgrade at the command line. IP cores that do not
support automatic upgrade do not support command line upgrade.

• To upgrade a single IP core that supports auto-upgrade, type the following command:

quartus_sh –ip_upgrade –variation_files <my_ip_filepath/my_ip>.<hdl>
<qii_project>

Example:
quartus_sh -ip_upgrade -variation_files mega/pll25.v hps_testx

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ALTIOBUF Parameters

• To simultaneously upgrade multiple IP cores that support auto-upgrade, type the following
command:

quartus_sh –ip_upgrade –variation_files “<my_ip_filepath/my_ip1>.<hdl>;
<my_ip_filepath/my_ip2>.<hdl>” <qii_project>

Example:
quartus_sh -ip_upgrade -variation_files "mega/pll_tx2.v;mega/pll3.v"
hps_testx

Note: IP cores older than Quartus II software version 12.0 do not support upgrade.

Altera verifies that the current version of the Quartus II software compiles the
previous version of each IP core. The Altera IP Release Notes reports any verifica‐
tion exceptions for Altera IP cores. Altera does not verify compilation for IP cores
older than the previous two releases.

Related Information

Altera IP Release Notes

ALTIOBUF Parameters

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This table lists the options ALTIOBUF IP core parameters.

Table 2: ALTIOBUF IP Core Parameters: General Tab

Parameter Description

Currently selected device family: Specify the device family you want to use.
How do you want to configure this

module?
What is the number of buffers to be

instantiated?

Specify whether it is an input buffer, output buffer, or bidirec‐
tional buffer.

Specify the number of buffers to be used. This defines the size
of the buffer.

Use bus hold circuitry If enabled, the bus-hold circuitry can weakly hold the signal

on an I/O pin at its last-driven state. Available in input buffer,
output buffer, or bidirectional buffer.

Use differential mode If enabled, datain/datain_b is used for input buffers, both

dataout/dataout_b are used for output buffers, and both
dataio/dataio_b are used for bidirectional buffers.

Use open drain output If enabled, the open drain output enables the device to

provide system-level control signals (for example, interrupt
and write-enable signals) that can be asserted by multiple
devices in your system. This option is only available for
output buffers and bidirectional buffers.

Use output enable port(s) If enabled, there is a port used to control when the output is

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enabled. This option is only available for output buffers and
bidirectional buffers.

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ALTIOBUF Parameters

Parameter Description

Use dynamic termination control(s) If enabled, this port receives the command to select either Rs

code (when input value = low) or Rt code (when input value =
high) from the core. Only enable Rt when the bi-directional I/
O is receiving input. Otherwise, it needs to be disabled so that
the output performance and power dissipation is optimal.
This option is available only for input and bidirectional
buffers.

An error is issued if parallel termination (Rt) is on and
dynamic termination control is not connected on a bidir pin.
An error is issued if parallel termination (Rt) is off and
dynamic termination control is connected on an input or
bidirectional pin.

Note that two I/Os in the same dynamic termination control
group needs to have the same dynamic termination control
signal. If the I/Os have separate dynamic termination control
signals, the Quartus II software produces a fitting error. A
dynamic termination control group is a group of pins that
share the same physical dynamic termination control signal
on the chip.

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This option is not available in Cyclone III and Cyclone IV
devices.

Use series and parallel termination
controls

If enabled, this allows the series and parallel termination
control ports to be used. These ports can then be connected to
termination logic blocks to receive the Rs or Rt code from the
termination logic blocks.

This option is only available for output buffers and bidirec‐
tional buffers. The series and parallel termination control
ports are 14-bit wide for series or parallel termination.

For Cyclone III, Cyclone IV, and Cyclone V devices, this
option is available for output buffers and bidirectional buffers,
but not for input buffers. Only series termination is available.
The series termination control ports are 16-bit wide. The
width of these ports increases depending on the amount of
buffers instantiated.

Use left shift series termination control If enabled, you can use the left shift series termination control

to get the calibrated OCT Rs with half of the impedance value
of the external reference resistors connected to RUP and RDN
pins. This option is useful in applications which required both
25-Ω and 50-Ω calibrated OCT Rs at the same V

. For more

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information, refer to I/O features chapter of the respective
device handbooks.

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