Altera HyperTransport MegaCore Function User Manual

HyperTransport MegaCore Function

User Guide

The IP described in this document is scheduled for product obsolescence and discontinued support as described in PDN0906. Therefore, Altera® does not recommend use of this IP in new designs. For more information about Altera’s current IP offering, refer to Altera’s Intellectual Property website.

101 Innovation Drive San Jose, CA 95134

www.altera.com

MegaCore Version: 9.1 Document Date: November 2009

Copyright © 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services

UG-MCHYPRTRNS-1.12

Chapter 1. About this MegaCore Function

Release Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Device Family Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

OpenCore Plus Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3

Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3

Chapter 2. Getting Started

Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

MegaCore Function Walkthrough . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2

Create a New Quartus II Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2

Launch the MegaWizard Plug-in Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3

Step 1: Parameterize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5

Step 2: Set Up Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9

Step 3: Generate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11

Simulate the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13

Compile the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13

Program a Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14

Set Up Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15

Append the License to Your license.dat File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15

Specify the License File in the Quartus II Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15

Example Simulation and Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16

Example Quartus II Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16

Example Simulation with Test Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16

Chapter 3. Specifications

HyperTransport Technology Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

HT Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2

HT Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3

HyperTransport MegaCore Function Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3

Physical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4

Synchronization and Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4

Protocol Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5

Clocking Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7

HyperTransport MegaCore Function Parameters and HT Link Performance . . . . . . . . . . . . . . . . . 3–10

Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–14

CSR Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–31

OpenCore Plus Time-Out Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–40

Appendix A. Parameters

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1

Parameter Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1

Device Family and Read Only Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1

Base Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–2

Clocking Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–3

Advanced Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–3

iv Contents

Appendix B. Stratix Device Pin Assignments

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–1

Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–1

Appendix C. Example Design

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C–1

Additional Information

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–2

HyperTransport MegaCore Function User Guide © November 2009 Altera Corporation

Release Information

Tab le 1– 1 provides information about this release of the HyperTransport MegaCore®

function.

Table 1–1. HyperTransport MegaCore Function Release Information

Version 9.1

Release Date November 2009

Ordering Code IP-HT

Product ID(s) 0098

Vendor ID(s) 6AF7

Altera previous version of each MegaCore function. Any exceptions to this verification are reported in the MegaCore IP Library Release Notes and Errata. Altera does not verify compilation with MegaCore function versions older than one release.

verifies that the current version of the Quartus® II software compiles the

1. About this MegaCore Function

Item Description

c The HyperTransport MegaCore function is scheduled for product obsolescence and

discontinued support as described in PDN0906. Therefore, Altera does not recommend use of this IP in new designs. For more information about Altera’s current IP offering, refer to Altera’s Intellectual Property website.

Device Family Support

MegaCore functions provide either full or preliminary support for target Altera device families:

■ Full support means the MegaCore function meets all functional and timing

requirements for the device family and may be used in production designs.

■ Preliminary support means the MegaCore function meets all functional

requirements, but may still be undergoing timing analysis for the device family; it may be used in production designs with caution.

Tab le 1– 2 shows the level of support offered by the HyperTransport MegaCore

function for each of the Altera device families.

Table 1–2. Device Family Support

Stratix

II Full

Stratix

Stratix II GX Preliminary

Stratix GX Full

Other device families No support

Device Family Support

Full

Preliminary

1–2 Chapter 1: About this MegaCore Function

Introduction

The HyperTransport MegaCore function implements high-speed packet transfers between physical (PHY) and link-layer devices, and is fully compliant with the HyperTransport I/O Link Specification, Revision 1.03. This MegaCore function allows designers to interface to a wide range of HyperTransport™ technology (HT) enabled devices quickly and easily, including network processors, coprocessors, video chipsets, and ASICs.

Features

The HyperTransport MegaCore function has the following features:

■ 8-bit fully integrated HT end-chain interface

■ Packet-based protocol

■ Dual unidirectional point-to-point links

■ Up to 16 Gigabits per second (Gbps) throughput (8 Gbps in each direction)

■ 200, 300, and 400 MHz DDR links in Stratix and Stratix GX devices

■ 200, 300, 400, and 500 MHz DDR links in Stratix II and Stratix II GX devices

■ Low-swing differential signaling with 100- differential impedance

■ Hardware verified with HyperTransport interfaces on multiple industry standard

processor and bridge devices

■ Fully parameterized MegaCore function allows flexible, easy configuration

■ Fully optimized for the Altera Stratix II, Stratix, Stratix GX, and Stratix II GX

device families

■ Application-side interface uses the Altera Atlantic

■ Manages HT flow control, optimizing performance and ease of use

■ Independent buffering for each HT virtual channel

■ Automatic handling of HT ordering rules

■ Stalling of one virtual channel does not delay other virtual channels (subject to

interface standard

ordering rules)

■ Flexible parameterized buffer sizes, allowing customization depending on

system requirements

■ User interface has independent interfaces for the HT virtual channels, allowing

independent user logic design

■ Cyclic redundancy code (CRC) generation and checking to preserve data integrity

■ Integrated detection and response to common HT error conditions

■ CRC errors

■ End-chain errors

■ Fully integrated HT configuration space includes all required configuration space

registers and HT capabilities list registers

HyperTransport MegaCore Function User Guide © November 2009 Altera Corporation

Preliminary

Chapter 1: About this MegaCore Function 1–3

Performance

■ 32-bit and 64-bit support across all base address registers (BARs)

■ Automatically handles all CSR space accesses

■ Verilog HDL and VHDL simulation support

OpenCore Plus Evaluation

With the Altera free OpenCore Plus evaluation feature, you can perform the following actions:

■ Simulate the behavior of a megafunction (Altera MegaCore function or AMPP

megafunction) within your system

■ Verify the functionality of your design, as well as quickly and easily evaluate its

size and speed

■ Generate time-limited device programming files for designs that include

MegaCore functions

■ Program a device and verify your design in hardware

You only need to purchase a license for the MegaCore function when you are completely satisfied with its functionality and performance, and want to take your design to production.

™

f For more information about OpenCore Plus hardware evaluation using the

HyperTransport MegaCore function, refer to “OpenCore Plus Time-Out Behavior” on

page 3–40 and AN 320: OpenCore Plus Evaluation of Megafunctions.

Performance

The HyperTransport MegaCore function uses 20 differential I/O pin pairs and 2 single-ended I/O pins, requiring 42 pins total. Tab le 1– 3 through Table 1–5 show typical performance and adaptive look-up table (ALUT) or logic element (LE) usage for the HyperTransport MegaCore function in StratixIIGX, StratixII, Stratix, and Stratix GX devices respectively, using the Quartus

Tab le 1– 3 shows the maximum supported data rates in megabits per second (Mbps)

by device family and speed grade.

Table 1–3. Maximum Supported HyperTransport Data Rates (Note 1)

Speed Grade

Device Family

-3 -4 -5 -6 -7 -8

Stratix II GX devices 1000 Mbps 1000 Mbps 800 Mbps N/A (2) N/A (2) N/A (2) Stratix II devices 1000 Mbps 1000 Mbps 800 Mbps N/A (2) N/A (2) N/A (2) Stratix devices

N/A (2) N/A (2) 800 Mbps 800 Mbps 600 Mbps 400 Mbps

(Flip-Chip packages) Stratix devices

N/A (2) N/A (2) N/A (2) 600 Mbps 400 Mbps 400 Mbps

(Wire Bond packages) Stratix GX devices N/A (2) N/A (2) 800 Mbps 800 Mbps 600 Mbps N/A (2)

Notes to Table 1–3:

(1) Rates are per interface bit. Multiply by eight to calculate the uni-directional data rate of an 8-bit interface. (2) Devices of this speed grade are not offered in this device family.

II software version 7.1.

Preliminary

1–4 Chapter 1: About this MegaCore Function

Performance

Tab le 1– 4 shows performance and device utilization for the HyperTransport

MegaCore function in Stratix II and Stratix II GX devices.

Table 1–4. HyperTransport MegaCore Function Performance in Stratix II and Stratix II GX Devices

Parameters

Posted

Buffers

Non-Posted

Buffers

Response

Buffers

Clocking

Option (1) M4K M512

84 4Shared

Combinational

ALUTs

(2)

Logic

Registers

3,500 5,200 12 0 500 125 (4)

Memory

HT Link

(MHz)

MAX

(3)

User

Interface

(MHz)

MAX

(3)

Rx/Tx/Ref

84 4Shared

3,500 5,200 14 0 500 125 (4)

Ref/Tx

84 4Shared

3,600 5,400 16 0 500 > 150

Rx/Tx

88 8Shared

4,000 6,000 16 0 500 > 150

Rx/Tx

16 8 8 Shared

4,100 6,200 12 0 500 125 (4)

Rx/Tx/Ref

16 8 8 Shared

4,100 6,200 14 0 500 125 (4)

Ref/Tx

16 8 8 Shared

4,200 6,400 16 0 500 > 150

Rx/Tx

Notes to Table 1–4:

(1) Refer to “Clocking Options” on page 3–7 for more information about these options. (2) Other parameters (BAR configurations, etc.) vary the ALUT and Logic Register utilization numbers by approximately +/- 200. (3) Figures for -3 speed grade devices only. (4) When using the Shared Rx/Tx/Ref and Shared Ref/Tx options, the user interface frequency is limited to exactly the HT frequency divided by

four.

Tab le 1– 5 shows performance and device utilization for the HyperTransport

MegaCore function in Stratix and Stratix GX devices.

Table 1–5. HyperTransport MegaCore Function Performance in Stratix and Stratix GX Devices

User Interface f

Posted

Buffers

Non-Posted

Buffers

Parameters Utilization HT Link f

Response

Buffers

Clocking Option

(1)

LEs

(2)

M4K

Blocks

-5 -6 -5 -6

(MHz)

MAX

Speed Grade

(MHz)

8 4 4 Shared Rx/Tx/Ref 7,500 12 400 400 100 (3) 100 (3) 8 4 4 Shared Ref/Tx 7,600 14 400 400 100 (3) 100 (3) 8 4 4 Shared Rx/Tx 7,900 16 400 400 > 125 > 100

8 8 8 Shared Rx/Tx 8,900 16 400 400 > 125 > 100 16 8 8 Shared Rx/Tx/Ref 9,400 12 400 400 100 (3) 100 (3) 16 8 8 Shared Ref/Tx 9,500 14 400 400 100 (3) 100 (3) 16 8 8 Shared Rx/Tx 9,700 16 400 400 > 125 > 100

Notes to Table 1–5:

(1) Refer to “Clocking Options” on page 3–7 for more information about these options. (2) Other parameters (BAR configurations etc.) vary the LE utilization by approximately +/- 200 LEs. (3) When using the Shared Rx/Tx/Ref and Shared Ref/Tx options, the user interface frequency is limited to exactly the HT frequency divided by four.

MAX

HyperTransport MegaCore Function User Guide © November 2009 Altera Corporation

Preliminary

Design Flow

doc

Contains the documentation for the HyperTransport MegaCore function.

example

Contains the design example for the HyperTransport MegaCore function

lib

Contains encrypted lower-level design files.

Contains the Altera MegaCore IP Library and third-party IP cores.

<path>

Installation directory.

altera

Contains the Altera MegaCore IP Library.

common

Contains shared components.

Contains the HyperTransport HyperTransport MegaCore function files and documentation.

f For system requirements and installation instructions, refer to Altera Software

2. Getting Started

To evaluate the HyperTransport MegaCore function using the OpenCore Plus feature, include these steps in your design flow:

1. Obtain and install the HyperTransport MegaCore function.

The HyperTransport MegaCore function is part of the MegaCore IP Library, which is distributed with the Quartus II software and downloadable from the Altera website,

www.altera.com.

Installation and Licensingon the Altera website at

www.altera.com/literature/lit-qts.jsp.

Figure 2–1 shows the directory structure after you install the HyperTransport

MegaCore function, where <path> is the installation directory. The default installation directory on Windows is C:\altera\<version number>; on Linux it is /opt/altera<version number>.

Figure 2–1. Directory Structure

2. Create a custom variation of the HyperTransport MegaCore function.

f For more information about IP functional simulation models, refer to the Simulating

3. Implement the rest of your design using the design entry method of your choice.

4. Use the IP functional simulation model to verify the operation of your design.

Altera IP in Third-Party Simulation Tools chapter in volume 3 of the Quartus II Handbook.

5. Use the Quartus II software to compile your design.

2–2 Chapter 2: Getting Started

MegaCore Function Walkthrough

1 You can also generate an OpenCore Plus time-limited programming file,

which you can use to verify the operation of your design in hardware.

6. Purchase a license for the HyperTransport MegaCore function.

After you have purchased a license for the HyperTransport MegaCore function, follow these additional steps:

1. Set up licensing.

2. Generate a programming file for the Altera device(s) on your board.

3. Program the Altera device(s) with the completed design.

MegaCore Function Walkthrough

This walkthrough explains how to create a custom variation using the Altera HyperTransport IP Toolbench and the Quartus II software, and simulate the function using an IP functional simulation model and the ModelSim software. When you are finished generating your custom variation of the function, you can incorporate it into your overall project.

1 IP Toolbench allows you to select only legal combinations of parameters, and warns

you of any invalid configurations.

In this walkthrough, you follow these steps:

■ Create a New Quartus II Project

■ Launch the MegaWizard Plug-in Manager

■ Step 1: Parameterize

■ Step 2: Set Up Simulation

■ Step 3: Generate

■ Simulate the Design

1 To generate a wrapper file and IP functional simulation model using default values,

omit the procedure described in “Step 1: Parameterize” on page 2–5.

Create a New Quartus II Project

Create a new Quartus II project with the New Project Wizard, which specifies the working directory for the project, assigns the project name, and designates the name of the top-level design entity.

To create a new project, perform the following steps:

1. On the Windows Start menu, select Programs > Altera > Quartus II <version> to

start the Quartus II software. Alternatively, you can use the Quartus II Web Edition software.

2. In the Quartus II window, on the File menu, click New Project Wizard. If you did not turn it off previously, the New Project Wizard: Introduction page appears.

3. On the New Project Wizard Introduction page, click Next.

HyperTransport MegaCore Function User Guide © November 2009 Altera Corporation

Chapter 2: Getting Started 2–3

MegaCore Function Walkthrough

4. On the New Project Wizard: Directory, Name, Top-Level Entity page, enter the following information:

a. Specify the working directory for your project. For example, this walkthrough

uses the C:\altera\projects\ht_project directory.

b. Specify the name of the project. This walkthrough uses ht_example for the

project name.

1 The Quartus II software automatically specifies a top-level design entity

that has the same name as the project. This walkthrough assumes that the names are the same.

5. Click Next to close this page and display the New Project Wizard: Add Files page.

1 When you specify a directory that does not already exist, a message asks if

the specified directory should be created. Click Yes to create the directory.

6. Click Next to close this page and display the New Project Wizard: Family and Device Settings page.

7. On the New Project Wizard: Family & Device Settings page, perform the following steps:

a. in the Family list, select the target device family.

b. Under Ta r g e t d e v i c e , turn on Specific device selected in ’Available devices’

list.

c. In the Available devices list, select a device.

8. The remaining pages in the New Project Wizard are optional. Click Finish to complete the Quartus II project.

You have finished creating your new Quartus II project.

Launch the MegaWizard Plug-in Manager

To launch the MegaWizardTM Plug-in Manager in the Quartus II software, perform the following steps:

1. On the To ol s menu, click MegaWizard Plug-In Manager. The MegaWizard Plug-In Manager displays, as shown in Figure 2–2.

1 Refer to Quartus II Help for more information about how to use the

MegaWizard Plug-In Manager.

2–4 Chapter 2: Getting Started

Figure 2–2. MegaWizard Opening Screen

MegaCore Function Walkthrough

2. Choose Create a new custom megafunction variation and click Next.

3. Under Interfaces in the HyperTransport folder, click the HT v9.1 component.

4. Choose the device family you want to use for this MegaCore function variation, for example, Stratix II GX. Your selection should match the device family you selected in step 7 on page 2–3 when creating the project.

5. Select the output file type for your design; the wizard supports VHDL and Verilog HDL.

6. The MegaWizard Plug-in Manager shows the project path that you specified in the New Project Wizard. Append a variation name for the MegaCore function output files <project path>\<variation name>. For this walkthrough, to create a project that includes only a single HyperTransport MegaCore function with no additional logic, define <variation name> to be ht_example to match the project name.

Figure 2–3 shows the wizard after you have made these settings.

HyperTransport MegaCore Function User Guide © November 2009 Altera Corporation

Chapter 2: Getting Started 2–5

MegaCore Function Walkthrough

Figure 2–3. Select the MegaCore Function

7. Click Next to launch the IP Toolbench for the HyperTransport MegaCore function.

Figure 2–4. IP Toolbench

Step 1: Parameterize

To parameterize your MegaCore function, follow these steps:

1. In the IP Toolbench, click Step 1: Parameterize, as shown in Figure 2–4. The IP Toolbench wizard opens to the Device Family & Read-Only Registers tab.

2–6 Chapter 2: Getting Started

MegaCore Function Walkthrough

2. Set the target Altera device family and the values for the read-only HyperTransport configuration registers on the Device Family & Read-Only Registers tab. For this walkthrough, use the default settings, which are shown in

Figure 2–5. For more information about these parameters, refer to Table A–1 on page A–1.

Figure 2–5. Parameterize—Device Family and Read-Only Registers

3. Click Next. The Base Address Registers tab appears.

4. On the Base Address Registers tab, configure the HyperTransport BARs that define the address ranges of memory read and write request packets that your application claims from the HyperTransport interface. For this walkthrough, use the default settings, which are shown in Figure 2–6. For more information about the parameters modified by these settings, refer to Table A–2 on page A–2.

Chapter 2: Getting Started 2–7

MegaCore Function Walkthrough

Figure 2–6. Parameterize—Base Address Registers Tab

5. Click Next. The Clocking Options tab displays, as shown in Figure 2–7.

6. You set the clocking options for your application on the Clocking Options tab. For more information about the available options, refer to “Clocking Options” on

page 3–7 and Tabl e A – 3 o n pa ge A–3 . For this walkthrough, use the default

settings, which are shown in Figure 2–7.

1 HyperTransport link clock frequencies of 500 MHz are only supported in

Stratix II and Stratix II GX devices.

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MegaCore Function Walkthrough

Figure 2–7. Parameterize—Clocking Options Tab

7. Click Next. The Advanced Settings tab displays.

8. You set the receiver virtual channel buffer sizes and the maximum allowed delay from the deassertion of TxRDav_o to the assertion of TxRSop_i on the Advanced Settings tab. For more information about these parameters, refer to Table A–4 on

page A–3. For this walkthrough, use the default settings, which are shown in Figure 2–8.

Chapter 2: Getting Started 2–9

MegaCore Function Walkthrough

Figure 2–8. Parameterize—Advanced Settings Tab

9. Click Finish. The Parameterize—HyperTransport MegaCore Function Parameterize panel closes and you are returned to the IP Toolbench interface.

Step 2: Set Up Simulation

An IP functional simulation model is a cycle-accurate VHDL or Verilog HDL model file produced by the Quartus II software. The simulation model allows for fast functional simulation of IP using industry-standard VHDL and Verilog HDL simulators.

1 You may only use these simulation model output files for simulation purposes and

expressly not for synthesis or any other purposes. Using these models for synthesis creates a nonfunctional design.

To generate an IP functional simulation model for your MegaCore function, follow these steps:

1. In the IP Toolbench, click Step 2: Set Up Simulation, as shown in Figure 2–9.

2–10 Chapter 2: Getting Started

MegaCore Function Walkthrough

Figure 2–9. Set Up Simulation

2. Turn on Generate Simulation Model, as shown in Figure 2–10.

Figure 2–10. Generate Simulation Model

3. Select the language in the Language list. In this case, Ver i lo g H DL was chosen.

If you are synthesizing your design with a third-party EDA synthesis tool, you can generate a netlist for the synthesis tool to estimate timing and resource usage for this megafunction.

1. To generate a netlist, turn on Generate netlist.

2. Click OK.

Chapter 2: Getting Started 2–11

MegaCore Function Walkthrough

Step 3: Generate

To generate your MegaCore function, follow these steps:

1. In the IP Toolbench, click Step 3: Generate as shown in Figure 2–11.

Figure 2–11. Generation

The generation report lists the design files that the IP Toolbench creates, as shown in Figure 2–12.

Figure 2–12. Generation Report—HyperTransport MegaCore Function

2–12 Chapter 2: Getting Started

MegaCore Function Walkthrough

2. After the MegaCore function is generated, according to the message and progress at the bottom of the generation report window, click Exit.

3. If you are prompted to add the Quartus II IP File (.qip) to the project, click Yes .

1 If you previously turned on Automatically add Quartus II IP Files to all

projects, the .qip file is generated automatically.

You have generated an instance of the HyperTransport MegaCore function.

Tab le 2– 1 describes the IP Toolbench-generated files, which are listed in the file

<variation name>.html in your project directory.

Table 2–1. IP Toolbench Files (Note 1)

File Name (2) Description

<variation name>.vhd or .v A MegaCore function variation file, which defines a VHDL or Verilog HDL top-level description

of the custom MegaCore function. Instantiate the entity defined by this file inside your design. Include this file when compiling your design in the Quartus II software.

<variation name>_bb.v Verilog HDL black-box file for the MegaCore function variation. Use this file when using a

third-party EDA tool to synthesize your design. This file is only produced when the Verilog HDL language is selected.

<variation name>.bsf Quartus II symbol file for the MegaCore function variation. You can use this file in the

Quartus II block diagram editor.

<variation name>.cmp A VHDL component declaration file for the MegaCore function variation. Add the contents of

this file to any VHDL architecture that instantiates the MegaCore function. This file is only produced when the VHDL language is selected.

<variation name>.vo or

Verilog HDL or VHDL IP functional simulation model.

<variation name>.vho

<variation name>.qip Contains Quartus II project information for your MegaCore function variation. <variation name>.html The MegaCore function report file.

Notes to Table 2–1:

(1) These files are variation dependent; some may be absent or their names may change. (2) <variation name> is the variation name selected by the user in the MegaWizard Plug-In Manager.

1 The .qip file is generated by the MegaWizard interface and contains information

about your generated IP core. You are prompted to add this .qip file to the current Quartus II project at the time of file generation. In most cases, the .qip file contains all of the necessary assignments and information required to process the core or system in the Quartus II compiler. Generally, a single .qip file is generated for each MegaCore function.

You can now integrate your custom megafunction in your design and compile the design.

Chapter 2: Getting Started 2–13

Simulate the Design

To simulate your design, you use the IP functional simulation models generated by the IP Toolbench. The IP Functional Simulation model is the .vo or .vho file generated by the IP Toolbench, as specified in “Step 2: Set Up Simulation” on page 2–9. Add this file in your simulation environment to perform functional simulation of your custom variation of the MegaCore function.

The HyperTransport MegaCore function vector-based testbench is an example you can use to help set up your own simulation environment. You should not attempt to edit these files. For information about how to perform a simulation using this vector-based testbench, see “Example Simulation and Compilation” on page 2–16.

f For more information about IP functional simulation models, refer to the Simulating

Altera IP in Third-Party Simulation Tools chapter in volume 3 of the Quartus II Handbook.

You can use any Altera-supported third-party simulator to simulate your design and testbench.

Compile the Design

You can use the Quartus II software to compile your design. Refer to Quartus II Help for instructions on compiling your design.

The instructions in this section assume that you named your wrapper file ht_example.v using the MegaWizard Plug-In Manager. If you chose a different name, substitute that name when following the instructions.

To compile your design in the Quartus II software, perform the following steps:

1. If you are using the Quartus II software to synthesize your design, skip to step 2. If you are using a third-party synthesis tool to synthesize your design, perform the following steps:

a. Set a black box attribute for ht_example.v before you synthesize the design.

Refer to the Quartus II Help for your specific synthesis tool for instructions on setting black-box attributes.

b. Run the synthesis tool to produce an EDIF Netlist File (.edf) or Verilog Quartus

Mapping file (.vqm) for input to the Quartus II software.

c. Add the .edf or .vqm file to your Quartus II project.

2. On the Processing menu, point to Start and click Start Analysis & Elaboration to elaborate the design.

3. On the Assignments menu, click Assignment Editor.

4. If the pin names are not displayed, on the View menu, click Show All Known Pin Names.

2–14 Chapter 2: Getting Started

5. Set the I/O Standard to HyperTransport for the I/O pins that are connected to the HyperTransport wrapper ports TxCAD_o[7:0], TxCTL_o, TxClk_o, RxCAD_i[7:0], RxCTL_i, and RxClk_i, by performing the following steps:

a. In the row for the pin, double-click in the Assignment Name column.

b. In the Assignment Name list, click I/O Standard.

c. In the row for the pin, double-click in the Val u e column.

d. In the Value list, click HyperTransport.

6. Set the I/O Standard to 2.5 V for the I/O pins connected to the HyperTransport wrapper ports PwrOk and Rstn.

7. If you are compiling the HyperTransport MegaCore function variation file top-level entity in your Quartus II project, set virtual pin attributes for all of the internal interface signals of the variation.

1 An example Quartus II project that has all of the above I/O standards set,

and virtual pin and clock latency settings, is included with the HyperTransport MegaCore function installation. Refer to “Example

Quartus II Project” on page 2–16.

Program a Device

8. Turn on the Quartus II timing analysis setting Enable Clock Latency to perform correct timing analysis. Refer to Quartus II Help for instructions on how to make this assignment.

9. Set the remaining constraints in the Quartus II software, including the device, pin assignments, timing requirements, and any other relevant constraints. Refer to

Appendix B, Stratix Device Pin Assignments for more details about assigning

pins. If you have not made pin assignments for your board design, you can use the Quartus II software to automatically assign pins.

10. On the Processing menu, click Start Compilation to compile the design.

Program a Device

After you compile your design, you can program your targeted Altera device and verify your design in hardware.

With Altera's free OpenCore Plus evaluation feature, you can evaluate the HyperTransport MegaCore function before you purchase a license. OpenCore Plus evaluation allows you to generate an IP functional simulation model and produce a time-limited programming file.

You can simulate the HyperTransport MegaCore function in your design and perform a time-limited evaluation of your design in hardware.

1 For more information about OpenCore Plus hardware evaluation for the

HyperTransport MegaCore function, refer to “OpenCore Plus Time-Out Behavior” on

page 3–40 and AN320: OpenCore Plus Evaluation of Megafunctions.

Chapter 2: Getting Started 2–15

Set Up Licensing

You need purchase a license for the MegaCore function only after you are completely satisfied with its functionality and performance and want to take your design to production.

After you purchase a license for the HyperTransport MegaCore function, you can request a license file from the Altera web site at www.altera.com/licensing and install it on your computer. After you request a license file, Altera emails you a license.dat file. If you do not have Internet access, contact your local Altera representative.

To install your license, you can either append the license to your Quartus II software license.dat file or you can specify the MegaCore function’s license.dat file in the Quartus II software.

1 Before you set up licensing for the HyperTransport MegaCore function, you must

already have the Quartus II software installed on your computer with licensing set up.

Append the License to Your license.dat File

To append the license, follow these steps:

1. Close the following software if it is running on your computer:

■ Quartus II software

■ MAX+PLUS

■ LeonardoSpectrum™ synthesis tool

■ Synplify software

■ ModelSim

II software

simulator

2. Open the HyperTransport license file in a text editor. The file should contain one FEATURE line, spanning 2 lines.

3. Open your Quartus II license.dat file in a text editor.

4. Copy the FEATURE line from the HyperTransport license file and paste it in the Quartus II license file.

1 Do not delete any FEATURE lines from the Quartus II license file.

5. Save the Quartus II license file.

1 When using editors such as Microsoft Word or Notepad, ensure that the file

does not have extra extensions appended to it after you save (for example, license.dat.txt or license.dat.doc). Verify the file name in a DOS box or at a command prompt.

Specify the License File in the Quartus II Software

To specify the MegaCore function’s license file, follow these steps:

+ 53 hidden pages

Altera HyperTransport MegaCore Function User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

Release Information

1. About this MegaCore Function

Device Family Support

Introduction

Features

Performance

OpenCore Plus Evaluation

Design Flow

2. Getting Started

MegaCore Function Walkthrough

Create a New Quartus II Project

Launch the MegaWizard Plug-in Manager

Step 1: Parameterize

Step 2: Set Up Simulation

Step 3: Generate

Simulate the Design

Compile the Design

Program a Device

Set Up Licensing

Append the License to Your license.dat File

Specify the License File in the Quartus II Software