Altera Hybrid Memory Cube Controller User Manual

Hybrid Memory Cube Controller IP Core

User Guide

Last updated for Altera Complete Design Suite: 15.0

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TOC-2

About the Altera Hybrid Memory Cube Controller IP Core

About the Altera Hybrid Memory Cube Controller IP Core.............................1-1

Getting Started with the HMC Controller IP Core............................................2-1

HMC Controller IP Core Supported Features.........................................................................................1-2

HMC Controller IP Core Supported HMC Transaction Types............................................................1-3

Device Family Support................................................................................................................................1-4

IP Core Verification.....................................................................................................................................1-4

Simulation.........................................................................................................................................1-5

Hardware Testing.............................................................................................................................1-5

Performance and Resource Utilization.....................................................................................................1-5

Device Speed Grade Support......................................................................................................................1-6

Release Information.....................................................................................................................................1-6

Installing and Licensing IP Cores..............................................................................................................2-2

OpenCore Plus IP Evaluation........................................................................................................ 2-2

Specifying IP Core Parameters and Options............................................................................................2-2

HMC Controller IP Core Parameters....................................................................................................... 2-3

RX Mapping and TX Mapping Parameters..................................................................................2-5

Files Generated for Altera IP Cores...........................................................................................................2-8

Integrating Your IP Core in Your Design................................................................................................ 2-9

Pin Constraints.................................................................................................................................2-9

Required External Blocks..............................................................................................................2-10

Simulating Altera IP Cores in other EDA Tools................................................................................... 2-16

Understanding the Testbench..................................................................................................................2-18

Generating and Running the Testbench.................................................................................................2-18

Functional Description....................................................................................... 3-1

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High Level Block Diagram..........................................................................................................................3-1

Interfaces Overview.....................................................................................................................................3-2

Application Interfaces..................................................................................................................... 3-2

HMC Interface..................................................................................................................................3-2

Interface to External I2C Master....................................................................................................3-3

Control and Status Register Interface........................................................................................... 3-3

Status and Debug Interface.............................................................................................................3-3

Transceiver Control Interfaces.......................................................................................................3-3

Clocking and Reset Structure.....................................................................................................................3-4

Initialization..................................................................................................................................................3-5

M20K ECC Support.....................................................................................................................................3-6

Flow Control.................................................................................................................................................3-7

Error Detection and Management.............................................................................................................3-7

Testing Features........................................................................................................................................... 3-8

About the Altera Hybrid Memory Cube Controller IP Core

TOC-3

HMC Controller IP Core Signals........................................................................4-1

Application Interface Signals......................................................................................................................4-1

Application Request Interface........................................................................................................4-1

Application Response Interface..................................................................................................... 4-4

HMC Controller IP Core Data Path Example............................................................................. 4-7

HMC Interface Signals................................................................................................................................4-8

Signals on the Interface to the I2C Master................................................................................................4-9

Control and Status Interface Signals.......................................................................................................4-10

Status and Debug Signals..........................................................................................................................4-11

Clock and Reset Signals.............................................................................................................................4-12

Transceiver Reconfiguration Signals.......................................................................................................4-13

Signals on the Interface to the External PLLs........................................................................................ 4-15

HMC Controller IP Core Register Map..............................................................5-1

CONTROL Register.....................................................................................................................................5-2

XCVR_STATUS Register............................................................................................................................5-3

LANE_STATUS Register............................................................................................................................5-3

LINK_STATUS Register.............................................................................................................................5-4

ERROR_RESPONSE Register....................................................................................................................5-5

Interrupt Related Registers.........................................................................................................................5-5

Error and Retry Statistics Registers........................................................................................................... 5-9

HMC Controller IP Core Example Design.........................................................6-1

Additional Information......................................................................................A-1

HMC Controller IP Core User Guide Revision History....................................................................... A-1

How to Contact Altera............................................................................................................................... A-1

Typographic Conventions......................................................................................................................... A-2

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About the Altera Hybrid Memory Cube

FPGA/

ASIC

HMC Controller

100Gbps Ethernet

MAC

Hybrid Memory Cube

Ethernet

Link

FPGA/

ASIC

HMC Controller

100G Interlaken

Interlaken Link

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The Hybrid Memory Cube (HMC) specification defines a new type of memory device that provides a significant increase in bandwidth and power efficiency over existing memory architectures. The HMC specification targets high performance computers and next-generation networking equipment and provides scalability for a wide range of applications.

The Altera® HMC Controller MegaCore® IP core enables easy access to external HMC devices. HMC devices provide high bandwidth, reliable access to large amounts of memory with a small form factor, and provide significant system cost savings in high performance, memory intensive applications. The HMC Controller IP core provides a simple user interface through which you can communicate with an external HMC device to incorporate these bandwidth and performance gains in your design.

Figure 1-1: Typical HMC Controller Application

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1-2

HMC Controller IP Core Supported Features

Related Information

HMC Specification 1.1

The HMC specification is available for download from the Hybrid Memory Cube Consortium web page.

HMC Controller IP Core Supported Features

The Altera HMC Controller IP core offers the following features:

• Communicates through Altera high-speed transceivers with an external HMC device compliant with

the HMC Specification 1.1.

• Communicates with the HMC device at per-lane rates of 10 Gbps or 12.5 Gbps.

• Features Avalon® Memory-Mapped (Avalon-MM) interface to access control and status registers.

• Supports selection of a full-width variation that connects to 16 lanes of an HMC device, or a half-width variation that connects to 8 lanes of an HMC device.

• Full-width IP core variations feature a simple 512-bit client data interface, and support memory

READ and WRITE transactions with payloads of 16, 32, 64, and 128 bytes.

• Half-width IP core variations feature a simple 256-bit client data interface, and support memory

READ and WRITE transactions with payloads of 16, 32, 48, 64, 80, 96, 112, and 128 bytes.

• Supports posted and non-posted versions of ATOMIC transactions, BIT WRITE transactions, and WRITE transactions.

• Supports MODE READ and MODE WRITE transactions.

• Supports Response Open Loop Mode for receive (RX) flow control to decrease device resource requirements.

• Supports token-based transmit (TX) flow control.

• Supports poisoned packets.

• Supports reordering of transceiver lanes for board-design flexibility.

• Supports link training sequence and provides word alignment, lane alignment, and transceiver status information in real time.

• Provides fast simulation support.

• Provides real-time error statistics.

• Provides hardware reset control.

• Optionally supports ADME direct access to transceiver registers through the Quartus II System Console.

• Provides option to include ECC support in all M20K memory blocks configured in the IP core.

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To support multi-link connection to the HMC device in your design, you can configure multiple HMC Controllers to communicate with the same HMC device through separate HMC links.

For the detailed HMC specification refer to the HMC Specification 1.1.

Related Information

Hybrid Memory Cube Consortium

The HMC Specification 1.1 is available on the Hybrid Memory Cube Consortium website.

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HMC Controller IP Core Supported HMC Transaction Types

The Altera HMC Controller IP core supports all HMC transactions. The full-width variations require that you specify READ transactions and posted and non-posted WRITE transactions with a payload size of 16, 32, 64, or 128 bytes. Half-width variations support all payload sizes described in the HMC Specification v1.1.

HMC Controller To HMC Device Packet Types

The HMC Controller IP core generates the following packet types on the link to the HMC device:

• NULL FLIT

• PRET (single FLIT packet)

• IRTRY (single FLIT packet)

• READ request (single FLIT packet)

• 16-byte WRITE or Posted WRITE request (2-FLIT packet)

• 32-byte WRITE or Posted WRITE request (3-FLIT packet)

• 48-byte WRITE or Posted WRITE request (4-FLIT packet) (half-width IP core only)

• 64-byte WRITE or Posted WRITE request (5-FLIT packet)

• 80-byte WRITE or Posted WRITE request (6-FLIT packet) (half-width IP core only)

• 96-byte WRITE or Posted WRITE request (7-FLIT packet) (half-width IP core only)

• 112-byte WRITE or Posted WRITE request (8-FLIT packet) (half-width IP core only)

• 128-byte WRITE or Posted WRITE request (9-FLIT packet)

• BIT WRITE or Posted BIT WRITE request (2-FLIT packet)

• MODE READ request (single FLIT packet)

• MODE WRITE request (2-FLIT packet)

• Dual 8-byte ADD IMMEDIATE or Posted Dual 8-byte ADD IMMEDIATE request (2-FLIT packet)

• Single 16-byte ADD IMMEDIATE or Posted Single 16-byte ADD IMMEDIATE request (2-FLIT packet)

1-3

The HMC Controller IP core operates in the Response Open Loop Mode and therefore does not generate TRET packets.

HMC Device to HMC Controller Packet Types

The HMC Controller IP core can process the following packet types generated by the HMC device:

• NULL FLIT

• PRET (single FLIT packet)

• TRET (single FLIT packet)

• IRTRY (single FLIT packet)

• ERROR response (single FLIT packet)

• WRITE response (single FLIT packet)

• 16-byte READ response (2-FLIT packet)

• 32-byte READ response (3-FLIT packet)

• 48-byte READ response (4-FLIT packet) (half-width IP core only)

• 64-byte READ response (5-FLIT packet)

• 80-byte READ response (6-FLIT packet) (half-width IP core only)

• 96-byte READ response (7-FLIT packet) (half-width IP core only)

• 112-byte READ response (8-FLIT packet) (half-width IP core only)

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Device Family Support

• 128-byte READ response (9-FLIT packet)

• MODE READ response (2-FLIT packet)

• MODE WRITE response (single FLIT packet)

The HMC Controller IP core does not process other packet types. Reception of any other packet type might cause the IP core to fail.

Device Family Support

The following table lists the device support level definitions for Altera IP cores.

Table 1-1: Altera IP Core Device Support Levels

FPGA Device Families

Preliminary support — The core is verified with preliminary timing models for this device family. The IP core meets all functional requirements, but might still be undergoing timing analysis for the device family. It can be used in production designs with caution.

Final support — The IP core is verified with final timing models for this device family. The IP core meets all functional and timing requirements for the device family and can be used in production designs.

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The following table shows the level of support offered by the HMC Controller IP core for each Altera device family.

Table 1-2: HMC Controller IP Core Device Family Support

Device Family Support

Arria 10 Preliminary

All other device families No support

IP Core Verification

Before releasing a version of the HMC Controller IP core, Altera runs comprehensive regression tests in the current version of the Quartus® II software. The HMC Controller IP Core is tested in simulation and hardware to confirm functionality.

Related Information

Knowledge Base Errata for HMC Controller IP core

Exceptions to functional correctness are documented in the HMC Controller IP core errata.

Altera IP Release Notes

Changes to the HMC Controller IP core are noted in the Altera IP Release Notes starting from the Quartus II software v15.0.

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Simulation

Altera performs the following tests on the HMC Controller IP core in simulation, using the Micron HMC BFM:

• Constrained random tests that cover randomized legal payload sizes and contents

• Assertion based tests to confirm proper behavior of the IP core with respect to the specification

• Extensive coverage of packet retry functionality

Constrained random techniques generate appropriate stimulus for the functional verification of the IP core. Altera monitors line, expression, and assertion coverage metrics to ensure that all important features are verified.

Hardware Testing

Altera performs hardware testing of the key functions of the HMC Controller IP core. The Altera hardware tests of the HMC Controller IP core also ensure reliable solution coverage for hardware related areas such as performance, link initialization, and reset recovery.

Altera performs hardware testing on the Arria 10 GX FPGA Development Kit with an HMC mezannine card. A Micron HMC 15G-SR device on the mezzannine card is connected to the development board through FMC connectors.

Simulation

1-5

Performance and Resource Utilization

Table 1-3: HMC Controller IP Core FPGA Resource Utilization

Typical resource utilization for an HMC Controller IP core configured with a data rate of 10 Gbps, using the Quartus II software v15.0, targetting a 10AX115S3F45I2SGE2 device, with IP core features ADME support and M20K ECC support both turned off.

The numbers of ALMs and logic registers are rounded up to the nearest 100. The numbers of ALMs, before rounding, are the ALMs needed numbers from the Quartus II Fitter Report.

Resource Utilization

IP Core Variation

Half-width

Full-width 19700 40900 50

Related Information

• Fitter Resources Reports in the Quartus II Help Information about Quartus II resource utilization reporting, including ALMs needed.

• Quartus II Handbook, Volume 1: Design and Synthesis

ALMs Needed Dedicated Logic

Registers

11500 23600 37

M20K Blocks

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1-6

Device Speed Grade Support

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Device Speed Grade Support

Table 1-4: Minimum Recommended Device Family Speed Grades

Altera recommends that you configure the HMC Controller IP core only in the device speed grades listed in the table, or any faster (lower numbered) device speed grades that are available.

Altera does not support configuration of this IP core in slower (higher numbered) device speed grades.

IP Core Variation: Lane Rate

Device Family

10 Gbps 12.5 Gbps

Arria 10 E1, I1, E2, I2 E1, I1

Release Information

Table 1-5: HMC Controller IP Core Current Release Information

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Item Value

Version 15.0

Release Date May 2014

Ordering Code Full-width: IP-HMCSR15FW

Half-width: IP-HMCSR15HW

Vendor ID 6AF7

Product ID Full-width: 0122

Half-width: 0128

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The following information explains how to install, parameterize, and simulate the Altera Hybrid Memory Cube Controller IP core.

Installing and Licensing IP Cores on page 2-2

The HMC Controller IP core is available with the Quartus II software in the Altera IP Library.

Specifying IP Core Parameters and Options on page 2-2

The HMC Controller IP core supports the standard customization and generation process. This IP core is not supported in Qsys.

HMC Controller IP Core Parameters on page 2-3

The HMC Controller parameter editor provides the parameters you can set to configure the HMC Controller IP core and simulation testbenches.

Files Generated for Altera IP Cores on page 2-8

The Quartus II software generates multiple files during generation of your IP core variation.

Integrating Your IP Core in Your Design on page 2-9

To ensure the HMC Controller IP core functions correctly in hardware, you must connect additional blocks to your IP core and assign device pins in order.

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Simulating Altera IP Cores in other EDA Tools on page 2-16

The Quartus II software supports RTL and gate-level design simulation of Altera IP cores in supported EDA simulators. Simulation involves setting up your simulator working environment, compiling simulation model libraries, and running your simulation.

Understanding the Testbench on page 2-18

Altera provides a testbench with the HMC Controller IP core.

Generating and Running the Testbench on page 2-18

Related Information

• HMC Controller IP Core Example Design on page 6-1 The HMC Controller example design provides an example of how to connect your IP core with an external I2C master module and an external TX PLL.

• Introduction to Altera IP Cores Provides more information about generating an Altera IP core and integrating it in your Quartus II project.

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acds

quartus - Contains the Quartus II software ip - Contains the Altera IP Library and third-party IP cores

altera - Contains the Altera IP Library source code

<IP core name> - Contains the IP core source files

2-2

Installing and Licensing IP Cores

The Altera IP Library provides many useful IP core functions for your production use without purchasing an additional license. Some Altera MegaCore IP functions require that you purchase a separate license for production use. However, the OpenCore® feature allows evaluation of any Altera IP core in simulation and compilation in the Quartus® II software. After you are satisfied with functionality and perfformance, visit the Self Service Licensing Center to obtain a license number for any Altera product.

Figure 2-1: IP Core Installation Path

Note: The default IP installation directory on Windows is <drive>:\altera\<version number>; on Linux it is

<home directory>/altera/ <version number>.

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Related Information

• Altera Licensing Site

• Altera Software Installation and Licensing Manual

OpenCore Plus IP Evaluation

Altera's free OpenCore Plus feature allows you to evaluate licensed MegaCore IP cores in simulation and hardware before purchase. You need only purchase a license for MegaCore IP cores if you decide to take your design to production. OpenCore Plus supports the following evaluations:

• Simulate the behavior of a licensed IP core in your system.

• Verify the functionality, size, and speed of the IP core quickly and easily.

• Generate time-limited device programming files for designs that include IP cores.

• Program a device with your IP core and verify your design in hardware. OpenCore Plus evaluation supports the following two operation modes:

• Untethered—run the design containing the licensed IP for a limited time.

• Tethered—run the design containing the licensed IP for a longer time or indefinitely. This requires a connection between your board and the host computer.

All IP cores that use OpenCore Plus time out simultaneously when any IP core in the design times

Note:

out.

Specifying IP Core Parameters and Options

The HMC Controller parameter editor allows you to quickly configure your custom IP variation. Use the following steps to specify IP core options and parameters in the Quartus II software.

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Getting Started with the HMC Controller IP Core

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HMC Controller IP Core Parameters

2-3

1. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize. The parameter editor appears.

2. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.qsys. Click OK.

3. Specify the parameters and options for your IP variation in the parameter editor, including one or more of the following. Refer to the Parameters section for information about specific IP core parameters.

• Optionally select preset parameter values if provided for your IP core. Presets specify initial

parameter values for specific applications.

• Specify parameters defining the IP core functionality, port configurations, and device-specific

features.

• Specify options for processing the IP core files in other EDA tools.

4. Click Generate HDL, the Generation dialog box appears.

5. Specify output file generation options, and then click Generate. The IP variation files generate

according to your specifications.

6. To generate an HDL instantiation template that you can copy and paste into your text editor, click Generate > HDL Example.

7. Click Finish. The parameter editor adds the top-level .qsys file to the current project automatically. If you are prompted to manually add the .qsys file to the project, click Project > Add/Remove Files in Project to add the file.

8. After generating and instantiating your IP variation, make appropriate pin assignments to connect

ports.

HMC Controller IP Core Parameters

The HMC Controller parameter editor provides the parameters you can set to configure the HMC Controller IP core and simulation testbenches.

Table 2-1: HMC Controller IP Core Parameters

Parameters for customizing the HMC Controller IP core in the HMC Controller parameter editor.

Parameter Type Range Default Setting Parameter Description

Lanes Integer • 8

• 16

Data rate String • 10 Gbps

• 12.5 Gbps

16 Selects half-width (8 lanes) or

full-width (16 lanes) function‐ ality.

10 Gbps Selects the data rate on each

lane.

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HMC Controller IP Core Parameters

Parameter Type Range Default Setting Parameter Description

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CDR

String • 312.5 MHz

reference clock

RX mapping 64-bit

value

TX mapping 64-bit

value

(at 10 Gbps only)

• 390.625 MHz (at 12.5 Gbps only)

• 125 MHz

• 156.25 MHz

• 166.67 MHz

125 MHz Selects the input reference clock

for the RX CDR PLL. You must drive the rx_cdr_refclk0 input signal at the frequency you specify for this parameter.

In addition, your design must derive this clock, the external transceiver TX PLL reference clock, and the REFCLKP and

REFCLKN input signals of the

external HMC device from the same clock source.

0xFEDCBA9876543210

Selects the RX lane mapping. Use caution in modifying this

parameter. Refer to RX and TX Mapping Parameters.

0xFEDCBA9876543210

Selects the TX lane mapping. Use caution in modifying this

parameter. Refer to RX and TX

Mapping Parameters.

Enable Altera Debug Master Endpoint (ADME)

Boolean

• True

• False

False Specifies whether the IP core

turns on the ADME feature in the embedded Arria 10 Native PHY IP core that configures the transceivers.

The ADME feature enables Native PHY register program‐ ming with the Altera System Console. For more information, refer to the Arria 10 Transceiver PHY User Guide.

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RX Mapping and TX Mapping Parameters

Parameter Type Range Default Setting Parameter Description

2-5

Enable M20K ECC

Boolean • True

• False

False

support

Related Information

• Arria 10 Transceiver PHY User Guide

Provides information about the Arria 10 ADME feature.

• Embedded Memory Blocks in Arria 10 Devices

Provides information about the Arria 10 M20K block ECC feature.

Specifies whether the IP core supports the ECC feature in the Arria 10 M20K memory blocks that are configured as part of the IP core.

You can turn on this parameter to enhance data reliability by enabling single-error correct, double-adjacent-error correct, and triple-adjacent-error detect ECC functionality in the M20K memory blocks configured in your IP core. You can turn off this parameter to decrease latency and resource utilization.

RX Mapping and TX Mapping Parameters

The HMC Controller IP core provides the RX mapping and TX mapping parameters for flexibility in board design.

The default values of these parameters specify the correct IP core behavior when the HMC device

LxTX[] output signal connects to the HMC Controller IP core hmc_lxrx[] input port, and the LxRX[] input signal connects to the HMC Controller IP core hmc_lxtx[] output port, for each .

However, if your design constraints prevent you from connecting these signals as expected, you can instead modify one or both HMC Controller IP core mapping parameters to accommodate the nonstandard connection.

The Quartus II Fitter prevents you from mapping the HMC Controller IP core lanes to Arria 10

Note:

device transceiver channels out of order. Therefore, these two parameters only compensate for outof-order connections on the board between the Arria 10 transceiver pins and the HMC device ports.

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FPG A

HMC Controller

Hybrid Memory Cube

hmc_lxtx[0] LxRX[0]

LxTX[0]hmc_lxrx[0]

hmc_lxtx[1] LxRX[1]

LxTX[1]hmc_lxrx[1]

hmc_lxtx[2] LxRX[2]

LxTX[2]hmc_lxrx[2]

hmc_lxtx[3] LxRX[3]

LxTX[3]hmc_lxrx[3]

hmc_lxtx[F] LxRX[F]

LxTX[F]hmc_lxrx[F]

hmc_lxtx[E] LxRX[E]

LxTX[E]hmc_lxrx[E]

hmc_lxtx[D] LxRX[D]

LxTX[D]hmc_lxrx[D]

hmc_lxtx[C] LxRX[C]

LxTX[C]hmc_lxrx[C]

. . . . . . . . .

RX mapping value 0xFEDCBA9876543210 TX mapping value 0xFEDCBA9876543210

2-6

RX Mapping and TX Mapping Parameters

Figure 2-2: Default RX and TX Mapping Parameter Values

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If the HMC device LxTX[] output signal connects to the HMC Controller IP core hmc_lxrx[<k>] input port, the value in bits [(4+3):(4)] (nibble ) of the RX mapping parameter is 4'h<k>. Therefore, the default value of the RX mapping parameter is 0xFEDCBA9876543210, indicating that

LxTX[F] connects to hmc_lxrx[F], LxTX[E] connects to hmc_lxrx[E], and so on.

If the HMC device LxRX[] input signal connects to the HMC Controller IP core hmc_lxtx[<k>] input port, the value in bits [(4+3):(4)] (nibble ) of the TX mapping parameter is 4'h<k>. Therefore, the default value of the TX mapping parameter is 0xFEDCBA9876543210, indicating that LxRX[F] connects to hmc_lxtx[F], LxRX[E] connects to hmc_lxtx[E], and so on.

Example: Non-Default RX Mapping Parameter Value

Table 2-2: Non-Default RX Connections

HMC Device Output Signal IP Core Input Signal

LxTX[2] hmc_lxrx[0] LxTX[1] hmc_lxrx[2] LxTX[0] hmc_lxrx[1]

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FPGA

HMC Controller

Hybrid Memory Cube

hmc_lxtx[0] LxRX[0]

LxTX[0]hmc_lxrx[0]

hmc_lxtx[1] LxRX[1]

LxTX[1]hmc_lxrx[1]

hmc_lxtx[2] LxRX[2]

LxTX[2]hmc_lxrx[2]

hmc_lxtx[3] LxRX[3]

LxTX[3]hmc_lxrx[3]

hmc_lxtx[F] LxRX[F]

LxTX[F]hmc_lxrx[F]

hmc_lxtx[E] LxRX[E]

LxTX[E]hmc_lxrx[E]

hmc_lxtx[D] LxRX[D]

LxTX[D]hmc_lxrx[D]

hmc_lxtx[C] LxRX[C]

LxTX[C]hmc_lxrx[C]

. . . . . . . . .

RX mapping value 0xFEDCBA9876543021 TX mapping value 0xFEDCBA9876543210

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RX Mapping and TX Mapping Parameters

Figure 2-3: Non-Default RX Mapping Parameter Value Example

If you connect the IP core hmc_lxrx[2:0] input signals according to the table, and connect all other IP core hmc_lxrx[] input ports to the corresponding HMC device LxTX[] output ports, you would set the value of the RX mapping parameter to 0xFEDCBA9876543021 to compensate for the nonstandard connection.

Note: The RX mapping parameter specifies the HMC device lane by position and the IP core lane by

value. The figure illustrates a mapping parameter value of 0xFED.......43021 and not a value of

0xFED....43102.

2-7

Example: Non-Default TX Mapping Parameter Value

Table 2-3: Non-Default TX Connections

HMC Device Input Signal IP Core Output Signal

LxRX[2] hmc_lxtx[0] LxRX[1] hmc_lxtx[2] LxRX[0] hmc_lxtx[1]

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FPGA

HMC Controller

Hybrid Memory Cube

hmc_lxtx[0] LxRX[0]

LxTX[0]hmc_lxrx[0]

hmc_lxtx[1] LxRX[1]

LxTX[1]hmc_lxrx[1]

hmc_lxtx[2] LxRX[2]

LxTX[2]hmc_lxrx[2]

hmc_lxtx[3] LxRX[3]

LxTX[3]hmc_lxrx[3]

hmc_lxtx[F] LxRX[F]

LxTX[F]hmc_lxrx[F]

hmc_lxtx[E] LxRX[E]

LxTX[E]hmc_lxrx[E]

hmc_lxtx[D] LxRX[D]

LxTX[D]hmc_lxrx[D]

hmc_lxtx[C] LxRX[C]

LxTX[C]hmc_lxrx[C]

. . . . . . . . .

RX mapping value 0xFEDCBA9876543210 TX mapping value 0xFEDCBA9876543021

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Files Generated for Altera IP Cores

Figure 2-4: Non-Default TX Mapping Parameter Value Example

If you connect the HMC Controller IP core hmc_lxtx[2:0] output signals according to the table, and connect all other IP core hmc_lxtx[] output ports to the corresponding HMC device LxRX[] input ports, you would set the value of the TX mapping parameter to 0xFEDCBA9876543021 to compensate for the non-standard connection.

Note: The TX mapping parameter specifies the HMC device lane by position and the IP core lane by

value. The figure illustrates a mapping parameter value of 0xFED.......43021 and not a value of

0xFED....43102.

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Use caution in modifying these parameters. In loopback configurations, you must ensure the RX mapping and TX mapping parameters specify reversed mappings. Otherwise, the IP core downstream of

the RX lane swapper appears to receive data on the wrong lanes.

Files Generated for Altera IP Cores

The Quartus II software generates multiple files during generation of your IP core variation.

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Getting Started with the HMC Controller IP Core

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<your_ip >.cmp - VHDL component declaration file

<your_ip >.ppf - XML I/O pin information file <your_ip >.qip - Lists IP synthesis files <your_ip >.sip - Lists files for simulation

<your_ip >.v or .vhd Top-level IP synthesis file

<your_ip >.v or .vhd Top-level simulation file

<simulator_setup_scripts >

<your_ip >.qsys - System or IP integration file

<your_ip >_bb.v - Verilog HDL black box EDA synthesis file <your_ip >_inst.v or .vhd - Sample instantiation template

<your_ip >_generation.rpt - IP generation report <your_ip >.debuginfo - Contains post-generation information

<your_ip >.html - Connection and memor y map data <your_ip >.bsf - Block symbol schematic <your_ip >.spd - Combines individual simulation scripts

<your_ip >.sopcinfo - Software tool-chain integration file

<your_ip>

IP variation files

sim

Simulation files

synth

IP synthesis files

Simulator scripts

<ip subcores> n

Subcore libraries

sim

Subcore

Simulation files

synth

Subcore

synthesis files

<your_ip> n

IP variation files

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Figure 2-5: IP Core Generated Files

Integrating Your IP Core in Your Design

2-9

Integrating Your IP Core in Your Design

To ensure the HMC Controller IP core functions correctly in hardware, you must connect additional blocks to your IP core and assign device pins in order.

Pin Constraints

Getting Started with the HMC Controller IP Core

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Required External Blocks

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When you integrate your HMC Controller IP core instance in your design, you must make appropriate pin assignments. You can create a virtual pin to avoid making specific pin assignments for top-level signals while you are simulating and not ready to map the design to hardware.

When you are ready to map the design to hardware, you must enforce the following constraints:

• Adjacent HMC Controller lanes must map to adjacent Altera device pins. You cannot swap the lane

order by mapping lanes to other Altera device pins. Instead, use the RX mapping and TX mapping parameters to compensate for board design issues.

• The lanes of an HMC Controller IP core must be configured in no more than three transceiver blocks. To enforce this constraint, you must configure IP core lanes in transceiver channels with the following restrictions:

• Lane 0 of a full-width HMC Controller IP core must map to channel 0, 1, or 2 of a transceiver

block.

• If Lane 0 maps to channel 0, then HMC Controller Lane 1 must map to channel 1 of the same transceiver block (transceiver block N), and Lane 15 maps to channel 3 of the transceiver block N+2.

• If Lane 0 maps to channel 1, then HMC Controller Lane 1 must map to channel 2 of the same transceiver block (transceiver block N), and Lane 15 maps to channel 4 of the transceiver block N+2.

• If Lane 0 maps to channel 2, then HMC Controller Lane 1 must map to channel 3 of the same transceiver block (transceiver block N), and Lane 15 maps to channel 5 of the transceiver block N+2.

• Lane 0 of a half-width HMC Controller IP core can map to any channel. If it maps to any of channels 0, 1, 2, 3, or 4, the IP core lanes are configured in two transceiver blocks.

Required External Blocks

The HMC Controller IP core requires that you define and instantiate the following additional modules:

• One or more external PLL IP cores to configure transceiver TX PLLs for all of the HMC lanes. Although the hardware these IP cores configure might physically be part of the device transceiver, you must instantiate them in software separately from the HMC Controller IP core. This requirement supports the configuration of multiple Altera IP cores using the same transceiver block in the device.

• An external I2C master module in your design. Your design must include this module to initialize the HMC device to which your IP core connects.

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Getting Started with the HMC Controller IP Core

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HMC Controller IP Core

FPGA

FIFO

Control and

Status Interface

InitializationInitialization

State Machine State Machine

Arria 10

Transceiver

Reconfiguration

Interface

Avalon-MM

Application

Interface

TX Lane Swapper

RX Lane Swapper

Avalon-MM

I C Master

Transceiver

x8 or x16

TX PLLs

HMC Device

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Adding the External PLL

Figure 2-6: Required External Blocks

The required external blocks appear darker than the other blocks in the figure. The external TX PLL IP core configures an ATX PLL in the device transceiver or an fPLL in Transceiver mode.

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Adding the External PLL

The HMC Controller IP core requires that you generate and connect external transceiver PLL IP cores. You must generate the number of PLL IP cores required to clock the transceiver channels that are configured as HMC Controller IP core lanes. Each ATX PLL IP core configures the transceiver PLL in the transceiver in hardware, but you must generate the transceiver PLL IP core separately from the HMC

Getting Started with the HMC Controller IP Core

Controller IP core in software. You can also configure an fPLL in transceiver mode. If you do not generate and connect the transceiver PLL IP core or cores, the HMC Controller IP core does not function correctly in hardware.

You can use the IP Catalog to generate each external PLL IP core that configures a transceiver PLL on the device. In the IP Catalog, select Arria 10 Transceiver ATX PLL or Arria 10 fPLL.

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Adding the External PLL

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In the transceiver PLL parameter editor, you must follow the instructions in the Arria 10 Transceiver PHY User Guide to configure the PLL IP core in the xN bonding configuration or in the PLL feedback

compensation bonding configuration. In addition, you must set the following parameter values:

• PLL output frequency to one half of the per-lane data rate of the IP core variation. The transceiver performs dual edge clocking, using both the rising and falling edges of the input clock from the PLL. Therefore, this PLL output frequency setting drives the transceiver with the correct clock for the lanes that connect to the HMC device.

• PMA interface width to 32.

• PLL integer reference clock frequency (ATX PLL) or Desired reference clock frequency (fPLL) depends on the bonding scheme.

• In the xN bonding scheme, Altera recommends that you specify one of 125 MHz, 156.25 MHz, or

166.67 MHz. You can theoretically specify any reference clock frequency from which the PLL can generate the required output clock frequency. However, you must drive this TX PLL and the RX CDR PLL (rx_cdr_refclk0 input signal to the HMC Controller IP core) and the HMC device reference clock input signals (REFCLKP and REFCLKN) from the same clock source.

• In the PLL feedback compensation bonding scheme, you must specify the lane rate divided by 32.

In this mode, the PLL is configured to bypass the reference clock divider. Therefore, if you select this bonding scheme, the reference clock frequency must be the lane rate divided by the PMA width, which is 32.

Note: You must drive the external PLL reference clock input signal at the frequency you specify for

this parameter.

Table 2-4: Required PLL Reference Clock Frequency with PLL Feedback Compensation Bonding

Lane Rate Required PLL Reference Clock Frequency

10 Gbps 312.5 MHz

12.5 Gbps 390.625 MHz

The number of external PLLs you must define depends on the bonding mode you specify. In xN bonding mode, a single PLL is sufficient to drive the channels in the configured transceiver blocks. Recall that your HMC link TX serial lanes must be configured in order in adjacent physical transceiver channels so that these lanes configure a maximum of three transceiver blocks. You can view I/O constraints that enforce these requirements in the example design Quartus Settings File hmcc_example.qsf provided with the HMC Controller IP core.

You set the bonding mode in the PLL parameter editor. In PLL Feedback Compensation mode, each PLL output connects to the x6 network for its transceiver block through the transceiver block's Master Clock Generation Block. In xN bonding mode, the PLL output connects directly to the x6 network for its transceiver block and drives additional transceiver blocks through the xN clock network.

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Getting Started with the HMC Controller IP Core

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+ 48 hidden pages

Altera Hybrid Memory Cube Controller User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

HMC Controller IP Core Supported Features

HMC Controller IP Core Supported HMC Transaction Types

Device Family Support

IP Core Verification

Simulation

Hardware Testing

Performance and Resource Utilization

Device Speed Grade Support

Release Information

Installing and Licensing IP Cores

OpenCore Plus IP Evaluation

Specifying IP Core Parameters and Options

HMC Controller IP Core Parameters

RX Mapping and TX Mapping Parameters

Files Generated for Altera IP Cores

Integrating Your IP Core in Your Design

Pin Constraints

Required External Blocks

Adding the External PLL