Altera Advanced SEU Detection IP Core User Manual

2015.05.04

www.altera.com

101 Innovation Drive, San Jose, CA 95134

Altera Advanced SEU Detection IP Core User Guide

ALTADVSEU

Subscribe

Send Feedback

The Altera Advanced SEU Detection IP core contains the following features:

• Hierarchy tagging—Enables tagging of logical hierarchies and specifying their criticality relative to
SEU.

• Sensitivity processing—Determines the criticality of an SEU detected and located by error detection
cyclical redundancy check (EDCRC) hard IP. This feature includes on and off-chip sensitivity
processing.

Table 1: Features Device Family Support

Feature Supported Device

Hierarchy tagging Stratix® IV, Arria® V, Arria V GZ, Cyclone® V, Stratix V and later.

Sensitivity processing Arria V, Arria V GZ,Cyclone V, Stratix V and later.

You can select and configure the Altera Advanced SEU Detection IP core through the IP Catalog and
parameter editor in the Quartus® II software.

Related Information

Introduction to Altera IP Cores

Functional Description

Stratix IV devices contain a 16-bit cyclic redundancy check (CRC) value per CRAM frame, and Arria V,
Cyclone V, Stratix V, and later device families contain a 32-bit CRC value per CRAM frame. The CRC
value allows the configuration engine to determine the SEU location. The Quartus II software can
generate a Sensitivity Map Header File (.smh) of the configuration regions of your design that are sensitive
to SEU.

You can instantiate the Altera Advanced SEU Detection IP core with the following configurations:

• On-Chip Lookup Sensitivity Processing—Error location reporting and lookup performed by the
FPGA.

• Off-Chip Lookup Sensitivity Processing—Error location lookup determined by an external unit (such
as a microprocessor).

On-Chip Lookup Sensitivity Processing

All device families that support SEU detection include a hard error detection block that detects soft errors
and provides the location of single-bit errors, and double-bit adjacent errors for supported devices. The

©

2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.

ISO
9001:2008
Registered

EMR

Unloader

IP Core

Advanced

SEU Detection

IP Core

User-Supplied

Memory Access

Logic

critical_error
noncritical_error
regions_report

Memory

Interface

Error

Messages

Register

Interface

CRAM CRC Error Detected

FPGA

Sensitivity Lookup

Information (SMH)

Stored in

External Memory

CRC_ERROR

2

On-Chip Lookup Sensitivity Processing

Altera Advanced SEU Detection IP core interprets the error detection register of the error detection block,
and then compares single-bit error locations with a sensitivity map. This check determines whether or not
the failure affects the device operation.

Figure 1: System Overview for On-Chip Lookup Sensitivity Processing

The Altera Advanced SEU Detection IP core accepts the content of the error message register (EMR) and
issues a query to an external memory containing the sensitivity map. The system designer is responsible
for the memory access logic and external memory.

ALTADVSEU

2015.05.04

Altera recommends that you implement an SEU detection circuit that tolerates a soft error in its logic by
instantiating two instances of the Altera Advanced SEU Detection IP core in your design. In this case, one
instance of the IP core flags errors that occur in the other instance of the IP core as “critical.”

Related Information

• Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices

Provides more information about the design security for Stratix IV devices.

• Configuration, Design Security, and Remote System Upgrades in Arria V Devices

Provides more information about the design security for Arria V devices.

• Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices

Provides more information about the design security for Cyclone V devices.

• Configuration, Design Security, and Remote System Upgrades in Stratix V Devices

Provides more information about the design security for Stratix V devices.

Altera Corporation

Altera Advanced SEU Detection IP Core User Guide

Send Feedback

clk

reset

cache_comparison_off

data
valid

error

address

read

byteenable

waitrequest

critical_error

clk

reset

cache_comparison_off

emr[66:0]

emr_valid
emr_error

mem_addr[31:0]

mem_rd
mem_bytesel[3:0]
mem_wait

critical_error

my_asd

Altera Advanced SEU Detection IP Core

noncritical_error noncritical_error

regions_report regions_report

readdata

readdatavalid

mem_data[31:0]
mem_datavalid

ALTADVSEU

2015.05.04

On-Chip Processing Signals

Figure 2: Altera Advanced SEU Detection Core Signals for On-Chip Processing

On-Chip Processing Signals

3

Table 2: Altera Advanced SEU Detection Core Signals for On-Chip Processing

Interface Signals Type Width Description

clk Input 1

• Clock input.

• Recommended frequency is 100 MHz or

Clock and reset

Cache Configu‐

ration

reset Input 1 Active-high reset.
cache_comparison_off Input 1

higher.

• Static input signal.

• Commands the IP core to bypass cache
comparison.

• You can use this signal with the internal
scrubbing feature for custom design.

emr Input 67 Error Message Register data input from the

Altera Error Message Register Unloader IP
core.

Avalon-ST

(Streaming)

Sink Interface

Signals

(1)

emr_valid Input 1 Indicates when emr data input is valid.
emr_error Input 1

• Indicates when emr data will be ignored due
to an error.

• This may occur when there is a data overrun
from the Altera EMR Unloader IP core.

(1)

The Avalon (ST) Streaming Sink Interface should be connected to the corresponding Avalon-ST Source

Altera Advanced SEU Detection IP Core User Guide

Interface of the EMR Uploader IP Core.

Send Feedback

Altera Corporation

4

On-Chip Processing Signals

Interface Signals Type Width Description

ALTADVSEU

2015.05.04

Errors Output

External
Memory

Avalon-MM

Master

noncritical_error Outpu

t

critical_error Outpu

t

regions_report Outpu

t

mem_addr

Outpu

t

mem_rd Outpu

t

mem_bytesel Outpu

t

mem_wait Input

1 Indicates that an SMH lookup determined that

the EDCRC error is in a non-critical region.

1 Indicates that an SMH lookup determined that

the EDCRC error is in a critical region.

1

• The ASD region for the error, as reported by
the SMH lookup.

• The width of this port comes from the
setting for the parameter “Largest ASD
region ID used.”

• Output to the user logic.

• Byte address of the 32-bit word to be read.

• Output to the user logic.

• Signals to the user logic to request a read
operation.

• Output to the user logic.

• A four-bit signal that selects the bytes
needed by the IP core. Use of this signal
allows 16-bit or 8-bit memories to optimize
the number of reads in cases where the IP
does not need all 32 bits. If bit 0 of mem_
bytesel is 0, then the IP core ignores bits 0 to
7 of mem_data, and similarly for bits 1 to 3
of mem_bytesel.

• Input from the user logic.

• Signals to the memory interface that the
read operation is still running. Must be high
by the first rising clock after mem_rd is
asserted to hold the IP core in a wait state.

Related Information

Altera Error Message Register Unloader IP Core User Guide

Altera Corporation

mem_data Input

mem_datavalid Input

• Input from the user logic.

• 32-bit data bus. Data must be present if
mem_wait goes high and if mem_rd returns
low.

• Input from the user logic.

• Signals that the mem_data signal contains
valid data in response to a previous mem_rd
request.

Altera Advanced SEU Detection IP Core User Guide

Send Feedback

EMR

Unloader

IP Core

Advanced

SEU Detection

IP Core

Error Message

Cache Interface

Error Message

Register Interface

CRAM CRC Error Detected

FPGA

Sensitivity Processor

(e.g., System CPU)

CRC_ERROR

Sensitivity Lookup

Information (SMH)

Stored in System Memory

ALTADVSEU

2015.05.04

Off-Chip Lookup Sensitivity Processing

The Altera Advanced SEU Detection IP core interprets the content of the error detection block’s EMR
and presents information to a system processor, which determines whether the failure affects the device
operation. The system processor implements the algorithm to perform a lookup against the .smh.

The off-chip lookup sensitivity processing consists of two components:

• Design logic to interpret content of the EMR of the CRC block and present the information to a
processor interface.

• Cache to store off-loaded content of the EMR.

Figure 3: System Overview for Off-Chip Lookup Sensitivity Processing

Off-Chip Lookup Sensitivity Processing

5

The EMR processing unit interprets the content of EMR offloaded from the CRC block by the EMR
Uploader IP core upon an SEU. The EMR processing unit writes each unique EMR value into cache, until
the cache is full. After the cache is full, it asserts a cache overflow flag to the system interface.

For each new value written into cache, the EMR processing unit asserts an interrupt to the processor. The
system processor reads the EMR value and performs a lookup against the .smh to determine the criticality
of a CRAM location. After the system processor services the interrupt, the EMR processing unit advances
the cache line and generates additional interrupt assertions, provided that there is an EMR value in cache
that has not been processed.

After SMH lookup, the system processor determines the required corrective response.

Related Information

• Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
Provides more information about the design security for Stratix IV devices.

• Configuration, Design Security, and Remote System Upgrades in Arria V Devices
Provides more information about the design security for Arria V devices.

• Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices
Provides more information about the design security for Cyclone V devices.

• Configuration, Design Security, and Remote System Upgrades in Stratix V Devices
Provides more information about the design security for Stratix V devices.

Altera Advanced SEU Detection IP Core User Guide

Send Feedback

Altera Corporation

CRC Error Writes a

Value into EMR

CPU Reads SMHSMH File

Bit Critical?

Log Event

Wait for SEU

Corrective

Action Needed?

Reset System

yes

no

yes

no

EMR Processing Unit

System-Level Response

Logic Caches EMR;

Asserts Interupt to CPU

6

Off-Chip Lookup Sensitivity Processing Operation Flow

Off-Chip Lookup Sensitivity Processing Operation Flow

Figure 4: Off-Chip Lookup Sensitivity Processing Operation Flow

ALTADVSEU

2015.05.04

Related Information

SMH Lookup on page 8

Off-Chip Processing Signals

Off-chip sensitivity processing has similar signals with on-chip sensitivity processing, with the exception
of the external memory interface; the off-chip sensitivity processing has EMR cache interface instead.

Altera Corporation

Altera Advanced SEU Detection IP Core User Guide

Send Feedback

clk

reset

cache_comparison_off

data
valid

error

data

valid

ready

error

cache_fill_level

critical_error

clk

reset

cache_comparison_off

emr[66:0]

emr_valid
emr_error

cache_data[34:0]
cache_valid
cache_ready
cache_error

cache_fill_level[3:0]

critical_error

my_asd

Altera Advanced SEU Detection IP Core

ALTADVSEU

2015.05.04

Off-Chip Processing Signals

Figure 5: Altera Advanced SEU Detection Core Signals for Off-Chip Processing

7

Table 3: Altera Advanced SEU Detection Core Signals for Off-Chip Processing

Clock and reset

Cache Configu‐

Avalon-ST

(Streaming)

Sink Interface

Signals

Errors Output critical_error Outpu

(2)

Altera Advanced SEU Detection IP Core User Guide

Send Feedback

Interface Signals Type Width Description

clk Input 1

• Clock input.

• Recommended frequency is 100 MHz or
higher.

reset Input 1 Active-high reset.
cache_comparison_off Input 1

ration

• Static input signal.

• Commands the IP core to bypass cache
comparison.

• You can use this signal with the internal
scrubbing feature for custom design.

emr Input 67 Error Message Register data input from the

Altera Error Message Register Unloader IP
core.

emr_valid Input 1 Indicates when emr data input is valid.

(2)

emr_error Input 1

t

• Indicates when emr data will be ignored due
to an error.

• This may occur when there is a data overrun
from the Altera EMR Unloader IP core.

1 Indicates that an SMH lookup determined that

the EDCRC error is in a critical region.

The Avalon (ST) Streaming Sink Interface should be connected to the corresponding Avalon-ST Source
Interface of the EMR Uploader IP Core.

Altera Corporation